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[openwrt/staging/dedeckeh.git] / target / linux / brcm2708 / patches-4.4 / 0032-MMC-added-alternative-MMC-driver.patch
1 From 231ef69db2b015b7da9994ef893090206bf5f63f Mon Sep 17 00:00:00 2001
2 From: gellert <gellert@raspberrypi.org>
3 Date: Fri, 15 Aug 2014 16:35:06 +0100
4 Subject: [PATCH 032/304] MMC: added alternative MMC driver
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 mmc: Disable CMD23 transfers on all cards
10
11 Pending wire-level investigation of these types of transfers
12 and associated errors on bcm2835-mmc, disable for now. Fallback of
13 CMD18/CMD25 transfers will be used automatically by the MMC layer.
14
15 Reported/Tested-by: Gellert Weisz <gellert@raspberrypi.org>
16
17 mmc: bcm2835-mmc: enable DT support for all architectures
18
19 Both ARCH_BCM2835 and ARCH_BCM270x are built with OF now.
20 Enable Device Tree support for all architectures.
21
22 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
23
24 mmc: bcm2835-mmc: fix probe error handling
25
26 Probe error handling is broken in several places.
27 Simplify error handling by using device managed functions.
28 Replace pr_{err,info} with dev_{err,info}.
29
30 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
31
32 bcm2835-mmc: Add locks when accessing sdhost registers
33
34 bcm2835-mmc: Add range of debug options for slowing things down
35
36 bcm2835-mmc: Add option to disable some delays
37
38 bcm2835-mmc: Add option to disable MMC_QUIRK_BLK_NO_CMD23
39
40 bcm2835-mmc: Default to disabling MMC_QUIRK_BLK_NO_CMD23
41
42 bcm2835-mmc: Adding overclocking option
43
44 Allow a different clock speed to be substitued for a requested 50MHz.
45 This option is exposed using the "overclock_50" DT parameter.
46 Note that the mmc interface is restricted to EVEN integer divisions of
47 250MHz, and the highest sensible option is 63 (250/4 = 62.5), the
48 next being 125 (250/2) which is much too high.
49
50 Use at your own risk.
51
52 bcm2835-mmc: Round up the overclock, so 62 works for 62.5Mhz
53
54 Also only warn once for each overclock setting.
55
56 mmc: bcm2835-mmc: Make available on ARCH_BCM2835
57
58 Make the bcm2835-mmc driver available for use on ARCH_BCM2835.
59
60 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
61
62 BCM270x_DT: add bcm2835-mmc entry
63
64 Add Device Tree entry for bcm2835-mmc.
65 In non-DT mode, don't add the device in the board file.
66
67 Signed-off-by: Noralf Trønnes <noralf@tronnes.org>
68
69 bcm2835-mmc: Don't overwrite MMC capabilities from DT
70 ---
71 drivers/mmc/core/quirks.c | 6 +
72 drivers/mmc/host/Kconfig | 29 +
73 drivers/mmc/host/Makefile | 1 +
74 drivers/mmc/host/bcm2835-mmc.c | 1542 ++++++++++++++++++++++++++++++++++++++++
75 4 files changed, 1578 insertions(+)
76 create mode 100644 drivers/mmc/host/bcm2835-mmc.c
77
78 --- a/drivers/mmc/core/quirks.c
79 +++ b/drivers/mmc/core/quirks.c
80 @@ -53,6 +53,7 @@ static const struct mmc_fixup mmc_fixup_
81
82 void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table)
83 {
84 + extern unsigned mmc_debug;
85 const struct mmc_fixup *f;
86 u64 rev = cid_rev_card(card);
87
88 @@ -77,5 +78,10 @@ void mmc_fixup_device(struct mmc_card *c
89 f->vendor_fixup(card, f->data);
90 }
91 }
92 + /* SDHCI on BCM2708 - bug causes a certain sequence of CMD23 operations to fail.
93 + * Disable this flag for all cards (fall-back to CMD25/CMD18 multi-block transfers).
94 + */
95 + if (mmc_debug & (1<<13))
96 + card->quirks |= MMC_QUIRK_BLK_NO_CMD23;
97 }
98 EXPORT_SYMBOL(mmc_fixup_device);
99 --- a/drivers/mmc/host/Kconfig
100 +++ b/drivers/mmc/host/Kconfig
101 @@ -4,6 +4,35 @@
102
103 comment "MMC/SD/SDIO Host Controller Drivers"
104
105 +config MMC_BCM2835
106 + tristate "MMC support on BCM2835"
107 + depends on MACH_BCM2708 || MACH_BCM2709 || ARCH_BCM2835
108 + help
109 + This selects the MMC Interface on BCM2835.
110 +
111 + If you have a controller with this interface, say Y or M here.
112 +
113 + If unsure, say N.
114 +
115 +config MMC_BCM2835_DMA
116 + bool "DMA support on BCM2835 Arasan controller"
117 + depends on MMC_BCM2835
118 + help
119 + Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
120 + based chips.
121 +
122 + If unsure, say N.
123 +
124 +config MMC_BCM2835_PIO_DMA_BARRIER
125 + int "Block count limit for PIO transfers"
126 + depends on MMC_BCM2835 && MMC_BCM2835_DMA
127 + range 0 256
128 + default 2
129 + help
130 + The inclusive limit in bytes under which PIO will be used instead of DMA
131 +
132 + If unsure, say 2 here.
133 +
134 config MMC_ARMMMCI
135 tristate "ARM AMBA Multimedia Card Interface support"
136 depends on ARM_AMBA
137 --- a/drivers/mmc/host/Makefile
138 +++ b/drivers/mmc/host/Makefile
139 @@ -18,6 +18,7 @@ obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c
140 obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
141 obj-$(CONFIG_MMC_SDHCI_F_SDH30) += sdhci_f_sdh30.o
142 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
143 +obj-$(CONFIG_MMC_BCM2835) += bcm2835-mmc.o
144 obj-$(CONFIG_MMC_WBSD) += wbsd.o
145 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
146 obj-$(CONFIG_MMC_MTK) += mtk-sd.o
147 --- /dev/null
148 +++ b/drivers/mmc/host/bcm2835-mmc.c
149 @@ -0,0 +1,1542 @@
150 +/*
151 + * BCM2835 MMC host driver.
152 + *
153 + * Author: Gellert Weisz <gellert@raspberrypi.org>
154 + * Copyright 2014
155 + *
156 + * Based on
157 + * sdhci-bcm2708.c by Broadcom
158 + * sdhci-bcm2835.c by Stephen Warren and Oleksandr Tymoshenko
159 + * sdhci.c and sdhci-pci.c by Pierre Ossman
160 + *
161 + * This program is free software; you can redistribute it and/or modify it
162 + * under the terms and conditions of the GNU General Public License,
163 + * version 2, as published by the Free Software Foundation.
164 + *
165 + * This program is distributed in the hope it will be useful, but WITHOUT
166 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
167 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
168 + * more details.
169 + *
170 + * You should have received a copy of the GNU General Public License
171 + * along with this program. If not, see <http://www.gnu.org/licenses/>.
172 + */
173 +
174 +#include <linux/delay.h>
175 +#include <linux/module.h>
176 +#include <linux/io.h>
177 +#include <linux/mmc/mmc.h>
178 +#include <linux/mmc/host.h>
179 +#include <linux/mmc/sd.h>
180 +#include <linux/scatterlist.h>
181 +#include <linux/of_address.h>
182 +#include <linux/of_irq.h>
183 +#include <linux/clk.h>
184 +#include <linux/platform_device.h>
185 +#include <linux/err.h>
186 +#include <linux/blkdev.h>
187 +#include <linux/dmaengine.h>
188 +#include <linux/dma-mapping.h>
189 +#include <linux/of_dma.h>
190 +
191 +#include "sdhci.h"
192 +
193 +
194 +#define DRIVER_NAME "mmc-bcm2835"
195 +
196 +#define DBG(f, x...) \
197 +pr_debug(DRIVER_NAME " [%s()]: " f, __func__, ## x)
198 +
199 +#ifndef CONFIG_MMC_BCM2835_DMA
200 + #define FORCE_PIO
201 +#endif
202 +
203 +
204 +/* the inclusive limit in bytes under which PIO will be used instead of DMA */
205 +#ifdef CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
206 +#define PIO_DMA_BARRIER CONFIG_MMC_BCM2835_PIO_DMA_BARRIER
207 +#else
208 +#define PIO_DMA_BARRIER 00
209 +#endif
210 +
211 +#define MIN_FREQ 400000
212 +#define TIMEOUT_VAL 0xE
213 +#define BCM2835_SDHCI_WRITE_DELAY(f) (((2 * 1000000) / f) + 1)
214 +
215 +
216 +unsigned mmc_debug;
217 +unsigned mmc_debug2;
218 +
219 +struct bcm2835_host {
220 + spinlock_t lock;
221 +
222 + void __iomem *ioaddr;
223 + u32 bus_addr;
224 +
225 + struct mmc_host *mmc;
226 +
227 + u32 timeout;
228 +
229 + int clock; /* Current clock speed */
230 + u8 pwr; /* Current voltage */
231 +
232 + unsigned int max_clk; /* Max possible freq */
233 + unsigned int timeout_clk; /* Timeout freq (KHz) */
234 + unsigned int clk_mul; /* Clock Muliplier value */
235 +
236 + struct tasklet_struct finish_tasklet; /* Tasklet structures */
237 +
238 + struct timer_list timer; /* Timer for timeouts */
239 +
240 + struct sg_mapping_iter sg_miter; /* SG state for PIO */
241 + unsigned int blocks; /* remaining PIO blocks */
242 +
243 + int irq; /* Device IRQ */
244 +
245 +
246 + u32 ier; /* cached registers */
247 +
248 + struct mmc_request *mrq; /* Current request */
249 + struct mmc_command *cmd; /* Current command */
250 + struct mmc_data *data; /* Current data request */
251 + unsigned int data_early:1; /* Data finished before cmd */
252 +
253 + wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
254 +
255 + u32 thread_isr;
256 +
257 + u32 shadow;
258 +
259 + /*DMA part*/
260 + struct dma_chan *dma_chan_rx; /* DMA channel for reads */
261 + struct dma_chan *dma_chan_tx; /* DMA channel for writes */
262 + struct dma_async_tx_descriptor *tx_desc; /* descriptor */
263 +
264 + bool have_dma;
265 + bool use_dma;
266 + /*end of DMA part*/
267 +
268 + int max_delay; /* maximum length of time spent waiting */
269 +
270 + int flags; /* Host attributes */
271 +#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
272 +#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
273 +#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
274 +#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
275 +#define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
276 +
277 + u32 overclock_50; /* frequency to use when 50MHz is requested (in MHz) */
278 + u32 max_overclock; /* Highest reported */
279 +};
280 +
281 +
282 +static inline void bcm2835_mmc_writel(struct bcm2835_host *host, u32 val, int reg, int from)
283 +{
284 + unsigned delay;
285 + lockdep_assert_held_once(&host->lock);
286 + writel(val, host->ioaddr + reg);
287 + udelay(BCM2835_SDHCI_WRITE_DELAY(max(host->clock, MIN_FREQ)));
288 +
289 + delay = ((mmc_debug >> 16) & 0xf) << ((mmc_debug >> 20) & 0xf);
290 + if (delay && !((1<<from) & mmc_debug2))
291 + udelay(delay);
292 +}
293 +
294 +static inline void mmc_raw_writel(struct bcm2835_host *host, u32 val, int reg)
295 +{
296 + unsigned delay;
297 + lockdep_assert_held_once(&host->lock);
298 + writel(val, host->ioaddr + reg);
299 +
300 + delay = ((mmc_debug >> 24) & 0xf) << ((mmc_debug >> 28) & 0xf);
301 + if (delay)
302 + udelay(delay);
303 +}
304 +
305 +static inline u32 bcm2835_mmc_readl(struct bcm2835_host *host, int reg)
306 +{
307 + lockdep_assert_held_once(&host->lock);
308 + return readl(host->ioaddr + reg);
309 +}
310 +
311 +static inline void bcm2835_mmc_writew(struct bcm2835_host *host, u16 val, int reg)
312 +{
313 + u32 oldval = (reg == SDHCI_COMMAND) ? host->shadow :
314 + bcm2835_mmc_readl(host, reg & ~3);
315 + u32 word_num = (reg >> 1) & 1;
316 + u32 word_shift = word_num * 16;
317 + u32 mask = 0xffff << word_shift;
318 + u32 newval = (oldval & ~mask) | (val << word_shift);
319 +
320 + if (reg == SDHCI_TRANSFER_MODE)
321 + host->shadow = newval;
322 + else
323 + bcm2835_mmc_writel(host, newval, reg & ~3, 0);
324 +
325 +}
326 +
327 +static inline void bcm2835_mmc_writeb(struct bcm2835_host *host, u8 val, int reg)
328 +{
329 + u32 oldval = bcm2835_mmc_readl(host, reg & ~3);
330 + u32 byte_num = reg & 3;
331 + u32 byte_shift = byte_num * 8;
332 + u32 mask = 0xff << byte_shift;
333 + u32 newval = (oldval & ~mask) | (val << byte_shift);
334 +
335 + bcm2835_mmc_writel(host, newval, reg & ~3, 1);
336 +}
337 +
338 +
339 +static inline u16 bcm2835_mmc_readw(struct bcm2835_host *host, int reg)
340 +{
341 + u32 val = bcm2835_mmc_readl(host, (reg & ~3));
342 + u32 word_num = (reg >> 1) & 1;
343 + u32 word_shift = word_num * 16;
344 + u32 word = (val >> word_shift) & 0xffff;
345 +
346 + return word;
347 +}
348 +
349 +static inline u8 bcm2835_mmc_readb(struct bcm2835_host *host, int reg)
350 +{
351 + u32 val = bcm2835_mmc_readl(host, (reg & ~3));
352 + u32 byte_num = reg & 3;
353 + u32 byte_shift = byte_num * 8;
354 + u32 byte = (val >> byte_shift) & 0xff;
355 +
356 + return byte;
357 +}
358 +
359 +static void bcm2835_mmc_unsignal_irqs(struct bcm2835_host *host, u32 clear)
360 +{
361 + u32 ier;
362 +
363 + ier = bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE);
364 + ier &= ~clear;
365 + /* change which requests generate IRQs - makes no difference to
366 + the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
367 + bcm2835_mmc_writel(host, ier, SDHCI_SIGNAL_ENABLE, 2);
368 +}
369 +
370 +
371 +static void bcm2835_mmc_dumpregs(struct bcm2835_host *host)
372 +{
373 + pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
374 + mmc_hostname(host->mmc));
375 +
376 + pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
377 + bcm2835_mmc_readl(host, SDHCI_DMA_ADDRESS),
378 + bcm2835_mmc_readw(host, SDHCI_HOST_VERSION));
379 + pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
380 + bcm2835_mmc_readw(host, SDHCI_BLOCK_SIZE),
381 + bcm2835_mmc_readw(host, SDHCI_BLOCK_COUNT));
382 + pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
383 + bcm2835_mmc_readl(host, SDHCI_ARGUMENT),
384 + bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE));
385 + pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
386 + bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE),
387 + bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL));
388 + pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
389 + bcm2835_mmc_readb(host, SDHCI_POWER_CONTROL),
390 + bcm2835_mmc_readb(host, SDHCI_BLOCK_GAP_CONTROL));
391 + pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
392 + bcm2835_mmc_readb(host, SDHCI_WAKE_UP_CONTROL),
393 + bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL));
394 + pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
395 + bcm2835_mmc_readb(host, SDHCI_TIMEOUT_CONTROL),
396 + bcm2835_mmc_readl(host, SDHCI_INT_STATUS));
397 + pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
398 + bcm2835_mmc_readl(host, SDHCI_INT_ENABLE),
399 + bcm2835_mmc_readl(host, SDHCI_SIGNAL_ENABLE));
400 + pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
401 + bcm2835_mmc_readw(host, SDHCI_ACMD12_ERR),
402 + bcm2835_mmc_readw(host, SDHCI_SLOT_INT_STATUS));
403 + pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
404 + bcm2835_mmc_readl(host, SDHCI_CAPABILITIES),
405 + bcm2835_mmc_readl(host, SDHCI_CAPABILITIES_1));
406 + pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
407 + bcm2835_mmc_readw(host, SDHCI_COMMAND),
408 + bcm2835_mmc_readl(host, SDHCI_MAX_CURRENT));
409 + pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
410 + bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2));
411 +
412 + pr_debug(DRIVER_NAME ": ===========================================\n");
413 +}
414 +
415 +
416 +static void bcm2835_mmc_reset(struct bcm2835_host *host, u8 mask)
417 +{
418 + unsigned long timeout;
419 + unsigned long flags;
420 +
421 + spin_lock_irqsave(&host->lock, flags);
422 + bcm2835_mmc_writeb(host, mask, SDHCI_SOFTWARE_RESET);
423 +
424 + if (mask & SDHCI_RESET_ALL)
425 + host->clock = 0;
426 +
427 + /* Wait max 100 ms */
428 + timeout = 100;
429 +
430 + /* hw clears the bit when it's done */
431 + while (bcm2835_mmc_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
432 + if (timeout == 0) {
433 + pr_err("%s: Reset 0x%x never completed.\n",
434 + mmc_hostname(host->mmc), (int)mask);
435 + bcm2835_mmc_dumpregs(host);
436 + return;
437 + }
438 + timeout--;
439 + spin_unlock_irqrestore(&host->lock, flags);
440 + mdelay(1);
441 + spin_lock_irqsave(&host->lock, flags);
442 + }
443 +
444 + if (100-timeout > 10 && 100-timeout > host->max_delay) {
445 + host->max_delay = 100-timeout;
446 + pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
447 + }
448 + spin_unlock_irqrestore(&host->lock, flags);
449 +}
450 +
451 +static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
452 +
453 +static void bcm2835_mmc_init(struct bcm2835_host *host, int soft)
454 +{
455 + unsigned long flags;
456 + if (soft)
457 + bcm2835_mmc_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
458 + else
459 + bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
460 +
461 + host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
462 + SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
463 + SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
464 + SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
465 + SDHCI_INT_RESPONSE;
466 +
467 + spin_lock_irqsave(&host->lock, flags);
468 + bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 3);
469 + bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 3);
470 + spin_unlock_irqrestore(&host->lock, flags);
471 +
472 + if (soft) {
473 + /* force clock reconfiguration */
474 + host->clock = 0;
475 + bcm2835_mmc_set_ios(host->mmc, &host->mmc->ios);
476 + }
477 +}
478 +
479 +
480 +
481 +static void bcm2835_mmc_finish_data(struct bcm2835_host *host);
482 +
483 +static void bcm2835_mmc_dma_complete(void *param)
484 +{
485 + struct bcm2835_host *host = param;
486 + struct dma_chan *dma_chan;
487 + unsigned long flags;
488 + u32 dir_data;
489 +
490 + spin_lock_irqsave(&host->lock, flags);
491 +
492 + if (host->data && !(host->data->flags & MMC_DATA_WRITE)) {
493 + /* otherwise handled in SDHCI IRQ */
494 + dma_chan = host->dma_chan_rx;
495 + dir_data = DMA_FROM_DEVICE;
496 +
497 + dma_unmap_sg(dma_chan->device->dev,
498 + host->data->sg, host->data->sg_len,
499 + dir_data);
500 +
501 + bcm2835_mmc_finish_data(host);
502 + }
503 +
504 + spin_unlock_irqrestore(&host->lock, flags);
505 +}
506 +
507 +static void bcm2835_bcm2835_mmc_read_block_pio(struct bcm2835_host *host)
508 +{
509 + unsigned long flags;
510 + size_t blksize, len, chunk;
511 +
512 + u32 uninitialized_var(scratch);
513 + u8 *buf;
514 +
515 + blksize = host->data->blksz;
516 + chunk = 0;
517 +
518 + local_irq_save(flags);
519 +
520 + while (blksize) {
521 + if (!sg_miter_next(&host->sg_miter))
522 + BUG();
523 +
524 + len = min(host->sg_miter.length, blksize);
525 +
526 + blksize -= len;
527 + host->sg_miter.consumed = len;
528 +
529 + buf = host->sg_miter.addr;
530 +
531 + while (len) {
532 + if (chunk == 0) {
533 + scratch = bcm2835_mmc_readl(host, SDHCI_BUFFER);
534 + chunk = 4;
535 + }
536 +
537 + *buf = scratch & 0xFF;
538 +
539 + buf++;
540 + scratch >>= 8;
541 + chunk--;
542 + len--;
543 + }
544 + }
545 +
546 + sg_miter_stop(&host->sg_miter);
547 +
548 + local_irq_restore(flags);
549 +}
550 +
551 +static void bcm2835_bcm2835_mmc_write_block_pio(struct bcm2835_host *host)
552 +{
553 + unsigned long flags;
554 + size_t blksize, len, chunk;
555 + u32 scratch;
556 + u8 *buf;
557 +
558 + blksize = host->data->blksz;
559 + chunk = 0;
560 + chunk = 0;
561 + scratch = 0;
562 +
563 + local_irq_save(flags);
564 +
565 + while (blksize) {
566 + if (!sg_miter_next(&host->sg_miter))
567 + BUG();
568 +
569 + len = min(host->sg_miter.length, blksize);
570 +
571 + blksize -= len;
572 + host->sg_miter.consumed = len;
573 +
574 + buf = host->sg_miter.addr;
575 +
576 + while (len) {
577 + scratch |= (u32)*buf << (chunk * 8);
578 +
579 + buf++;
580 + chunk++;
581 + len--;
582 +
583 + if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
584 + mmc_raw_writel(host, scratch, SDHCI_BUFFER);
585 + chunk = 0;
586 + scratch = 0;
587 + }
588 + }
589 + }
590 +
591 + sg_miter_stop(&host->sg_miter);
592 +
593 + local_irq_restore(flags);
594 +}
595 +
596 +
597 +static void bcm2835_mmc_transfer_pio(struct bcm2835_host *host)
598 +{
599 + u32 mask;
600 +
601 + BUG_ON(!host->data);
602 +
603 + if (host->blocks == 0)
604 + return;
605 +
606 + if (host->data->flags & MMC_DATA_READ)
607 + mask = SDHCI_DATA_AVAILABLE;
608 + else
609 + mask = SDHCI_SPACE_AVAILABLE;
610 +
611 + while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
612 +
613 + if (host->data->flags & MMC_DATA_READ)
614 + bcm2835_bcm2835_mmc_read_block_pio(host);
615 + else
616 + bcm2835_bcm2835_mmc_write_block_pio(host);
617 +
618 + host->blocks--;
619 +
620 + /* QUIRK used in sdhci.c removes the 'if' */
621 + /* but it seems this is unnecessary */
622 + if (host->blocks == 0)
623 + break;
624 +
625 +
626 + }
627 +}
628 +
629 +
630 +static void bcm2835_mmc_transfer_dma(struct bcm2835_host *host)
631 +{
632 + u32 len, dir_data, dir_slave;
633 + struct dma_async_tx_descriptor *desc = NULL;
634 + struct dma_chan *dma_chan;
635 +
636 +
637 + WARN_ON(!host->data);
638 +
639 + if (!host->data)
640 + return;
641 +
642 + if (host->blocks == 0)
643 + return;
644 +
645 + if (host->data->flags & MMC_DATA_READ) {
646 + dma_chan = host->dma_chan_rx;
647 + dir_data = DMA_FROM_DEVICE;
648 + dir_slave = DMA_DEV_TO_MEM;
649 + } else {
650 + dma_chan = host->dma_chan_tx;
651 + dir_data = DMA_TO_DEVICE;
652 + dir_slave = DMA_MEM_TO_DEV;
653 + }
654 +
655 + BUG_ON(!dma_chan->device);
656 + BUG_ON(!dma_chan->device->dev);
657 + BUG_ON(!host->data->sg);
658 +
659 + len = dma_map_sg(dma_chan->device->dev, host->data->sg,
660 + host->data->sg_len, dir_data);
661 + if (len > 0) {
662 + desc = dmaengine_prep_slave_sg(dma_chan, host->data->sg,
663 + len, dir_slave,
664 + DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
665 + } else {
666 + dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n");
667 + }
668 + if (desc) {
669 + unsigned long flags;
670 + spin_lock_irqsave(&host->lock, flags);
671 + bcm2835_mmc_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
672 + SDHCI_INT_SPACE_AVAIL);
673 + host->tx_desc = desc;
674 + desc->callback = bcm2835_mmc_dma_complete;
675 + desc->callback_param = host;
676 + spin_unlock_irqrestore(&host->lock, flags);
677 + dmaengine_submit(desc);
678 + dma_async_issue_pending(dma_chan);
679 + }
680 +
681 +}
682 +
683 +
684 +
685 +static void bcm2835_mmc_set_transfer_irqs(struct bcm2835_host *host)
686 +{
687 + u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
688 + u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
689 +
690 + if (host->use_dma)
691 + host->ier = (host->ier & ~pio_irqs) | dma_irqs;
692 + else
693 + host->ier = (host->ier & ~dma_irqs) | pio_irqs;
694 +
695 + bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 4);
696 + bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 4);
697 +}
698 +
699 +
700 +static void bcm2835_mmc_prepare_data(struct bcm2835_host *host, struct mmc_command *cmd)
701 +{
702 + u8 count;
703 + struct mmc_data *data = cmd->data;
704 +
705 + WARN_ON(host->data);
706 +
707 + if (data || (cmd->flags & MMC_RSP_BUSY)) {
708 + count = TIMEOUT_VAL;
709 + bcm2835_mmc_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
710 + }
711 +
712 + if (!data)
713 + return;
714 +
715 + /* Sanity checks */
716 + BUG_ON(data->blksz * data->blocks > 524288);
717 + BUG_ON(data->blksz > host->mmc->max_blk_size);
718 + BUG_ON(data->blocks > 65535);
719 +
720 + host->data = data;
721 + host->data_early = 0;
722 + host->data->bytes_xfered = 0;
723 +
724 +
725 + if (!(host->flags & SDHCI_REQ_USE_DMA)) {
726 + int flags;
727 +
728 + flags = SG_MITER_ATOMIC;
729 + if (host->data->flags & MMC_DATA_READ)
730 + flags |= SG_MITER_TO_SG;
731 + else
732 + flags |= SG_MITER_FROM_SG;
733 + sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
734 + host->blocks = data->blocks;
735 + }
736 +
737 + host->use_dma = host->have_dma && data->blocks > PIO_DMA_BARRIER;
738 +
739 + bcm2835_mmc_set_transfer_irqs(host);
740 +
741 + /* Set the DMA boundary value and block size */
742 + bcm2835_mmc_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
743 + data->blksz), SDHCI_BLOCK_SIZE);
744 + bcm2835_mmc_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
745 +
746 + BUG_ON(!host->data);
747 +}
748 +
749 +static void bcm2835_mmc_set_transfer_mode(struct bcm2835_host *host,
750 + struct mmc_command *cmd)
751 +{
752 + u16 mode;
753 + struct mmc_data *data = cmd->data;
754 +
755 + if (data == NULL) {
756 + /* clear Auto CMD settings for no data CMDs */
757 + mode = bcm2835_mmc_readw(host, SDHCI_TRANSFER_MODE);
758 + bcm2835_mmc_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
759 + SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
760 + return;
761 + }
762 +
763 + WARN_ON(!host->data);
764 +
765 + mode = SDHCI_TRNS_BLK_CNT_EN;
766 +
767 + if ((mmc_op_multi(cmd->opcode) || data->blocks > 1)) {
768 + mode |= SDHCI_TRNS_MULTI;
769 +
770 + /*
771 + * If we are sending CMD23, CMD12 never gets sent
772 + * on successful completion (so no Auto-CMD12).
773 + */
774 + if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
775 + mode |= SDHCI_TRNS_AUTO_CMD12;
776 + else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
777 + mode |= SDHCI_TRNS_AUTO_CMD23;
778 + bcm2835_mmc_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2, 5);
779 + }
780 + }
781 +
782 + if (data->flags & MMC_DATA_READ)
783 + mode |= SDHCI_TRNS_READ;
784 + if (host->flags & SDHCI_REQ_USE_DMA)
785 + mode |= SDHCI_TRNS_DMA;
786 +
787 + bcm2835_mmc_writew(host, mode, SDHCI_TRANSFER_MODE);
788 +}
789 +
790 +void bcm2835_mmc_send_command(struct bcm2835_host *host, struct mmc_command *cmd)
791 +{
792 + int flags;
793 + u32 mask;
794 + unsigned long timeout;
795 +
796 + WARN_ON(host->cmd);
797 +
798 + /* Wait max 10 ms */
799 + timeout = 1000;
800 +
801 + mask = SDHCI_CMD_INHIBIT;
802 + if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
803 + mask |= SDHCI_DATA_INHIBIT;
804 +
805 + /* We shouldn't wait for data inihibit for stop commands, even
806 + though they might use busy signaling */
807 + if (host->mrq->data && (cmd == host->mrq->data->stop))
808 + mask &= ~SDHCI_DATA_INHIBIT;
809 +
810 + while (bcm2835_mmc_readl(host, SDHCI_PRESENT_STATE) & mask) {
811 + if (timeout == 0) {
812 + pr_err("%s: Controller never released inhibit bit(s).\n",
813 + mmc_hostname(host->mmc));
814 + bcm2835_mmc_dumpregs(host);
815 + cmd->error = -EIO;
816 + tasklet_schedule(&host->finish_tasklet);
817 + return;
818 + }
819 + timeout--;
820 + udelay(10);
821 + }
822 +
823 + if ((1000-timeout)/100 > 1 && (1000-timeout)/100 > host->max_delay) {
824 + host->max_delay = (1000-timeout)/100;
825 + pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
826 + }
827 +
828 + timeout = jiffies;
829 + if (!cmd->data && cmd->busy_timeout > 9000)
830 + timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
831 + else
832 + timeout += 10 * HZ;
833 + mod_timer(&host->timer, timeout);
834 +
835 + host->cmd = cmd;
836 +
837 + bcm2835_mmc_prepare_data(host, cmd);
838 +
839 + bcm2835_mmc_writel(host, cmd->arg, SDHCI_ARGUMENT, 6);
840 +
841 + bcm2835_mmc_set_transfer_mode(host, cmd);
842 +
843 + if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
844 + pr_err("%s: Unsupported response type!\n",
845 + mmc_hostname(host->mmc));
846 + cmd->error = -EINVAL;
847 + tasklet_schedule(&host->finish_tasklet);
848 + return;
849 + }
850 +
851 + if (!(cmd->flags & MMC_RSP_PRESENT))
852 + flags = SDHCI_CMD_RESP_NONE;
853 + else if (cmd->flags & MMC_RSP_136)
854 + flags = SDHCI_CMD_RESP_LONG;
855 + else if (cmd->flags & MMC_RSP_BUSY)
856 + flags = SDHCI_CMD_RESP_SHORT_BUSY;
857 + else
858 + flags = SDHCI_CMD_RESP_SHORT;
859 +
860 + if (cmd->flags & MMC_RSP_CRC)
861 + flags |= SDHCI_CMD_CRC;
862 + if (cmd->flags & MMC_RSP_OPCODE)
863 + flags |= SDHCI_CMD_INDEX;
864 +
865 + if (cmd->data)
866 + flags |= SDHCI_CMD_DATA;
867 +
868 + bcm2835_mmc_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
869 +}
870 +
871 +
872 +static void bcm2835_mmc_finish_data(struct bcm2835_host *host)
873 +{
874 + struct mmc_data *data;
875 +
876 + BUG_ON(!host->data);
877 +
878 + data = host->data;
879 + host->data = NULL;
880 +
881 + if (data->error)
882 + data->bytes_xfered = 0;
883 + else
884 + data->bytes_xfered = data->blksz * data->blocks;
885 +
886 + /*
887 + * Need to send CMD12 if -
888 + * a) open-ended multiblock transfer (no CMD23)
889 + * b) error in multiblock transfer
890 + */
891 + if (data->stop &&
892 + (data->error ||
893 + !host->mrq->sbc)) {
894 +
895 + /*
896 + * The controller needs a reset of internal state machines
897 + * upon error conditions.
898 + */
899 + if (data->error) {
900 + bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
901 + bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
902 + }
903 +
904 + bcm2835_mmc_send_command(host, data->stop);
905 + } else
906 + tasklet_schedule(&host->finish_tasklet);
907 +}
908 +
909 +static void bcm2835_mmc_finish_command(struct bcm2835_host *host)
910 +{
911 + int i;
912 +
913 + BUG_ON(host->cmd == NULL);
914 +
915 + if (host->cmd->flags & MMC_RSP_PRESENT) {
916 + if (host->cmd->flags & MMC_RSP_136) {
917 + /* CRC is stripped so we need to do some shifting. */
918 + for (i = 0; i < 4; i++) {
919 + host->cmd->resp[i] = bcm2835_mmc_readl(host,
920 + SDHCI_RESPONSE + (3-i)*4) << 8;
921 + if (i != 3)
922 + host->cmd->resp[i] |=
923 + bcm2835_mmc_readb(host,
924 + SDHCI_RESPONSE + (3-i)*4-1);
925 + }
926 + } else {
927 + host->cmd->resp[0] = bcm2835_mmc_readl(host, SDHCI_RESPONSE);
928 + }
929 + }
930 +
931 + host->cmd->error = 0;
932 +
933 + /* Finished CMD23, now send actual command. */
934 + if (host->cmd == host->mrq->sbc) {
935 + host->cmd = NULL;
936 + bcm2835_mmc_send_command(host, host->mrq->cmd);
937 +
938 + if (host->mrq->cmd->data && host->use_dma) {
939 + /* DMA transfer starts now, PIO starts after interrupt */
940 + bcm2835_mmc_transfer_dma(host);
941 + }
942 + } else {
943 +
944 + /* Processed actual command. */
945 + if (host->data && host->data_early)
946 + bcm2835_mmc_finish_data(host);
947 +
948 + if (!host->cmd->data)
949 + tasklet_schedule(&host->finish_tasklet);
950 +
951 + host->cmd = NULL;
952 + }
953 +}
954 +
955 +
956 +static void bcm2835_mmc_timeout_timer(unsigned long data)
957 +{
958 + struct bcm2835_host *host;
959 + unsigned long flags;
960 +
961 + host = (struct bcm2835_host *)data;
962 +
963 + spin_lock_irqsave(&host->lock, flags);
964 +
965 + if (host->mrq) {
966 + pr_err("%s: Timeout waiting for hardware interrupt.\n",
967 + mmc_hostname(host->mmc));
968 + bcm2835_mmc_dumpregs(host);
969 +
970 + if (host->data) {
971 + host->data->error = -ETIMEDOUT;
972 + bcm2835_mmc_finish_data(host);
973 + } else {
974 + if (host->cmd)
975 + host->cmd->error = -ETIMEDOUT;
976 + else
977 + host->mrq->cmd->error = -ETIMEDOUT;
978 +
979 + tasklet_schedule(&host->finish_tasklet);
980 + }
981 + }
982 +
983 + mmiowb();
984 + spin_unlock_irqrestore(&host->lock, flags);
985 +}
986 +
987 +
988 +static void bcm2835_mmc_enable_sdio_irq_nolock(struct bcm2835_host *host, int enable)
989 +{
990 + if (!(host->flags & SDHCI_DEVICE_DEAD)) {
991 + if (enable)
992 + host->ier |= SDHCI_INT_CARD_INT;
993 + else
994 + host->ier &= ~SDHCI_INT_CARD_INT;
995 +
996 + bcm2835_mmc_writel(host, host->ier, SDHCI_INT_ENABLE, 7);
997 + bcm2835_mmc_writel(host, host->ier, SDHCI_SIGNAL_ENABLE, 7);
998 + mmiowb();
999 + }
1000 +}
1001 +
1002 +static void bcm2835_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1003 +{
1004 + struct bcm2835_host *host = mmc_priv(mmc);
1005 + unsigned long flags;
1006 +
1007 + spin_lock_irqsave(&host->lock, flags);
1008 + if (enable)
1009 + host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1010 + else
1011 + host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1012 +
1013 + bcm2835_mmc_enable_sdio_irq_nolock(host, enable);
1014 + spin_unlock_irqrestore(&host->lock, flags);
1015 +}
1016 +
1017 +static void bcm2835_mmc_cmd_irq(struct bcm2835_host *host, u32 intmask)
1018 +{
1019 +
1020 + BUG_ON(intmask == 0);
1021 +
1022 + if (!host->cmd) {
1023 + pr_err("%s: Got command interrupt 0x%08x even "
1024 + "though no command operation was in progress.\n",
1025 + mmc_hostname(host->mmc), (unsigned)intmask);
1026 + bcm2835_mmc_dumpregs(host);
1027 + return;
1028 + }
1029 +
1030 + if (intmask & SDHCI_INT_TIMEOUT)
1031 + host->cmd->error = -ETIMEDOUT;
1032 + else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
1033 + SDHCI_INT_INDEX)) {
1034 + host->cmd->error = -EILSEQ;
1035 + }
1036 +
1037 + if (host->cmd->error) {
1038 + tasklet_schedule(&host->finish_tasklet);
1039 + return;
1040 + }
1041 +
1042 + if (intmask & SDHCI_INT_RESPONSE)
1043 + bcm2835_mmc_finish_command(host);
1044 +
1045 +}
1046 +
1047 +static void bcm2835_mmc_data_irq(struct bcm2835_host *host, u32 intmask)
1048 +{
1049 + struct dma_chan *dma_chan;
1050 + u32 dir_data;
1051 +
1052 + BUG_ON(intmask == 0);
1053 +
1054 + if (!host->data) {
1055 + /*
1056 + * The "data complete" interrupt is also used to
1057 + * indicate that a busy state has ended. See comment
1058 + * above in sdhci_cmd_irq().
1059 + */
1060 + if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
1061 + if (intmask & SDHCI_INT_DATA_END) {
1062 + bcm2835_mmc_finish_command(host);
1063 + return;
1064 + }
1065 + }
1066 +
1067 + pr_debug("%s: Got data interrupt 0x%08x even "
1068 + "though no data operation was in progress.\n",
1069 + mmc_hostname(host->mmc), (unsigned)intmask);
1070 + bcm2835_mmc_dumpregs(host);
1071 +
1072 + return;
1073 + }
1074 +
1075 + if (intmask & SDHCI_INT_DATA_TIMEOUT)
1076 + host->data->error = -ETIMEDOUT;
1077 + else if (intmask & SDHCI_INT_DATA_END_BIT)
1078 + host->data->error = -EILSEQ;
1079 + else if ((intmask & SDHCI_INT_DATA_CRC) &&
1080 + SDHCI_GET_CMD(bcm2835_mmc_readw(host, SDHCI_COMMAND))
1081 + != MMC_BUS_TEST_R)
1082 + host->data->error = -EILSEQ;
1083 +
1084 + if (host->use_dma) {
1085 + if (host->data->flags & MMC_DATA_WRITE) {
1086 + /* IRQ handled here */
1087 +
1088 + dma_chan = host->dma_chan_tx;
1089 + dir_data = DMA_TO_DEVICE;
1090 + dma_unmap_sg(dma_chan->device->dev,
1091 + host->data->sg, host->data->sg_len,
1092 + dir_data);
1093 +
1094 + bcm2835_mmc_finish_data(host);
1095 + }
1096 +
1097 + } else {
1098 + if (host->data->error)
1099 + bcm2835_mmc_finish_data(host);
1100 + else {
1101 + if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
1102 + bcm2835_mmc_transfer_pio(host);
1103 +
1104 + if (intmask & SDHCI_INT_DATA_END) {
1105 + if (host->cmd) {
1106 + /*
1107 + * Data managed to finish before the
1108 + * command completed. Make sure we do
1109 + * things in the proper order.
1110 + */
1111 + host->data_early = 1;
1112 + } else {
1113 + bcm2835_mmc_finish_data(host);
1114 + }
1115 + }
1116 + }
1117 + }
1118 +}
1119 +
1120 +
1121 +static irqreturn_t bcm2835_mmc_irq(int irq, void *dev_id)
1122 +{
1123 + irqreturn_t result = IRQ_NONE;
1124 + struct bcm2835_host *host = dev_id;
1125 + u32 intmask, mask, unexpected = 0;
1126 + int max_loops = 16;
1127 +
1128 + spin_lock(&host->lock);
1129 +
1130 + intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
1131 +
1132 + if (!intmask || intmask == 0xffffffff) {
1133 + result = IRQ_NONE;
1134 + goto out;
1135 + }
1136 +
1137 + do {
1138 + /* Clear selected interrupts. */
1139 + mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
1140 + SDHCI_INT_BUS_POWER);
1141 + bcm2835_mmc_writel(host, mask, SDHCI_INT_STATUS, 8);
1142 +
1143 +
1144 + if (intmask & SDHCI_INT_CMD_MASK)
1145 + bcm2835_mmc_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
1146 +
1147 + if (intmask & SDHCI_INT_DATA_MASK)
1148 + bcm2835_mmc_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
1149 +
1150 + if (intmask & SDHCI_INT_BUS_POWER)
1151 + pr_err("%s: Card is consuming too much power!\n",
1152 + mmc_hostname(host->mmc));
1153 +
1154 + if (intmask & SDHCI_INT_CARD_INT) {
1155 + bcm2835_mmc_enable_sdio_irq_nolock(host, false);
1156 + host->thread_isr |= SDHCI_INT_CARD_INT;
1157 + result = IRQ_WAKE_THREAD;
1158 + }
1159 +
1160 + intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
1161 + SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
1162 + SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
1163 + SDHCI_INT_CARD_INT);
1164 +
1165 + if (intmask) {
1166 + unexpected |= intmask;
1167 + bcm2835_mmc_writel(host, intmask, SDHCI_INT_STATUS, 9);
1168 + }
1169 +
1170 + if (result == IRQ_NONE)
1171 + result = IRQ_HANDLED;
1172 +
1173 + intmask = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
1174 + } while (intmask && --max_loops);
1175 +out:
1176 + spin_unlock(&host->lock);
1177 +
1178 + if (unexpected) {
1179 + pr_err("%s: Unexpected interrupt 0x%08x.\n",
1180 + mmc_hostname(host->mmc), unexpected);
1181 + bcm2835_mmc_dumpregs(host);
1182 + }
1183 +
1184 + return result;
1185 +}
1186 +
1187 +static irqreturn_t bcm2835_mmc_thread_irq(int irq, void *dev_id)
1188 +{
1189 + struct bcm2835_host *host = dev_id;
1190 + unsigned long flags;
1191 + u32 isr;
1192 +
1193 + spin_lock_irqsave(&host->lock, flags);
1194 + isr = host->thread_isr;
1195 + host->thread_isr = 0;
1196 + spin_unlock_irqrestore(&host->lock, flags);
1197 +
1198 + if (isr & SDHCI_INT_CARD_INT) {
1199 + sdio_run_irqs(host->mmc);
1200 +
1201 + spin_lock_irqsave(&host->lock, flags);
1202 + if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
1203 + bcm2835_mmc_enable_sdio_irq_nolock(host, true);
1204 + spin_unlock_irqrestore(&host->lock, flags);
1205 + }
1206 +
1207 + return isr ? IRQ_HANDLED : IRQ_NONE;
1208 +}
1209 +
1210 +
1211 +
1212 +void bcm2835_mmc_set_clock(struct bcm2835_host *host, unsigned int clock)
1213 +{
1214 + int div = 0; /* Initialized for compiler warning */
1215 + int real_div = div, clk_mul = 1;
1216 + u16 clk = 0;
1217 + unsigned long timeout;
1218 + unsigned int input_clock = clock;
1219 +
1220 + if (host->overclock_50 && (clock == 50000000))
1221 + clock = host->overclock_50 * 1000000 + 999999;
1222 +
1223 + host->mmc->actual_clock = 0;
1224 +
1225 + bcm2835_mmc_writew(host, 0, SDHCI_CLOCK_CONTROL);
1226 +
1227 + if (clock == 0)
1228 + return;
1229 +
1230 + /* Version 3.00 divisors must be a multiple of 2. */
1231 + if (host->max_clk <= clock)
1232 + div = 1;
1233 + else {
1234 + for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1235 + div += 2) {
1236 + if ((host->max_clk / div) <= clock)
1237 + break;
1238 + }
1239 + }
1240 +
1241 + real_div = div;
1242 + div >>= 1;
1243 +
1244 + if (real_div)
1245 + clock = (host->max_clk * clk_mul) / real_div;
1246 + host->mmc->actual_clock = clock;
1247 +
1248 + if ((clock > input_clock) && (clock > host->max_overclock)) {
1249 + pr_warn("%s: Overclocking to %dHz\n",
1250 + mmc_hostname(host->mmc), clock);
1251 + host->max_overclock = clock;
1252 + }
1253 +
1254 + clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1255 + clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1256 + << SDHCI_DIVIDER_HI_SHIFT;
1257 + clk |= SDHCI_CLOCK_INT_EN;
1258 + bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
1259 +
1260 + /* Wait max 20 ms */
1261 + timeout = 20;
1262 + while (!((clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL))
1263 + & SDHCI_CLOCK_INT_STABLE)) {
1264 + if (timeout == 0) {
1265 + pr_err("%s: Internal clock never "
1266 + "stabilised.\n", mmc_hostname(host->mmc));
1267 + bcm2835_mmc_dumpregs(host);
1268 + return;
1269 + }
1270 + timeout--;
1271 + mdelay(1);
1272 + }
1273 +
1274 + if (20-timeout > 10 && 20-timeout > host->max_delay) {
1275 + host->max_delay = 20-timeout;
1276 + pr_warning("Warning: MMC controller hung for %d ms\n", host->max_delay);
1277 + }
1278 +
1279 + clk |= SDHCI_CLOCK_CARD_EN;
1280 + bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
1281 +}
1282 +
1283 +static void bcm2835_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
1284 +{
1285 + struct bcm2835_host *host;
1286 + unsigned long flags;
1287 +
1288 + host = mmc_priv(mmc);
1289 +
1290 + spin_lock_irqsave(&host->lock, flags);
1291 +
1292 + WARN_ON(host->mrq != NULL);
1293 +
1294 + host->mrq = mrq;
1295 +
1296 + if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1297 + bcm2835_mmc_send_command(host, mrq->sbc);
1298 + else
1299 + bcm2835_mmc_send_command(host, mrq->cmd);
1300 +
1301 + mmiowb();
1302 + spin_unlock_irqrestore(&host->lock, flags);
1303 +
1304 + if (!(mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) && mrq->cmd->data && host->use_dma) {
1305 + /* DMA transfer starts now, PIO starts after interrupt */
1306 + bcm2835_mmc_transfer_dma(host);
1307 + }
1308 +}
1309 +
1310 +
1311 +static void bcm2835_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1312 +{
1313 +
1314 + struct bcm2835_host *host = mmc_priv(mmc);
1315 + unsigned long flags;
1316 + u8 ctrl;
1317 + u16 clk, ctrl_2;
1318 +
1319 + pr_debug("bcm2835_mmc_set_ios: clock %d, pwr %d, bus_width %d, timing %d, vdd %d, drv_type %d\n",
1320 + ios->clock, ios->power_mode, ios->bus_width,
1321 + ios->timing, ios->signal_voltage, ios->drv_type);
1322 +
1323 + spin_lock_irqsave(&host->lock, flags);
1324 +
1325 + if (!ios->clock || ios->clock != host->clock) {
1326 + bcm2835_mmc_set_clock(host, ios->clock);
1327 + host->clock = ios->clock;
1328 + }
1329 +
1330 + if (host->pwr != SDHCI_POWER_330) {
1331 + host->pwr = SDHCI_POWER_330;
1332 + bcm2835_mmc_writeb(host, SDHCI_POWER_330 | SDHCI_POWER_ON, SDHCI_POWER_CONTROL);
1333 + }
1334 +
1335 + ctrl = bcm2835_mmc_readb(host, SDHCI_HOST_CONTROL);
1336 +
1337 + /* set bus width */
1338 + ctrl &= ~SDHCI_CTRL_8BITBUS;
1339 + if (ios->bus_width == MMC_BUS_WIDTH_4)
1340 + ctrl |= SDHCI_CTRL_4BITBUS;
1341 + else
1342 + ctrl &= ~SDHCI_CTRL_4BITBUS;
1343 +
1344 + ctrl &= ~SDHCI_CTRL_HISPD; /* NO_HISPD_BIT */
1345 +
1346 +
1347 + bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1348 + /*
1349 + * We only need to set Driver Strength if the
1350 + * preset value enable is not set.
1351 + */
1352 + ctrl_2 = bcm2835_mmc_readw(host, SDHCI_HOST_CONTROL2);
1353 + ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1354 + if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1355 + ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1356 + else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1357 + ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1358 +
1359 + bcm2835_mmc_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1360 +
1361 + /* Reset SD Clock Enable */
1362 + clk = bcm2835_mmc_readw(host, SDHCI_CLOCK_CONTROL);
1363 + clk &= ~SDHCI_CLOCK_CARD_EN;
1364 + bcm2835_mmc_writew(host, clk, SDHCI_CLOCK_CONTROL);
1365 +
1366 + /* Re-enable SD Clock */
1367 + bcm2835_mmc_set_clock(host, host->clock);
1368 + bcm2835_mmc_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1369 +
1370 + mmiowb();
1371 +
1372 + spin_unlock_irqrestore(&host->lock, flags);
1373 +}
1374 +
1375 +
1376 +static struct mmc_host_ops bcm2835_ops = {
1377 + .request = bcm2835_mmc_request,
1378 + .set_ios = bcm2835_mmc_set_ios,
1379 + .enable_sdio_irq = bcm2835_mmc_enable_sdio_irq,
1380 +};
1381 +
1382 +
1383 +static void bcm2835_mmc_tasklet_finish(unsigned long param)
1384 +{
1385 + struct bcm2835_host *host;
1386 + unsigned long flags;
1387 + struct mmc_request *mrq;
1388 +
1389 + host = (struct bcm2835_host *)param;
1390 +
1391 + spin_lock_irqsave(&host->lock, flags);
1392 +
1393 + /*
1394 + * If this tasklet gets rescheduled while running, it will
1395 + * be run again afterwards but without any active request.
1396 + */
1397 + if (!host->mrq) {
1398 + spin_unlock_irqrestore(&host->lock, flags);
1399 + return;
1400 + }
1401 +
1402 + del_timer(&host->timer);
1403 +
1404 + mrq = host->mrq;
1405 +
1406 + /*
1407 + * The controller needs a reset of internal state machines
1408 + * upon error conditions.
1409 + */
1410 + if (!(host->flags & SDHCI_DEVICE_DEAD) &&
1411 + ((mrq->cmd && mrq->cmd->error) ||
1412 + (mrq->data && (mrq->data->error ||
1413 + (mrq->data->stop && mrq->data->stop->error))))) {
1414 +
1415 + spin_unlock_irqrestore(&host->lock, flags);
1416 + bcm2835_mmc_reset(host, SDHCI_RESET_CMD);
1417 + bcm2835_mmc_reset(host, SDHCI_RESET_DATA);
1418 + spin_lock_irqsave(&host->lock, flags);
1419 + }
1420 +
1421 + host->mrq = NULL;
1422 + host->cmd = NULL;
1423 + host->data = NULL;
1424 +
1425 + mmiowb();
1426 +
1427 + spin_unlock_irqrestore(&host->lock, flags);
1428 + mmc_request_done(host->mmc, mrq);
1429 +}
1430 +
1431 +
1432 +
1433 +static int bcm2835_mmc_add_host(struct bcm2835_host *host)
1434 +{
1435 + struct mmc_host *mmc = host->mmc;
1436 + struct device *dev = mmc->parent;
1437 +#ifndef FORCE_PIO
1438 + struct dma_slave_config cfg;
1439 +#endif
1440 + int ret;
1441 +
1442 + bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
1443 +
1444 + host->clk_mul = 0;
1445 +
1446 + mmc->f_max = host->max_clk;
1447 + mmc->f_max = host->max_clk;
1448 + mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
1449 +
1450 + /* SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK */
1451 + host->timeout_clk = mmc->f_max / 1000;
1452 + mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
1453 +
1454 + /* host controller capabilities */
1455 + mmc->caps |= MMC_CAP_CMD23 | MMC_CAP_ERASE | MMC_CAP_NEEDS_POLL |
1456 + MMC_CAP_SDIO_IRQ | MMC_CAP_SD_HIGHSPEED |
1457 + MMC_CAP_MMC_HIGHSPEED | MMC_CAP_4_BIT_DATA;
1458 +
1459 + mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
1460 +
1461 + host->flags = SDHCI_AUTO_CMD23;
1462 +
1463 + dev_info(dev, "mmc_debug:%x mmc_debug2:%x\n", mmc_debug, mmc_debug2);
1464 +#ifdef FORCE_PIO
1465 + dev_info(dev, "Forcing PIO mode\n");
1466 + host->have_dma = false;
1467 +#else
1468 + if (IS_ERR_OR_NULL(host->dma_chan_tx) ||
1469 + IS_ERR_OR_NULL(host->dma_chan_rx)) {
1470 + dev_err(dev, "%s: Unable to initialise DMA channels. Falling back to PIO\n",
1471 + DRIVER_NAME);
1472 + host->have_dma = false;
1473 + } else {
1474 + dev_info(dev, "DMA channels allocated");
1475 + host->have_dma = true;
1476 +
1477 + cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1478 + cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1479 + cfg.slave_id = 11; /* DREQ channel */
1480 +
1481 + cfg.direction = DMA_MEM_TO_DEV;
1482 + cfg.src_addr = 0;
1483 + cfg.dst_addr = host->bus_addr + SDHCI_BUFFER;
1484 + ret = dmaengine_slave_config(host->dma_chan_tx, &cfg);
1485 +
1486 + cfg.direction = DMA_DEV_TO_MEM;
1487 + cfg.src_addr = host->bus_addr + SDHCI_BUFFER;
1488 + cfg.dst_addr = 0;
1489 + ret = dmaengine_slave_config(host->dma_chan_rx, &cfg);
1490 + }
1491 +#endif
1492 + mmc->max_segs = 128;
1493 + mmc->max_req_size = 524288;
1494 + mmc->max_seg_size = mmc->max_req_size;
1495 + mmc->max_blk_size = 512;
1496 + mmc->max_blk_count = 65535;
1497 +
1498 + /* report supported voltage ranges */
1499 + mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1500 +
1501 + tasklet_init(&host->finish_tasklet,
1502 + bcm2835_mmc_tasklet_finish, (unsigned long)host);
1503 +
1504 + setup_timer(&host->timer, bcm2835_mmc_timeout_timer, (unsigned long)host);
1505 + init_waitqueue_head(&host->buf_ready_int);
1506 +
1507 + bcm2835_mmc_init(host, 0);
1508 + ret = devm_request_threaded_irq(dev, host->irq, bcm2835_mmc_irq,
1509 + bcm2835_mmc_thread_irq, IRQF_SHARED,
1510 + mmc_hostname(mmc), host);
1511 + if (ret) {
1512 + dev_err(dev, "Failed to request IRQ %d: %d\n", host->irq, ret);
1513 + goto untasklet;
1514 + }
1515 +
1516 + mmiowb();
1517 + mmc_add_host(mmc);
1518 +
1519 + return 0;
1520 +
1521 +untasklet:
1522 + tasklet_kill(&host->finish_tasklet);
1523 +
1524 + return ret;
1525 +}
1526 +
1527 +static int bcm2835_mmc_probe(struct platform_device *pdev)
1528 +{
1529 + struct device *dev = &pdev->dev;
1530 + struct device_node *node = dev->of_node;
1531 + struct clk *clk;
1532 + struct resource *iomem;
1533 + struct bcm2835_host *host;
1534 + struct mmc_host *mmc;
1535 + const __be32 *addr;
1536 + int ret;
1537 +
1538 + mmc = mmc_alloc_host(sizeof(*host), dev);
1539 + if (!mmc)
1540 + return -ENOMEM;
1541 +
1542 + mmc->ops = &bcm2835_ops;
1543 + host = mmc_priv(mmc);
1544 + host->mmc = mmc;
1545 + host->timeout = msecs_to_jiffies(1000);
1546 + spin_lock_init(&host->lock);
1547 +
1548 + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1549 + host->ioaddr = devm_ioremap_resource(dev, iomem);
1550 + if (IS_ERR(host->ioaddr)) {
1551 + ret = PTR_ERR(host->ioaddr);
1552 + goto err;
1553 + }
1554 +
1555 + addr = of_get_address(node, 0, NULL, NULL);
1556 + if (!addr) {
1557 + dev_err(dev, "could not get DMA-register address\n");
1558 + return -ENODEV;
1559 + }
1560 + host->bus_addr = be32_to_cpup(addr);
1561 + pr_debug(" - ioaddr %lx, iomem->start %lx, bus_addr %lx\n",
1562 + (unsigned long)host->ioaddr,
1563 + (unsigned long)iomem->start,
1564 + (unsigned long)host->bus_addr);
1565 +
1566 +#ifndef FORCE_PIO
1567 + if (node) {
1568 + host->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1569 + host->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1570 + } else {
1571 + dma_cap_mask_t mask;
1572 +
1573 + dma_cap_zero(mask);
1574 + /* we don't care about the channel, any would work */
1575 + dma_cap_set(DMA_SLAVE, mask);
1576 + host->dma_chan_tx = dma_request_channel(mask, NULL, NULL);
1577 + host->dma_chan_rx = dma_request_channel(mask, NULL, NULL);
1578 + }
1579 +#endif
1580 + clk = devm_clk_get(dev, NULL);
1581 + if (IS_ERR(clk)) {
1582 + dev_err(dev, "could not get clk\n");
1583 + ret = PTR_ERR(clk);
1584 + goto err;
1585 + }
1586 +
1587 + host->max_clk = clk_get_rate(clk);
1588 +
1589 + host->irq = platform_get_irq(pdev, 0);
1590 + if (host->irq <= 0) {
1591 + dev_err(dev, "get IRQ failed\n");
1592 + ret = -EINVAL;
1593 + goto err;
1594 + }
1595 +
1596 + if (node) {
1597 + mmc_of_parse(mmc);
1598 +
1599 + /* Read any custom properties */
1600 + of_property_read_u32(node,
1601 + "brcm,overclock-50",
1602 + &host->overclock_50);
1603 + } else {
1604 + mmc->caps |= MMC_CAP_4_BIT_DATA;
1605 + }
1606 +
1607 + ret = bcm2835_mmc_add_host(host);
1608 + if (ret)
1609 + goto err;
1610 +
1611 + platform_set_drvdata(pdev, host);
1612 +
1613 + return 0;
1614 +err:
1615 + mmc_free_host(mmc);
1616 +
1617 + return ret;
1618 +}
1619 +
1620 +static int bcm2835_mmc_remove(struct platform_device *pdev)
1621 +{
1622 + struct bcm2835_host *host = platform_get_drvdata(pdev);
1623 + unsigned long flags;
1624 + int dead;
1625 + u32 scratch;
1626 +
1627 + dead = 0;
1628 + scratch = bcm2835_mmc_readl(host, SDHCI_INT_STATUS);
1629 + if (scratch == (u32)-1)
1630 + dead = 1;
1631 +
1632 +
1633 + if (dead) {
1634 + spin_lock_irqsave(&host->lock, flags);
1635 +
1636 + host->flags |= SDHCI_DEVICE_DEAD;
1637 +
1638 + if (host->mrq) {
1639 + pr_err("%s: Controller removed during "
1640 + " transfer!\n", mmc_hostname(host->mmc));
1641 +
1642 + host->mrq->cmd->error = -ENOMEDIUM;
1643 + tasklet_schedule(&host->finish_tasklet);
1644 + }
1645 +
1646 + spin_unlock_irqrestore(&host->lock, flags);
1647 + }
1648 +
1649 + mmc_remove_host(host->mmc);
1650 +
1651 + if (!dead)
1652 + bcm2835_mmc_reset(host, SDHCI_RESET_ALL);
1653 +
1654 + free_irq(host->irq, host);
1655 +
1656 + del_timer_sync(&host->timer);
1657 +
1658 + tasklet_kill(&host->finish_tasklet);
1659 +
1660 + mmc_free_host(host->mmc);
1661 + platform_set_drvdata(pdev, NULL);
1662 +
1663 + return 0;
1664 +}
1665 +
1666 +
1667 +static const struct of_device_id bcm2835_mmc_match[] = {
1668 + { .compatible = "brcm,bcm2835-mmc" },
1669 + { }
1670 +};
1671 +MODULE_DEVICE_TABLE(of, bcm2835_mmc_match);
1672 +
1673 +
1674 +
1675 +static struct platform_driver bcm2835_mmc_driver = {
1676 + .probe = bcm2835_mmc_probe,
1677 + .remove = bcm2835_mmc_remove,
1678 + .driver = {
1679 + .name = DRIVER_NAME,
1680 + .owner = THIS_MODULE,
1681 + .of_match_table = bcm2835_mmc_match,
1682 + },
1683 +};
1684 +module_platform_driver(bcm2835_mmc_driver);
1685 +
1686 +module_param(mmc_debug, uint, 0644);
1687 +module_param(mmc_debug2, uint, 0644);
1688 +MODULE_ALIAS("platform:mmc-bcm2835");
1689 +MODULE_DESCRIPTION("BCM2835 SDHCI driver");
1690 +MODULE_LICENSE("GPL v2");
1691 +MODULE_AUTHOR("Gellert Weisz");
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