target/linux/brcm2708/patches-4.4/0117-drm-vc4-A-few-more-non-functional-changes-to-sync-to.patch

   1 From a7d3659d3eefde8fc449f0ca33584a9490165d15 Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Tue, 8 Dec 2015 14:00:43 -0800
   4 Subject: [PATCH 117/423] drm/vc4: A few more non-functional changes to sync to
   5  upstream.
   6
   7 At this point all that's left is the force-enable of HDMI connector,
   8 and using direct firmware calls to turn on V3D instead of the generic
   9 power domain support.
  10
  11 Signed-off-by: Eric Anholt <eric@anholt.net>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_v3d.c |   2 +-
  14  include/uapi/drm/vc4_drm.h    | 182 +++++++++++++++++++++---------------------
  15  2 files changed, 92 insertions(+), 92 deletions(-)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_v3d.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_v3d.c
  19 @@ -109,7 +109,7 @@ static const struct {
  20
  21  int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused)
  22  {
  23 -       struct drm_info_node *node = (struct drm_info_node *) m->private;
  24 +       struct drm_info_node *node = (struct drm_info_node *)m->private;
  25         struct drm_device *dev = node->minor->dev;
  26         struct vc4_dev *vc4 = to_vc4_dev(dev);
  27         int i;
  28 --- a/include/uapi/drm/vc4_drm.h
  29 +++ b/include/uapi/drm/vc4_drm.h
  30 @@ -24,7 +24,7 @@
  31  #ifndef _UAPI_VC4_DRM_H_
  32  #define _UAPI_VC4_DRM_H_
  33
  34 -#include <drm/drm.h>
  35 +#include "drm.h"
  36
  37  #define DRM_VC4_SUBMIT_CL                         0x00
  38  #define DRM_VC4_WAIT_SEQNO                        0x01
  39 @@ -34,25 +34,25 @@
  40  #define DRM_VC4_CREATE_SHADER_BO                  0x05
  41  #define DRM_VC4_GET_HANG_STATE                    0x06
  42
  43 -#define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
  44 -#define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
  45 -#define DRM_IOCTL_VC4_WAIT_BO             DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
  46 -#define DRM_IOCTL_VC4_CREATE_BO           DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
  47 -#define DRM_IOCTL_VC4_MMAP_BO             DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
  48 -#define DRM_IOCTL_VC4_CREATE_SHADER_BO    DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
  49 -#define DRM_IOCTL_VC4_GET_HANG_STATE      DRM_IOWR( DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
  50 +#define DRM_IOCTL_VC4_SUBMIT_CL           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_SUBMIT_CL, struct drm_vc4_submit_cl)
  51 +#define DRM_IOCTL_VC4_WAIT_SEQNO          DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_SEQNO, struct drm_vc4_wait_seqno)
  52 +#define DRM_IOCTL_VC4_WAIT_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_WAIT_BO, struct drm_vc4_wait_bo)
  53 +#define DRM_IOCTL_VC4_CREATE_BO           DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_BO, struct drm_vc4_create_bo)
  54 +#define DRM_IOCTL_VC4_MMAP_BO             DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_MMAP_BO, struct drm_vc4_mmap_bo)
  55 +#define DRM_IOCTL_VC4_CREATE_SHADER_BO    DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_CREATE_SHADER_BO, struct drm_vc4_create_shader_bo)
  56 +#define DRM_IOCTL_VC4_GET_HANG_STATE      DRM_IOWR(DRM_COMMAND_BASE + DRM_VC4_GET_HANG_STATE, struct drm_vc4_get_hang_state)
  57
  58  struct drm_vc4_submit_rcl_surface {
  59 -       uint32_t hindex; /* Handle index, or ~0 if not present. */
  60 -       uint32_t offset; /* Offset to start of buffer. */
  61 +       __u32 hindex; /* Handle index, or ~0 if not present. */
  62 +       __u32 offset; /* Offset to start of buffer. */
  63         /*
  64 -         * Bits for either render config (color_write) or load/store packet.
  65 -         * Bits should all be 0 for MSAA load/stores.
  66 +        * Bits for either render config (color_write) or load/store packet.
  67 +        * Bits should all be 0 for MSAA load/stores.
  68          */
  69 -       uint16_t bits;
  70 +       __u16 bits;
  71
  72  #define VC4_SUBMIT_RCL_SURFACE_READ_IS_FULL_RES                (1 << 0)
  73 -       uint16_t flags;
  74 +       __u16 flags;
  75  };
  76
  77  /**
  78 @@ -76,7 +76,7 @@ struct drm_vc4_submit_cl {
  79          * then writes out the state updates and draw calls necessary per tile
  80          * to the tile allocation BO.
  81          */
  82 -       uint64_t bin_cl;
  83 +       __u64 bin_cl;
  84
  85         /* Pointer to the shader records.
  86          *
  87 @@ -85,16 +85,16 @@ struct drm_vc4_submit_cl {
  88          * reference to the shader record has enough information to determine
  89          * how many pointers are necessary (fixed number for shaders/uniforms,
  90          * and an attribute count), so those BO indices into bo_handles are
  91 -        * just stored as uint32_ts before each shader record passed in.
  92 +        * just stored as __u32s before each shader record passed in.
  93          */
  94 -       uint64_t shader_rec;
  95 +       __u64 shader_rec;
  96
  97         /* Pointer to uniform data and texture handles for the textures
  98          * referenced by the shader.
  99          *
 100          * For each shader state record, there is a set of uniform data in the
 101          * order referenced by the record (FS, VS, then CS).  Each set of
 102 -        * uniform data has a uint32_t index into bo_handles per texture
 103 +        * uniform data has a __u32 index into bo_handles per texture
 104          * sample operation, in the order the QPU_W_TMUn_S writes appear in
 105          * the program.  Following the texture BO handle indices is the actual
 106          * uniform data.
 107 @@ -103,52 +103,52 @@ struct drm_vc4_submit_cl {
 108          * because the kernel has to determine the sizes anyway during shader
 109          * code validation.
 110          */
 111 -       uint64_t uniforms;
 112 -       uint64_t bo_handles;
 113 +       __u64 uniforms;
 114 +       __u64 bo_handles;
 115
 116         /* Size in bytes of the binner command list. */
 117 -       uint32_t bin_cl_size;
 118 +       __u32 bin_cl_size;
 119         /* Size in bytes of the set of shader records. */
 120 -       uint32_t shader_rec_size;
 121 +       __u32 shader_rec_size;
 122         /* Number of shader records.
 123          *
 124          * This could just be computed from the contents of shader_records and
 125          * the address bits of references to them from the bin CL, but it
 126          * keeps the kernel from having to resize some allocations it makes.
 127          */
 128 -       uint32_t shader_rec_count;
 129 +       __u32 shader_rec_count;
 130         /* Size in bytes of the uniform state. */
 131 -       uint32_t uniforms_size;
 132 +       __u32 uniforms_size;
 133
 134         /* Number of BO handles passed in (size is that times 4). */
 135 -       uint32_t bo_handle_count;
 136 +       __u32 bo_handle_count;
 137
 138         /* RCL setup: */
 139 -       uint16_t width;
 140 -       uint16_t height;
 141 -       uint8_t min_x_tile;
 142 -       uint8_t min_y_tile;
 143 -       uint8_t max_x_tile;
 144 -       uint8_t max_y_tile;
 145 +       __u16 width;
 146 +       __u16 height;
 147 +       __u8 min_x_tile;
 148 +       __u8 min_y_tile;
 149 +       __u8 max_x_tile;
 150 +       __u8 max_y_tile;
 151         struct drm_vc4_submit_rcl_surface color_read;
 152         struct drm_vc4_submit_rcl_surface color_write;
 153         struct drm_vc4_submit_rcl_surface zs_read;
 154         struct drm_vc4_submit_rcl_surface zs_write;
 155         struct drm_vc4_submit_rcl_surface msaa_color_write;
 156         struct drm_vc4_submit_rcl_surface msaa_zs_write;
 157 -       uint32_t clear_color[2];
 158 -       uint32_t clear_z;
 159 -       uint8_t clear_s;
 160 +       __u32 clear_color[2];
 161 +       __u32 clear_z;
 162 +       __u8 clear_s;
 163
 164 -       uint32_t pad:24;
 165 +       __u32 pad:24;
 166
 167  #define VC4_SUBMIT_CL_USE_CLEAR_COLOR                  (1 << 0)
 168 -       uint32_t flags;
 169 +       __u32 flags;
 170
 171         /* Returned value of the seqno of this render job (for the
 172          * wait ioctl).
 173          */
 174 -       uint64_t seqno;
 175 +       __u64 seqno;
 176  };
 177
 178  /**
 179 @@ -159,8 +159,8 @@ struct drm_vc4_submit_cl {
 180   * block, just return the status."
 181   */
 182  struct drm_vc4_wait_seqno {
 183 -       uint64_t seqno;
 184 -       uint64_t timeout_ns;
 185 +       __u64 seqno;
 186 +       __u64 timeout_ns;
 187  };
 188
 189  /**
 190 @@ -172,9 +172,9 @@ struct drm_vc4_wait_seqno {
 191   * completed.
 192   */
 193  struct drm_vc4_wait_bo {
 194 -       uint32_t handle;
 195 -       uint32_t pad;
 196 -       uint64_t timeout_ns;
 197 +       __u32 handle;
 198 +       __u32 pad;
 199 +       __u64 timeout_ns;
 200  };
 201
 202  /**
 203 @@ -184,11 +184,30 @@ struct drm_vc4_wait_bo {
 204   * used in a future extension.
 205   */
 206  struct drm_vc4_create_bo {
 207 -       uint32_t size;
 208 -       uint32_t flags;
 209 +       __u32 size;
 210 +       __u32 flags;
 211         /** Returned GEM handle for the BO. */
 212 -       uint32_t handle;
 213 -       uint32_t pad;
 214 +       __u32 handle;
 215 +       __u32 pad;
 216 +};
 217 +
 218 +/**
 219 + * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
 220 + *
 221 + * This doesn't actually perform an mmap.  Instead, it returns the
 222 + * offset you need to use in an mmap on the DRM device node.  This
 223 + * means that tools like valgrind end up knowing about the mapped
 224 + * memory.
 225 + *
 226 + * There are currently no values for the flags argument, but it may be
 227 + * used in a future extension.
 228 + */
 229 +struct drm_vc4_mmap_bo {
 230 +       /** Handle for the object being mapped. */
 231 +       __u32 handle;
 232 +       __u32 flags;
 233 +       /** offset into the drm node to use for subsequent mmap call. */
 234 +       __u64 offset;
 235  };
 236
 237  /**
 238 @@ -201,43 +220,24 @@ struct drm_vc4_create_bo {
 239   */
 240  struct drm_vc4_create_shader_bo {
 241         /* Size of the data argument. */
 242 -       uint32_t size;
 243 +       __u32 size;
 244         /* Flags, currently must be 0. */
 245 -       uint32_t flags;
 246 +       __u32 flags;
 247
 248         /* Pointer to the data. */
 249 -       uint64_t data;
 250 +       __u64 data;
 251
 252         /** Returned GEM handle for the BO. */
 253 -       uint32_t handle;
 254 +       __u32 handle;
 255         /* Pad, must be 0. */
 256 -       uint32_t pad;
 257 -};
 258 -
 259 -/**
 260 - * struct drm_vc4_mmap_bo - ioctl argument for mapping VC4 BOs.
 261 - *
 262 - * This doesn't actually perform an mmap.  Instead, it returns the
 263 - * offset you need to use in an mmap on the DRM device node.  This
 264 - * means that tools like valgrind end up knowing about the mapped
 265 - * memory.
 266 - *
 267 - * There are currently no values for the flags argument, but it may be
 268 - * used in a future extension.
 269 - */
 270 -struct drm_vc4_mmap_bo {
 271 -       /** Handle for the object being mapped. */
 272 -       uint32_t handle;
 273 -       uint32_t flags;
 274 -       /** offset into the drm node to use for subsequent mmap call. */
 275 -       uint64_t offset;
 276 +       __u32 pad;
 277  };
 278
 279  struct drm_vc4_get_hang_state_bo {
 280 -       uint32_t handle;
 281 -       uint32_t paddr;
 282 -       uint32_t size;
 283 -       uint32_t pad;
 284 +       __u32 handle;
 285 +       __u32 paddr;
 286 +       __u32 size;
 287 +       __u32 pad;
 288  };
 289
 290  /**
 291 @@ -246,34 +246,34 @@ struct drm_vc4_get_hang_state_bo {
 292  */
 293  struct drm_vc4_get_hang_state {
 294         /** Pointer to array of struct drm_vc4_get_hang_state_bo. */
 295 -       uint64_t bo;
 296 +       __u64 bo;
 297         /**
 298          * On input, the size of the bo array.  Output is the number
 299          * of bos to be returned.
 300          */
 301 -       uint32_t bo_count;
 302 +       __u32 bo_count;
 303
 304 -       uint32_t start_bin, start_render;
 305 +       __u32 start_bin, start_render;
 306
 307 -       uint32_t ct0ca, ct0ea;
 308 -       uint32_t ct1ca, ct1ea;
 309 -       uint32_t ct0cs, ct1cs;
 310 -       uint32_t ct0ra0, ct1ra0;
 311 -
 312 -       uint32_t bpca, bpcs;
 313 -       uint32_t bpoa, bpos;
 314 -
 315 -       uint32_t vpmbase;
 316 -
 317 -       uint32_t dbge;
 318 -       uint32_t fdbgo;
 319 -       uint32_t fdbgb;
 320 -       uint32_t fdbgr;
 321 -       uint32_t fdbgs;
 322 -       uint32_t errstat;
 323 +       __u32 ct0ca, ct0ea;
 324 +       __u32 ct1ca, ct1ea;
 325 +       __u32 ct0cs, ct1cs;
 326 +       __u32 ct0ra0, ct1ra0;
 327 +
 328 +       __u32 bpca, bpcs;
 329 +       __u32 bpoa, bpos;
 330 +
 331 +       __u32 vpmbase;
 332 +
 333 +       __u32 dbge;
 334 +       __u32 fdbgo;
 335 +       __u32 fdbgb;
 336 +       __u32 fdbgr;
 337 +       __u32 fdbgs;
 338 +       __u32 errstat;
 339
 340         /* Pad that we may save more registers into in the future. */
 341 -       uint32_t pad[16];
 342 +       __u32 pad[16];
 343  };
 344
 345  #endif /* _UAPI_VC4_DRM_H_ */