target/linux/brcm2708/patches-4.4/0262-clk-bcm2835-reorganize-bcm2835_clock_array-assignmen.patch

   1 From 34db3e8f383a79ea01a1fee31270e779956ec939 Mon Sep 17 00:00:00 2001
   2 From: Martin Sperl <kernel@martin.sperl.org>
   3 Date: Mon, 29 Feb 2016 12:51:42 +0000
   4 Subject: [PATCH 262/381] clk: bcm2835: reorganize bcm2835_clock_array
   5  assignment
   6
   7 Reorganize bcm2835_clock_array so that there is no more
   8 need for separate bcm2835_*_data structures to be defined.
   9 Instead the required structures are generated inline via
  10 helper macros.
  11
  12 To allow this to also work for pll alone it was required that
  13 the parent_pll was changed from a pointer to bcm2835_pll_data
  14 to the name of the pll instead.
  15
  16 Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
  17 Signed-off-by: Eric Anholt <eric@anholt.net>
  18 Reviewed-by: Eric Anholt <eric@anholt.net>
  19 (cherry picked from commit 3b15afefbef9b5952e3d68ad73d93f981b9faca8)
  20 ---
  21  drivers/clk/bcm/clk-bcm2835.c | 852 +++++++++++++++++++-----------------------
  22  1 file changed, 393 insertions(+), 459 deletions(-)
  23
  24 --- a/drivers/clk/bcm/clk-bcm2835.c
  25 +++ b/drivers/clk/bcm/clk-bcm2835.c
  26 @@ -418,115 +418,10 @@ static const struct bcm2835_pll_ana_bits
  27         .fb_prediv_mask = BIT(11),
  28  };
  29
  30 -/*
  31 - * PLLA is the auxiliary PLL, used to drive the CCP2 (Compact Camera
  32 - * Port 2) transmitter clock.
  33 - *
  34 - * It is in the PX LDO power domain, which is on when the AUDIO domain
  35 - * is on.
  36 - */
  37 -static const struct bcm2835_pll_data bcm2835_plla_data = {
  38 -       .name = "plla",
  39 -       .cm_ctrl_reg = CM_PLLA,
  40 -       .a2w_ctrl_reg = A2W_PLLA_CTRL,
  41 -       .frac_reg = A2W_PLLA_FRAC,
  42 -       .ana_reg_base = A2W_PLLA_ANA0,
  43 -       .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
  44 -       .lock_mask = CM_LOCK_FLOCKA,
  45 -
  46 -       .ana = &bcm2835_ana_default,
  47 -
  48 -       .min_rate = 600000000u,
  49 -       .max_rate = 2400000000u,
  50 -       .max_fb_rate = BCM2835_MAX_FB_RATE,
  51 -};
  52 -
  53 -/* PLLB is used for the ARM's clock. */
  54 -static const struct bcm2835_pll_data bcm2835_pllb_data = {
  55 -       .name = "pllb",
  56 -       .cm_ctrl_reg = CM_PLLB,
  57 -       .a2w_ctrl_reg = A2W_PLLB_CTRL,
  58 -       .frac_reg = A2W_PLLB_FRAC,
  59 -       .ana_reg_base = A2W_PLLB_ANA0,
  60 -       .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
  61 -       .lock_mask = CM_LOCK_FLOCKB,
  62 -
  63 -       .ana = &bcm2835_ana_default,
  64 -
  65 -       .min_rate = 600000000u,
  66 -       .max_rate = 3000000000u,
  67 -       .max_fb_rate = BCM2835_MAX_FB_RATE,
  68 -};
  69 -
  70 -/*
  71 - * PLLC is the core PLL, used to drive the core VPU clock.
  72 - *
  73 - * It is in the PX LDO power domain, which is on when the AUDIO domain
  74 - * is on.
  75 -*/
  76 -static const struct bcm2835_pll_data bcm2835_pllc_data = {
  77 -       .name = "pllc",
  78 -       .cm_ctrl_reg = CM_PLLC,
  79 -       .a2w_ctrl_reg = A2W_PLLC_CTRL,
  80 -       .frac_reg = A2W_PLLC_FRAC,
  81 -       .ana_reg_base = A2W_PLLC_ANA0,
  82 -       .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
  83 -       .lock_mask = CM_LOCK_FLOCKC,
  84 -
  85 -       .ana = &bcm2835_ana_default,
  86 -
  87 -       .min_rate = 600000000u,
  88 -       .max_rate = 3000000000u,
  89 -       .max_fb_rate = BCM2835_MAX_FB_RATE,
  90 -};
  91 -
  92 -/*
  93 - * PLLD is the display PLL, used to drive DSI display panels.
  94 - *
  95 - * It is in the PX LDO power domain, which is on when the AUDIO domain
  96 - * is on.
  97 - */
  98 -static const struct bcm2835_pll_data bcm2835_plld_data = {
  99 -       .name = "plld",
 100 -       .cm_ctrl_reg = CM_PLLD,
 101 -       .a2w_ctrl_reg = A2W_PLLD_CTRL,
 102 -       .frac_reg = A2W_PLLD_FRAC,
 103 -       .ana_reg_base = A2W_PLLD_ANA0,
 104 -       .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
 105 -       .lock_mask = CM_LOCK_FLOCKD,
 106 -
 107 -       .ana = &bcm2835_ana_default,
 108 -
 109 -       .min_rate = 600000000u,
 110 -       .max_rate = 2400000000u,
 111 -       .max_fb_rate = BCM2835_MAX_FB_RATE,
 112 -};
 113 -
 114 -/*
 115 - * PLLH is used to supply the pixel clock or the AUX clock for the TV
 116 - * encoder.
 117 - *
 118 - * It is in the HDMI power domain.
 119 - */
 120 -static const struct bcm2835_pll_data bcm2835_pllh_data = {
 121 -       "pllh",
 122 -       .cm_ctrl_reg = CM_PLLH,
 123 -       .a2w_ctrl_reg = A2W_PLLH_CTRL,
 124 -       .frac_reg = A2W_PLLH_FRAC,
 125 -       .ana_reg_base = A2W_PLLH_ANA0,
 126 -       .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
 127 -       .lock_mask = CM_LOCK_FLOCKH,
 128 -
 129 -       .ana = &bcm2835_ana_pllh,
 130 -
 131 -       .min_rate = 600000000u,
 132 -       .max_rate = 3000000000u,
 133 -       .max_fb_rate = BCM2835_MAX_FB_RATE,
 134 -};
 135 -
 136  struct bcm2835_pll_divider_data {
 137         const char *name;
 138 -       const struct bcm2835_pll_data *source_pll;
 139 +       const char *source_pll;
 140 +
 141         u32 cm_reg;
 142         u32 a2w_reg;
 143
 144 @@ -535,124 +430,6 @@ struct bcm2835_pll_divider_data {
 145         u32 fixed_divider;
 146  };
 147
 148 -static const struct bcm2835_pll_divider_data bcm2835_plla_core_data = {
 149 -       .name = "plla_core",
 150 -       .source_pll = &bcm2835_plla_data,
 151 -       .cm_reg = CM_PLLA,
 152 -       .a2w_reg = A2W_PLLA_CORE,
 153 -       .load_mask = CM_PLLA_LOADCORE,
 154 -       .hold_mask = CM_PLLA_HOLDCORE,
 155 -       .fixed_divider = 1,
 156 -};
 157 -
 158 -static const struct bcm2835_pll_divider_data bcm2835_plla_per_data = {
 159 -       .name = "plla_per",
 160 -       .source_pll = &bcm2835_plla_data,
 161 -       .cm_reg = CM_PLLA,
 162 -       .a2w_reg = A2W_PLLA_PER,
 163 -       .load_mask = CM_PLLA_LOADPER,
 164 -       .hold_mask = CM_PLLA_HOLDPER,
 165 -       .fixed_divider = 1,
 166 -};
 167 -
 168 -static const struct bcm2835_pll_divider_data bcm2835_pllb_arm_data = {
 169 -       .name = "pllb_arm",
 170 -       .source_pll = &bcm2835_pllb_data,
 171 -       .cm_reg = CM_PLLB,
 172 -       .a2w_reg = A2W_PLLB_ARM,
 173 -       .load_mask = CM_PLLB_LOADARM,
 174 -       .hold_mask = CM_PLLB_HOLDARM,
 175 -       .fixed_divider = 1,
 176 -};
 177 -
 178 -static const struct bcm2835_pll_divider_data bcm2835_pllc_core0_data = {
 179 -       .name = "pllc_core0",
 180 -       .source_pll = &bcm2835_pllc_data,
 181 -       .cm_reg = CM_PLLC,
 182 -       .a2w_reg = A2W_PLLC_CORE0,
 183 -       .load_mask = CM_PLLC_LOADCORE0,
 184 -       .hold_mask = CM_PLLC_HOLDCORE0,
 185 -       .fixed_divider = 1,
 186 -};
 187 -
 188 -static const struct bcm2835_pll_divider_data bcm2835_pllc_core1_data = {
 189 -       .name = "pllc_core1", .source_pll = &bcm2835_pllc_data,
 190 -       .cm_reg = CM_PLLC, A2W_PLLC_CORE1,
 191 -       .load_mask = CM_PLLC_LOADCORE1,
 192 -       .hold_mask = CM_PLLC_HOLDCORE1,
 193 -       .fixed_divider = 1,
 194 -};
 195 -
 196 -static const struct bcm2835_pll_divider_data bcm2835_pllc_core2_data = {
 197 -       .name = "pllc_core2",
 198 -       .source_pll = &bcm2835_pllc_data,
 199 -       .cm_reg = CM_PLLC,
 200 -       .a2w_reg = A2W_PLLC_CORE2,
 201 -       .load_mask = CM_PLLC_LOADCORE2,
 202 -       .hold_mask = CM_PLLC_HOLDCORE2,
 203 -       .fixed_divider = 1,
 204 -};
 205 -
 206 -static const struct bcm2835_pll_divider_data bcm2835_pllc_per_data = {
 207 -       .name = "pllc_per",
 208 -       .source_pll = &bcm2835_pllc_data,
 209 -       .cm_reg = CM_PLLC,
 210 -       .a2w_reg = A2W_PLLC_PER,
 211 -       .load_mask = CM_PLLC_LOADPER,
 212 -       .hold_mask = CM_PLLC_HOLDPER,
 213 -       .fixed_divider = 1,
 214 -};
 215 -
 216 -static const struct bcm2835_pll_divider_data bcm2835_plld_core_data = {
 217 -       .name = "plld_core",
 218 -       .source_pll = &bcm2835_plld_data,
 219 -       .cm_reg = CM_PLLD,
 220 -       .a2w_reg = A2W_PLLD_CORE,
 221 -       .load_mask = CM_PLLD_LOADCORE,
 222 -       .hold_mask = CM_PLLD_HOLDCORE,
 223 -       .fixed_divider = 1,
 224 -};
 225 -
 226 -static const struct bcm2835_pll_divider_data bcm2835_plld_per_data = {
 227 -       .name = "plld_per",
 228 -       .source_pll = &bcm2835_plld_data,
 229 -       .cm_reg = CM_PLLD,
 230 -       .a2w_reg = A2W_PLLD_PER,
 231 -       .load_mask = CM_PLLD_LOADPER,
 232 -       .hold_mask = CM_PLLD_HOLDPER,
 233 -       .fixed_divider = 1,
 234 -};
 235 -
 236 -static const struct bcm2835_pll_divider_data bcm2835_pllh_rcal_data = {
 237 -       .name = "pllh_rcal",
 238 -       .source_pll = &bcm2835_pllh_data,
 239 -       .cm_reg = CM_PLLH,
 240 -       .a2w_reg = A2W_PLLH_RCAL,
 241 -       .load_mask = CM_PLLH_LOADRCAL,
 242 -       .hold_mask = 0,
 243 -       .fixed_divider = 10,
 244 -};
 245 -
 246 -static const struct bcm2835_pll_divider_data bcm2835_pllh_aux_data = {
 247 -       .name = "pllh_aux",
 248 -       .source_pll = &bcm2835_pllh_data,
 249 -       .cm_reg = CM_PLLH,
 250 -       .a2w_reg = A2W_PLLH_AUX,
 251 -       .load_mask = CM_PLLH_LOADAUX,
 252 -       .hold_mask = 0,
 253 -       .fixed_divider = 10,
 254 -};
 255 -
 256 -static const struct bcm2835_pll_divider_data bcm2835_pllh_pix_data = {
 257 -       .name = "pllh_pix",
 258 -       .source_pll = &bcm2835_pllh_data,
 259 -       .cm_reg = CM_PLLH,
 260 -       .a2w_reg = A2W_PLLH_PIX,
 261 -       .load_mask = CM_PLLH_LOADPIX,
 262 -       .hold_mask = 0,
 263 -       .fixed_divider = 10,
 264 -};
 265 -
 266  struct bcm2835_clock_data {
 267         const char *name;
 268
 269 @@ -671,188 +448,6 @@ struct bcm2835_clock_data {
 270         bool is_mash_clock;
 271  };
 272
 273 -static const char *const bcm2835_clock_per_parents[] = {
 274 -       "gnd",
 275 -       "xosc",
 276 -       "testdebug0",
 277 -       "testdebug1",
 278 -       "plla_per",
 279 -       "pllc_per",
 280 -       "plld_per",
 281 -       "pllh_aux",
 282 -};
 283 -
 284 -static const char *const bcm2835_clock_vpu_parents[] = {
 285 -       "gnd",
 286 -       "xosc",
 287 -       "testdebug0",
 288 -       "testdebug1",
 289 -       "plla_core",
 290 -       "pllc_core0",
 291 -       "plld_core",
 292 -       "pllh_aux",
 293 -       "pllc_core1",
 294 -       "pllc_core2",
 295 -};
 296 -
 297 -static const char *const bcm2835_clock_osc_parents[] = {
 298 -       "gnd",
 299 -       "xosc",
 300 -       "testdebug0",
 301 -       "testdebug1"
 302 -};
 303 -
 304 -/*
 305 - * Used for a 1Mhz clock for the system clocksource, and also used by
 306 - * the watchdog timer and the camera pulse generator.
 307 - */
 308 -static const struct bcm2835_clock_data bcm2835_clock_timer_data = {
 309 -       .name = "timer",
 310 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
 311 -       .parents = bcm2835_clock_osc_parents,
 312 -       .ctl_reg = CM_TIMERCTL,
 313 -       .div_reg = CM_TIMERDIV,
 314 -       .int_bits = 6,
 315 -       .frac_bits = 12,
 316 -};
 317 -
 318 -/* One Time Programmable Memory clock.  Maximum 10Mhz. */
 319 -static const struct bcm2835_clock_data bcm2835_clock_otp_data = {
 320 -       .name = "otp",
 321 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
 322 -       .parents = bcm2835_clock_osc_parents,
 323 -       .ctl_reg = CM_OTPCTL,
 324 -       .div_reg = CM_OTPDIV,
 325 -       .int_bits = 4,
 326 -       .frac_bits = 0,
 327 -};
 328 -
 329 -/*
 330 - * VPU clock.  This doesn't have an enable bit, since it drives the
 331 - * bus for everything else, and is special so it doesn't need to be
 332 - * gated for rate changes.  It is also known as "clk_audio" in various
 333 - * hardware documentation.
 334 - */
 335 -static const struct bcm2835_clock_data bcm2835_clock_vpu_data = {
 336 -       .name = "vpu",
 337 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
 338 -       .parents = bcm2835_clock_vpu_parents,
 339 -       .ctl_reg = CM_VPUCTL,
 340 -       .div_reg = CM_VPUDIV,
 341 -       .int_bits = 12,
 342 -       .frac_bits = 8,
 343 -       .is_vpu_clock = true,
 344 -};
 345 -
 346 -static const struct bcm2835_clock_data bcm2835_clock_v3d_data = {
 347 -       .name = "v3d",
 348 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
 349 -       .parents = bcm2835_clock_vpu_parents,
 350 -       .ctl_reg = CM_V3DCTL,
 351 -       .div_reg = CM_V3DDIV,
 352 -       .int_bits = 4,
 353 -       .frac_bits = 8,
 354 -};
 355 -
 356 -static const struct bcm2835_clock_data bcm2835_clock_isp_data = {
 357 -       .name = "isp",
 358 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
 359 -       .parents = bcm2835_clock_vpu_parents,
 360 -       .ctl_reg = CM_ISPCTL,
 361 -       .div_reg = CM_ISPDIV,
 362 -       .int_bits = 4,
 363 -       .frac_bits = 8,
 364 -};
 365 -
 366 -static const struct bcm2835_clock_data bcm2835_clock_h264_data = {
 367 -       .name = "h264",
 368 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
 369 -       .parents = bcm2835_clock_vpu_parents,
 370 -       .ctl_reg = CM_H264CTL,
 371 -       .div_reg = CM_H264DIV,
 372 -       .int_bits = 4,
 373 -       .frac_bits = 8,
 374 -};
 375 -
 376 -/* TV encoder clock.  Only operating frequency is 108Mhz.  */
 377 -static const struct bcm2835_clock_data bcm2835_clock_vec_data = {
 378 -       .name = "vec",
 379 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
 380 -       .parents = bcm2835_clock_per_parents,
 381 -       .ctl_reg = CM_VECCTL,
 382 -       .div_reg = CM_VECDIV,
 383 -       .int_bits = 4,
 384 -       .frac_bits = 0,
 385 -};
 386 -
 387 -static const struct bcm2835_clock_data bcm2835_clock_uart_data = {
 388 -       .name = "uart",
 389 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
 390 -       .parents = bcm2835_clock_per_parents,
 391 -       .ctl_reg = CM_UARTCTL,
 392 -       .div_reg = CM_UARTDIV,
 393 -       .int_bits = 10,
 394 -       .frac_bits = 12,
 395 -};
 396 -
 397 -/* HDMI state machine */
 398 -static const struct bcm2835_clock_data bcm2835_clock_hsm_data = {
 399 -       .name = "hsm",
 400 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
 401 -       .parents = bcm2835_clock_per_parents,
 402 -       .ctl_reg = CM_HSMCTL,
 403 -       .div_reg = CM_HSMDIV,
 404 -       .int_bits = 4,
 405 -       .frac_bits = 8,
 406 -};
 407 -
 408 -/*
 409 - * Secondary SDRAM clock.  Used for low-voltage modes when the PLL in
 410 - * the SDRAM controller can't be used.
 411 - */
 412 -static const struct bcm2835_clock_data bcm2835_clock_sdram_data = {
 413 -       .name = "sdram",
 414 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),
 415 -       .parents = bcm2835_clock_vpu_parents,
 416 -       .ctl_reg = CM_SDCCTL,
 417 -       .div_reg = CM_SDCDIV,
 418 -       .int_bits = 6,
 419 -       .frac_bits = 0,
 420 -};
 421 -
 422 -/* Clock for the temperature sensor.  Generally run at 2Mhz, max 5Mhz. */
 423 -static const struct bcm2835_clock_data bcm2835_clock_tsens_data = {
 424 -       .name = "tsens",
 425 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),
 426 -       .parents = bcm2835_clock_osc_parents,
 427 -       .ctl_reg = CM_TSENSCTL,
 428 -       .div_reg = CM_TSENSDIV,
 429 -       .int_bits = 5,
 430 -       .frac_bits = 0,
 431 -};
 432 -
 433 -/* Arasan EMMC clock */
 434 -static const struct bcm2835_clock_data bcm2835_clock_emmc_data = {
 435 -       .name = "emmc",
 436 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
 437 -       .parents = bcm2835_clock_per_parents,
 438 -       .ctl_reg = CM_EMMCCTL,
 439 -       .div_reg = CM_EMMCDIV,
 440 -       .int_bits = 4,
 441 -       .frac_bits = 8,
 442 -};
 443 -
 444 -static const struct bcm2835_clock_data bcm2835_clock_pwm_data = {
 445 -       .name = "pwm",
 446 -       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),
 447 -       .parents = bcm2835_clock_per_parents,
 448 -       .ctl_reg = CM_PWMCTL,
 449 -       .div_reg = CM_PWMDIV,
 450 -       .int_bits = 12,
 451 -       .frac_bits = 12,
 452 -       .is_mash_clock = true,
 453 -};
 454 -
 455  struct bcm2835_gate_data {
 456         const char *name;
 457         const char *parent;
 458 @@ -860,18 +455,6 @@ struct bcm2835_gate_data {
 459         u32 ctl_reg;
 460  };
 461
 462 -/*
 463 - * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
 464 - * you have the debug bit set in the power manager, which we
 465 - * don't bother exposing) are individual gates off of the
 466 - * non-stop vpu clock.
 467 - */
 468 -static const struct bcm2835_gate_data bcm2835_clock_peri_image_data = {
 469 -       .name = "peri_image",
 470 -       .parent = "vpu",
 471 -       .ctl_reg = CM_PERIICTL,
 472 -};
 473 -
 474  struct bcm2835_pll {
 475         struct clk_hw hw;
 476         struct bcm2835_cprman *cprman;
 477 @@ -1594,7 +1177,7 @@ bcm2835_register_pll_divider(struct bcm2
 478
 479         memset(&init, 0, sizeof(init));
 480
 481 -       init.parent_names = &data->source_pll->name;
 482 +       init.parent_names = &data->source_pll;
 483         init.num_parents = 1;
 484         init.name = divider_name;
 485         init.ops = &bcm2835_pll_divider_clk_ops;
 486 @@ -1693,50 +1276,401 @@ struct bcm2835_clk_desc {
 487         const void *data;
 488  };
 489
 490 -#define _REGISTER(f, d) { .clk_register = (bcm2835_clk_register)f, \
 491 -                         .data = d }
 492 -#define REGISTER_PLL(d)                _REGISTER(&bcm2835_register_pll, d)
 493 -#define REGISTER_PLL_DIV(d)    _REGISTER(&bcm2835_register_pll_divider, d)
 494 -#define REGISTER_CLK(d)                _REGISTER(&bcm2835_register_clock, d)
 495 -#define REGISTER_GATE(d)       _REGISTER(&bcm2835_register_gate, d)
 496 +/* assignment helper macros for different clock types */
 497 +#define _REGISTER(f, ...) { .clk_register = (bcm2835_clk_register)f, \
 498 +                           .data = __VA_ARGS__ }
 499 +#define REGISTER_PLL(...)      _REGISTER(&bcm2835_register_pll,        \
 500 +                                         &(struct bcm2835_pll_data)    \
 501 +                                         {__VA_ARGS__})
 502 +#define REGISTER_PLL_DIV(...)  _REGISTER(&bcm2835_register_pll_divider, \
 503 +                                         &(struct bcm2835_pll_divider_data) \
 504 +                                         {__VA_ARGS__})
 505 +#define REGISTER_CLK(...)      _REGISTER(&bcm2835_register_clock,      \
 506 +                                         &(struct bcm2835_clock_data)  \
 507 +                                         {__VA_ARGS__})
 508 +#define REGISTER_GATE(...)     _REGISTER(&bcm2835_register_gate,       \
 509 +                                         &(struct bcm2835_gate_data)   \
 510 +                                         {__VA_ARGS__})
 511 +
 512 +/* parent mux arrays plus helper macros */
 513 +
 514 +/* main oscillator parent mux */
 515 +static const char *const bcm2835_clock_osc_parents[] = {
 516 +       "gnd",
 517 +       "xosc",
 518 +       "testdebug0",
 519 +       "testdebug1"
 520 +};
 521 +
 522 +#define REGISTER_OSC_CLK(...)  REGISTER_CLK(                           \
 523 +       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_osc_parents),       \
 524 +       .parents = bcm2835_clock_osc_parents,                           \
 525 +       __VA_ARGS__)
 526 +
 527 +/* main peripherial parent mux */
 528 +static const char *const bcm2835_clock_per_parents[] = {
 529 +       "gnd",
 530 +       "xosc",
 531 +       "testdebug0",
 532 +       "testdebug1",
 533 +       "plla_per",
 534 +       "pllc_per",
 535 +       "plld_per",
 536 +       "pllh_aux",
 537 +};
 538 +
 539 +#define REGISTER_PER_CLK(...)  REGISTER_CLK(                           \
 540 +       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_per_parents),       \
 541 +       .parents = bcm2835_clock_per_parents,                           \
 542 +       __VA_ARGS__)
 543 +
 544 +/* main vpu parent mux */
 545 +static const char *const bcm2835_clock_vpu_parents[] = {
 546 +       "gnd",
 547 +       "xosc",
 548 +       "testdebug0",
 549 +       "testdebug1",
 550 +       "plla_core",
 551 +       "pllc_core0",
 552 +       "plld_core",
 553 +       "pllh_aux",
 554 +       "pllc_core1",
 555 +       "pllc_core2",
 556 +};
 557 +
 558 +#define REGISTER_VPU_CLK(...)  REGISTER_CLK(                           \
 559 +       .num_mux_parents = ARRAY_SIZE(bcm2835_clock_vpu_parents),       \
 560 +       .parents = bcm2835_clock_vpu_parents,                           \
 561 +       __VA_ARGS__)
 562
 563 +/*
 564 + * the real definition of all the pll, pll_dividers and clocks
 565 + * these make use of the above REGISTER_* macros
 566 + */
 567  static const struct bcm2835_clk_desc clk_desc_array[] = {
 568 -       /* register PLL */
 569 -       [BCM2835_PLLA]          = REGISTER_PLL(&bcm2835_plla_data),
 570 -       [BCM2835_PLLB]          = REGISTER_PLL(&bcm2835_pllb_data),
 571 -       [BCM2835_PLLC]          = REGISTER_PLL(&bcm2835_pllc_data),
 572 -       [BCM2835_PLLD]          = REGISTER_PLL(&bcm2835_plld_data),
 573 -       [BCM2835_PLLH]          = REGISTER_PLL(&bcm2835_pllh_data),
 574 -       /* the PLL dividers */
 575 -       [BCM2835_PLLA_CORE]     = REGISTER_PLL_DIV(&bcm2835_plla_core_data),
 576 -       [BCM2835_PLLA_PER]      = REGISTER_PLL_DIV(&bcm2835_plla_per_data),
 577 -       [BCM2835_PLLC_CORE0]    = REGISTER_PLL_DIV(&bcm2835_pllc_core0_data),
 578 -       [BCM2835_PLLC_CORE1]    = REGISTER_PLL_DIV(&bcm2835_pllc_core1_data),
 579 -       [BCM2835_PLLC_CORE2]    = REGISTER_PLL_DIV(&bcm2835_pllc_core2_data),
 580 -       [BCM2835_PLLC_PER]      = REGISTER_PLL_DIV(&bcm2835_pllc_per_data),
 581 -       [BCM2835_PLLD_CORE]     = REGISTER_PLL_DIV(&bcm2835_plld_core_data),
 582 -       [BCM2835_PLLD_PER]      = REGISTER_PLL_DIV(&bcm2835_plld_per_data),
 583 -       [BCM2835_PLLH_RCAL]     = REGISTER_PLL_DIV(&bcm2835_pllh_rcal_data),
 584 -       [BCM2835_PLLH_AUX]      = REGISTER_PLL_DIV(&bcm2835_pllh_aux_data),
 585 -       [BCM2835_PLLH_PIX]      = REGISTER_PLL_DIV(&bcm2835_pllh_pix_data),
 586 +       /* the PLL + PLL dividers */
 587 +
 588 +       /*
 589 +        * PLLA is the auxiliary PLL, used to drive the CCP2
 590 +        * (Compact Camera Port 2) transmitter clock.
 591 +        *
 592 +        * It is in the PX LDO power domain, which is on when the
 593 +        * AUDIO domain is on.
 594 +        */
 595 +       [BCM2835_PLLA]          = REGISTER_PLL(
 596 +               .name = "plla",
 597 +               .cm_ctrl_reg = CM_PLLA,
 598 +               .a2w_ctrl_reg = A2W_PLLA_CTRL,
 599 +               .frac_reg = A2W_PLLA_FRAC,
 600 +               .ana_reg_base = A2W_PLLA_ANA0,
 601 +               .reference_enable_mask = A2W_XOSC_CTRL_PLLA_ENABLE,
 602 +               .lock_mask = CM_LOCK_FLOCKA,
 603 +
 604 +               .ana = &bcm2835_ana_default,
 605 +
 606 +               .min_rate = 600000000u,
 607 +               .max_rate = 2400000000u,
 608 +               .max_fb_rate = BCM2835_MAX_FB_RATE),
 609 +       [BCM2835_PLLA_CORE]     = REGISTER_PLL_DIV(
 610 +               .name = "plla_core",
 611 +               .source_pll = "plla",
 612 +               .cm_reg = CM_PLLA,
 613 +               .a2w_reg = A2W_PLLA_CORE,
 614 +               .load_mask = CM_PLLA_LOADCORE,
 615 +               .hold_mask = CM_PLLA_HOLDCORE,
 616 +               .fixed_divider = 1),
 617 +       [BCM2835_PLLA_PER]      = REGISTER_PLL_DIV(
 618 +               .name = "plla_per",
 619 +               .source_pll = "plla",
 620 +               .cm_reg = CM_PLLA,
 621 +               .a2w_reg = A2W_PLLA_PER,
 622 +               .load_mask = CM_PLLA_LOADPER,
 623 +               .hold_mask = CM_PLLA_HOLDPER,
 624 +               .fixed_divider = 1),
 625 +
 626 +       /* PLLB is used for the ARM's clock. */
 627 +       [BCM2835_PLLB]          = REGISTER_PLL(
 628 +               .name = "pllb",
 629 +               .cm_ctrl_reg = CM_PLLB,
 630 +               .a2w_ctrl_reg = A2W_PLLB_CTRL,
 631 +               .frac_reg = A2W_PLLB_FRAC,
 632 +               .ana_reg_base = A2W_PLLB_ANA0,
 633 +               .reference_enable_mask = A2W_XOSC_CTRL_PLLB_ENABLE,
 634 +               .lock_mask = CM_LOCK_FLOCKB,
 635 +
 636 +               .ana = &bcm2835_ana_default,
 637 +
 638 +               .min_rate = 600000000u,
 639 +               .max_rate = 3000000000u,
 640 +               .max_fb_rate = BCM2835_MAX_FB_RATE),
 641 +       [BCM2835_PLLB_ARM]      = REGISTER_PLL_DIV(
 642 +               .name = "pllb_arm",
 643 +               .source_pll = "pllb",
 644 +               .cm_reg = CM_PLLB,
 645 +               .a2w_reg = A2W_PLLB_ARM,
 646 +               .load_mask = CM_PLLB_LOADARM,
 647 +               .hold_mask = CM_PLLB_HOLDARM,
 648 +               .fixed_divider = 1),
 649 +
 650 +       /*
 651 +        * PLLC is the core PLL, used to drive the core VPU clock.
 652 +        *
 653 +        * It is in the PX LDO power domain, which is on when the
 654 +        * AUDIO domain is on.
 655 +        */
 656 +       [BCM2835_PLLC]          = REGISTER_PLL(
 657 +               .name = "pllc",
 658 +               .cm_ctrl_reg = CM_PLLC,
 659 +               .a2w_ctrl_reg = A2W_PLLC_CTRL,
 660 +               .frac_reg = A2W_PLLC_FRAC,
 661 +               .ana_reg_base = A2W_PLLC_ANA0,
 662 +               .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
 663 +               .lock_mask = CM_LOCK_FLOCKC,
 664 +
 665 +               .ana = &bcm2835_ana_default,
 666 +
 667 +               .min_rate = 600000000u,
 668 +               .max_rate = 3000000000u,
 669 +               .max_fb_rate = BCM2835_MAX_FB_RATE),
 670 +       [BCM2835_PLLC_CORE0]    = REGISTER_PLL_DIV(
 671 +               .name = "pllc_core0",
 672 +               .source_pll = "pllc",
 673 +               .cm_reg = CM_PLLC,
 674 +               .a2w_reg = A2W_PLLC_CORE0,
 675 +               .load_mask = CM_PLLC_LOADCORE0,
 676 +               .hold_mask = CM_PLLC_HOLDCORE0,
 677 +               .fixed_divider = 1),
 678 +       [BCM2835_PLLC_CORE1]    = REGISTER_PLL_DIV(
 679 +               .name = "pllc_core1",
 680 +               .source_pll = "pllc",
 681 +               .cm_reg = CM_PLLC,
 682 +               .a2w_reg = A2W_PLLC_CORE1,
 683 +               .load_mask = CM_PLLC_LOADCORE1,
 684 +               .hold_mask = CM_PLLC_HOLDCORE1,
 685 +               .fixed_divider = 1),
 686 +       [BCM2835_PLLC_CORE2]    = REGISTER_PLL_DIV(
 687 +               .name = "pllc_core2",
 688 +               .source_pll = "pllc",
 689 +               .cm_reg = CM_PLLC,
 690 +               .a2w_reg = A2W_PLLC_CORE2,
 691 +               .load_mask = CM_PLLC_LOADCORE2,
 692 +               .hold_mask = CM_PLLC_HOLDCORE2,
 693 +               .fixed_divider = 1),
 694 +       [BCM2835_PLLC_PER]      = REGISTER_PLL_DIV(
 695 +               .name = "pllc_per",
 696 +               .source_pll = "pllc",
 697 +               .cm_reg = CM_PLLC,
 698 +               .a2w_reg = A2W_PLLC_PER,
 699 +               .load_mask = CM_PLLC_LOADPER,
 700 +               .hold_mask = CM_PLLC_HOLDPER,
 701 +               .fixed_divider = 1),
 702 +
 703 +       /*
 704 +        * PLLD is the display PLL, used to drive DSI display panels.
 705 +        *
 706 +        * It is in the PX LDO power domain, which is on when the
 707 +        * AUDIO domain is on.
 708 +        */
 709 +       [BCM2835_PLLD]          = REGISTER_PLL(
 710 +               .name = "plld",
 711 +               .cm_ctrl_reg = CM_PLLD,
 712 +               .a2w_ctrl_reg = A2W_PLLD_CTRL,
 713 +               .frac_reg = A2W_PLLD_FRAC,
 714 +               .ana_reg_base = A2W_PLLD_ANA0,
 715 +               .reference_enable_mask = A2W_XOSC_CTRL_DDR_ENABLE,
 716 +               .lock_mask = CM_LOCK_FLOCKD,
 717 +
 718 +               .ana = &bcm2835_ana_default,
 719 +
 720 +               .min_rate = 600000000u,
 721 +               .max_rate = 2400000000u,
 722 +               .max_fb_rate = BCM2835_MAX_FB_RATE),
 723 +       [BCM2835_PLLD_CORE]     = REGISTER_PLL_DIV(
 724 +               .name = "plld_core",
 725 +               .source_pll = "plld",
 726 +               .cm_reg = CM_PLLD,
 727 +               .a2w_reg = A2W_PLLD_CORE,
 728 +               .load_mask = CM_PLLD_LOADCORE,
 729 +               .hold_mask = CM_PLLD_HOLDCORE,
 730 +               .fixed_divider = 1),
 731 +       [BCM2835_PLLD_PER]      = REGISTER_PLL_DIV(
 732 +               .name = "plld_per",
 733 +               .source_pll = "plld",
 734 +               .cm_reg = CM_PLLD,
 735 +               .a2w_reg = A2W_PLLD_PER,
 736 +               .load_mask = CM_PLLD_LOADPER,
 737 +               .hold_mask = CM_PLLD_HOLDPER,
 738 +               .fixed_divider = 1),
 739 +
 740 +       /*
 741 +        * PLLH is used to supply the pixel clock or the AUX clock for the
 742 +        * TV encoder.
 743 +        *
 744 +        * It is in the HDMI power domain.
 745 +        */
 746 +       [BCM2835_PLLH]          = REGISTER_PLL(
 747 +               "pllh",
 748 +               .cm_ctrl_reg = CM_PLLH,
 749 +               .a2w_ctrl_reg = A2W_PLLH_CTRL,
 750 +               .frac_reg = A2W_PLLH_FRAC,
 751 +               .ana_reg_base = A2W_PLLH_ANA0,
 752 +               .reference_enable_mask = A2W_XOSC_CTRL_PLLC_ENABLE,
 753 +               .lock_mask = CM_LOCK_FLOCKH,
 754 +
 755 +               .ana = &bcm2835_ana_pllh,
 756 +
 757 +               .min_rate = 600000000u,
 758 +               .max_rate = 3000000000u,
 759 +               .max_fb_rate = BCM2835_MAX_FB_RATE),
 760 +       [BCM2835_PLLH_RCAL]     = REGISTER_PLL_DIV(
 761 +               .name = "pllh_rcal",
 762 +               .source_pll = "pllh",
 763 +               .cm_reg = CM_PLLH,
 764 +               .a2w_reg = A2W_PLLH_RCAL,
 765 +               .load_mask = CM_PLLH_LOADRCAL,
 766 +               .hold_mask = 0,
 767 +               .fixed_divider = 10),
 768 +       [BCM2835_PLLH_AUX]      = REGISTER_PLL_DIV(
 769 +               .name = "pllh_aux",
 770 +               .source_pll = "pllh",
 771 +               .cm_reg = CM_PLLH,
 772 +               .a2w_reg = A2W_PLLH_AUX,
 773 +               .load_mask = CM_PLLH_LOADAUX,
 774 +               .hold_mask = 0,
 775 +               .fixed_divider = 10),
 776 +       [BCM2835_PLLH_PIX]      = REGISTER_PLL_DIV(
 777 +               .name = "pllh_pix",
 778 +               .source_pll = "pllh",
 779 +               .cm_reg = CM_PLLH,
 780 +               .a2w_reg = A2W_PLLH_PIX,
 781 +               .load_mask = CM_PLLH_LOADPIX,
 782 +               .hold_mask = 0,
 783 +               .fixed_divider = 10),
 784 +
 785         /* the clocks */
 786 -       [BCM2835_CLOCK_TIMER]   = REGISTER_CLK(&bcm2835_clock_timer_data),
 787 -       [BCM2835_CLOCK_OTP]     = REGISTER_CLK(&bcm2835_clock_otp_data),
 788 -       [BCM2835_CLOCK_TSENS]   = REGISTER_CLK(&bcm2835_clock_tsens_data),
 789 -       [BCM2835_CLOCK_VPU]     = REGISTER_CLK(&bcm2835_clock_vpu_data),
 790 -       [BCM2835_CLOCK_V3D]     = REGISTER_CLK(&bcm2835_clock_v3d_data),
 791 -       [BCM2835_CLOCK_ISP]     = REGISTER_CLK(&bcm2835_clock_isp_data),
 792 -       [BCM2835_CLOCK_H264]    = REGISTER_CLK(&bcm2835_clock_h264_data),
 793 -       [BCM2835_CLOCK_V3D]     = REGISTER_CLK(&bcm2835_clock_v3d_data),
 794 -       [BCM2835_CLOCK_SDRAM]   = REGISTER_CLK(&bcm2835_clock_sdram_data),
 795 -       [BCM2835_CLOCK_UART]    = REGISTER_CLK(&bcm2835_clock_uart_data),
 796 -       [BCM2835_CLOCK_VEC]     = REGISTER_CLK(&bcm2835_clock_vec_data),
 797 -       [BCM2835_CLOCK_HSM]     = REGISTER_CLK(&bcm2835_clock_hsm_data),
 798 -       [BCM2835_CLOCK_EMMC]    = REGISTER_CLK(&bcm2835_clock_emmc_data),
 799 -       [BCM2835_CLOCK_PWM]     = REGISTER_CLK(&bcm2835_clock_pwm_data),
 800 +
 801 +       /* clocks with oscillator parent mux */
 802 +
 803 +       /* One Time Programmable Memory clock.  Maximum 10Mhz. */
 804 +       [BCM2835_CLOCK_OTP]     = REGISTER_OSC_CLK(
 805 +               .name = "otp",
 806 +               .ctl_reg = CM_OTPCTL,
 807 +               .div_reg = CM_OTPDIV,
 808 +               .int_bits = 4,
 809 +               .frac_bits = 0),
 810 +       /*
 811 +        * Used for a 1Mhz clock for the system clocksource, and also used
 812 +        * bythe watchdog timer and the camera pulse generator.
 813 +        */
 814 +       [BCM2835_CLOCK_TIMER]   = REGISTER_OSC_CLK(
 815 +               .name = "timer",
 816 +               .ctl_reg = CM_TIMERCTL,
 817 +               .div_reg = CM_TIMERDIV,
 818 +               .int_bits = 6,
 819 +               .frac_bits = 12),
 820 +       /*
 821 +        * Clock for the temperature sensor.
 822 +        * Generally run at 2Mhz, max 5Mhz.
 823 +        */
 824 +       [BCM2835_CLOCK_TSENS]   = REGISTER_OSC_CLK(
 825 +               .name = "tsens",
 826 +               .ctl_reg = CM_TSENSCTL,
 827 +               .div_reg = CM_TSENSDIV,
 828 +               .int_bits = 5,
 829 +               .frac_bits = 0),
 830 +
 831 +       /* clocks with vpu parent mux */
 832 +       [BCM2835_CLOCK_H264]    = REGISTER_VPU_CLK(
 833 +               .name = "h264",
 834 +               .ctl_reg = CM_H264CTL,
 835 +               .div_reg = CM_H264DIV,
 836 +               .int_bits = 4,
 837 +               .frac_bits = 8),
 838 +       [BCM2835_CLOCK_ISP]     = REGISTER_VPU_CLK(
 839 +               .name = "isp",
 840 +               .ctl_reg = CM_ISPCTL,
 841 +               .div_reg = CM_ISPDIV,
 842 +               .int_bits = 4,
 843 +               .frac_bits = 8),
 844 +       /*
 845 +        * Secondary SDRAM clock.  Used for low-voltage modes when the PLL
 846 +        * in the SDRAM controller can't be used.
 847 +        */
 848 +       [BCM2835_CLOCK_SDRAM]   = REGISTER_VPU_CLK(
 849 +               .name = "sdram",
 850 +               .ctl_reg = CM_SDCCTL,
 851 +               .div_reg = CM_SDCDIV,
 852 +               .int_bits = 6,
 853 +               .frac_bits = 0),
 854 +       [BCM2835_CLOCK_V3D]     = REGISTER_VPU_CLK(
 855 +               .name = "v3d",
 856 +               .ctl_reg = CM_V3DCTL,
 857 +               .div_reg = CM_V3DDIV,
 858 +               .int_bits = 4,
 859 +               .frac_bits = 8),
 860 +       /*
 861 +        * VPU clock.  This doesn't have an enable bit, since it drives
 862 +        * the bus for everything else, and is special so it doesn't need
 863 +        * to be gated for rate changes.  It is also known as "clk_audio"
 864 +        * in various hardware documentation.
 865 +        */
 866 +       [BCM2835_CLOCK_VPU]     = REGISTER_VPU_CLK(
 867 +               .name = "vpu",
 868 +               .ctl_reg = CM_VPUCTL,
 869 +               .div_reg = CM_VPUDIV,
 870 +               .int_bits = 12,
 871 +               .frac_bits = 8,
 872 +               .is_vpu_clock = true),
 873 +
 874 +       /* clocks with per parent mux */
 875 +
 876 +       /* Arasan EMMC clock */
 877 +       [BCM2835_CLOCK_EMMC]    = REGISTER_PER_CLK(
 878 +               .name = "emmc",
 879 +               .ctl_reg = CM_EMMCCTL,
 880 +               .div_reg = CM_EMMCDIV,
 881 +               .int_bits = 4,
 882 +               .frac_bits = 8),
 883 +       /* HDMI state machine */
 884 +       [BCM2835_CLOCK_HSM]     = REGISTER_PER_CLK(
 885 +               .name = "hsm",
 886 +               .ctl_reg = CM_HSMCTL,
 887 +               .div_reg = CM_HSMDIV,
 888 +               .int_bits = 4,
 889 +               .frac_bits = 8),
 890 +       [BCM2835_CLOCK_PWM]     = REGISTER_PER_CLK(
 891 +               .name = "pwm",
 892 +               .ctl_reg = CM_PWMCTL,
 893 +               .div_reg = CM_PWMDIV,
 894 +               .int_bits = 12,
 895 +               .frac_bits = 12,
 896 +               .is_mash_clock = true),
 897 +       [BCM2835_CLOCK_UART]    = REGISTER_PER_CLK(
 898 +               .name = "uart",
 899 +               .ctl_reg = CM_UARTCTL,
 900 +               .div_reg = CM_UARTDIV,
 901 +               .int_bits = 10,
 902 +               .frac_bits = 12),
 903 +       /* TV encoder clock.  Only operating frequency is 108Mhz.  */
 904 +       [BCM2835_CLOCK_VEC]     = REGISTER_PER_CLK(
 905 +               .name = "vec",
 906 +               .ctl_reg = CM_VECCTL,
 907 +               .div_reg = CM_VECDIV,
 908 +               .int_bits = 4,
 909 +               .frac_bits = 0),
 910 +
 911         /* the gates */
 912 +
 913 +       /*
 914 +        * CM_PERIICTL (and CM_PERIACTL, CM_SYSCTL and CM_VPUCTL if
 915 +        * you have the debug bit set in the power manager, which we
 916 +        * don't bother exposing) are individual gates off of the
 917 +        * non-stop vpu clock.
 918 +        */
 919         [BCM2835_CLOCK_PERI_IMAGE] = REGISTER_GATE(
 920 -               &bcm2835_clock_peri_image_data),
 921 +               .name = "peri_image",
 922 +               .parent = "vpu",
 923 +               .ctl_reg = CM_PERIICTL),
 924  };
 925
 926  static int bcm2835_clk_probe(struct platform_device *pdev)