target/linux/brcm2708/patches-4.4/0289-drm-vc4-Bring-HDMI-up-from-power-off-if-necessary.patch

   1 From e25771aa6a4b2b701f3280956d97de4682c54231 Mon Sep 17 00:00:00 2001
   2 From: Eric Anholt <eric@anholt.net>
   3 Date: Fri, 12 Feb 2016 14:15:14 -0800
   4 Subject: [PATCH 289/304] drm/vc4: Bring HDMI up from power off if necessary.
   5
   6 If the firmware hadn't brought up HDMI for us, we need to do its
   7 power-on reset sequence (reset HD and and clear its STANDBY bits,
   8 reset HDMI, and leave the PHY disabled).
   9
  10 Signed-off-by: Eric Anholt <eric@anholt.net>
  11 (cherry picked from commit 851479ad5927b7b1aa141ca9dedb897a7bce2b1d)
  12 ---
  13  drivers/gpu/drm/vc4/vc4_hdmi.c | 29 ++++++++++++++++++++++++++++-
  14  drivers/gpu/drm/vc4/vc4_regs.h |  2 ++
  15  2 files changed, 30 insertions(+), 1 deletion(-)
  16
  17 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  18 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  19 @@ -497,6 +497,16 @@ static int vc4_hdmi_bind(struct device *
  20                 goto err_put_i2c;
  21         }
  22
  23 +       /* This is the rate that is set by the firmware.  The number
  24 +        * needs to be a bit higher than the pixel clock rate
  25 +        * (generally 148.5Mhz).
  26 +        */
  27 +       ret = clk_set_rate(hdmi->hsm_clock, 163682864);
  28 +       if (ret) {
  29 +               DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
  30 +               goto err_unprepare_pix;
  31 +       }
  32 +
  33         ret = clk_prepare_enable(hdmi->hsm_clock);
  34         if (ret) {
  35                 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
  36 @@ -518,7 +528,24 @@ static int vc4_hdmi_bind(struct device *
  37         vc4->hdmi = hdmi;
  38
  39         /* HDMI core must be enabled. */
  40 -       WARN_ON_ONCE((HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE) == 0);
  41 +       if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
  42 +               HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
  43 +               udelay(1);
  44 +               HD_WRITE(VC4_HD_M_CTL, 0);
  45 +
  46 +               HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
  47 +
  48 +               HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
  49 +                          VC4_HDMI_SW_RESET_HDMI |
  50 +                          VC4_HDMI_SW_RESET_FORMAT_DETECT);
  51 +
  52 +               HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
  53 +
  54 +               /* PHY should be in reset, like
  55 +                * vc4_hdmi_encoder_disable() does.
  56 +                */
  57 +               HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
  58 +       }
  59
  60         drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
  61                          DRM_MODE_ENCODER_TMDS);
  62 --- a/drivers/gpu/drm/vc4/vc4_regs.h
  63 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
  64 @@ -456,6 +456,8 @@
  65  #define VC4_HDMI_TX_PHY_RESET_CTL              0x2c0
  66
  67  #define VC4_HD_M_CTL                           0x00c
  68 +# define VC4_HD_M_REGISTER_FILE_STANDBY                (3 << 6)
  69 +# define VC4_HD_M_RAM_STANDBY                  (3 << 4)
  70  # define VC4_HD_M_SW_RST                       BIT(2)
  71  # define VC4_HD_M_ENABLE                       BIT(0)
  72