target/linux/brcm2708/patches-4.4/0392-Revert-dmaengine-bcm2835-Add-slave-dma-support.patch

   1 From b80a19b329a3fcbb74490a4b8d86055ee7d40c13 Mon Sep 17 00:00:00 2001
   2 From: Martin Sperl <kernel@martin.sperl.org>
   3 Date: Fri, 22 Apr 2016 17:17:37 +0000
   4 Subject: [PATCH] Revert "dmaengine: bcm2835: Add slave dma support"
   5
   6 This reverts commit 8a349301238aabb40c9da5ca8c8492b6b8d146f6.
   7 ---
   8  drivers/dma/bcm2835-dma.c | 206 ++++------------------------------------------
   9  1 file changed, 14 insertions(+), 192 deletions(-)
  10
  11 --- a/drivers/dma/bcm2835-dma.c
  12 +++ b/drivers/dma/bcm2835-dma.c
  13 @@ -1,10 +1,11 @@
  14  /*
  15   * BCM2835 DMA engine support
  16   *
  17 + * This driver only supports cyclic DMA transfers
  18 + * as needed for the I2S module.
  19 + *
  20   * Author:      Florian Meier <florian.meier@koalo.de>
  21   *              Copyright 2013
  22 - *              Gellert Weisz <gellert@raspberrypi.org>
  23 - *              Copyright 2013-2014
  24   *
  25   * Based on
  26   *     OMAP DMAengine support by Russell King
  27 @@ -94,8 +95,6 @@ struct bcm2835_desc {
  28         size_t size;
  29  };
  30
  31 -#define BCM2835_DMA_WAIT_CYCLES        0  /* Slow down DMA transfers: 0-31 */
  32 -
  33  #define BCM2835_DMA_CS         0x00
  34  #define BCM2835_DMA_ADDR       0x04
  35  #define BCM2835_DMA_SOURCE_AD  0x0c
  36 @@ -112,16 +111,12 @@ struct bcm2835_desc {
  37  #define BCM2835_DMA_RESET      BIT(31) /* WO, self clearing */
  38
  39  #define BCM2835_DMA_INT_EN     BIT(0)
  40 -#define BCM2835_DMA_WAIT_RESP  BIT(3)
  41  #define BCM2835_DMA_D_INC      BIT(4)
  42 -#define BCM2835_DMA_D_WIDTH    BIT(5)
  43  #define BCM2835_DMA_D_DREQ     BIT(6)
  44  #define BCM2835_DMA_S_INC      BIT(8)
  45 -#define BCM2835_DMA_S_WIDTH    BIT(9)
  46  #define BCM2835_DMA_S_DREQ     BIT(10)
  47
  48  #define BCM2835_DMA_PER_MAP(x) ((x) << 16)
  49 -#define BCM2835_DMA_WAITS(x)   (((x) & 0x1f) << 21)
  50
  51  #define BCM2835_DMA_DATA_TYPE_S8       1
  52  #define BCM2835_DMA_DATA_TYPE_S16      2
  53 @@ -135,14 +130,6 @@ struct bcm2835_desc {
  54  #define BCM2835_DMA_CHAN(n)    ((n) << 8) /* Base address */
  55  #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
  56
  57 -#define MAX_NORMAL_TRANSFER    SZ_1G
  58 -/*
  59 - * Max length on a Lite channel is 65535 bytes.
  60 - * DMA handles byte-enables on SDRAM reads and writes even on 128-bit accesses,
  61 - * but byte-enables don't exist on peripheral addresses, so align to 32-bit.
  62 - */
  63 -#define MAX_LITE_TRANSFER      (SZ_64K - 4)
  64 -
  65  static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
  66  {
  67         return container_of(d, struct bcm2835_dmadev, ddev);
  68 @@ -239,19 +226,13 @@ static irqreturn_t bcm2835_dma_callback(
  69         d = c->desc;
  70
  71         if (d) {
  72 -               if (c->cyclic) {
  73 -                       vchan_cyclic_callback(&d->vd);
  74 -
  75 -                       /* Keep the DMA engine running */
  76 -                       writel(BCM2835_DMA_ACTIVE,
  77 -                              c->chan_base + BCM2835_DMA_CS);
  78 -
  79 -               } else {
  80 -                       vchan_cookie_complete(&c->desc->vd);
  81 -                       bcm2835_dma_start_desc(c);
  82 -               }
  83 +               /* TODO Only works for cyclic DMA */
  84 +               vchan_cyclic_callback(&d->vd);
  85         }
  86
  87 +       /* Keep the DMA engine running */
  88 +       writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
  89 +
  90         spin_unlock_irqrestore(&c->vc.lock, flags);
  91
  92         return IRQ_HANDLED;
  93 @@ -358,6 +339,8 @@ static void bcm2835_dma_issue_pending(st
  94         struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
  95         unsigned long flags;
  96
  97 +       c->cyclic = true; /* Nothing else is implemented */
  98 +
  99         spin_lock_irqsave(&c->vc.lock, flags);
 100         if (vchan_issue_pending(&c->vc) && !c->desc)
 101                 bcm2835_dma_start_desc(c);
 102 @@ -375,7 +358,7 @@ static struct dma_async_tx_descriptor *b
 103         struct bcm2835_desc *d;
 104         dma_addr_t dev_addr;
 105         unsigned int es, sync_type;
 106 -       unsigned int frame, max_size;
 107 +       unsigned int frame;
 108         int i;
 109
 110         /* Grab configuration */
 111 @@ -410,12 +393,7 @@ static struct dma_async_tx_descriptor *b
 112
 113         d->c = c;
 114         d->dir = direction;
 115 -       if (c->ch >= 8) /* LITE channel */
 116 -               max_size = MAX_LITE_TRANSFER;
 117 -       else
 118 -               max_size = MAX_NORMAL_TRANSFER;
 119 -       period_len = min(period_len, max_size);
 120 -       d->frames = (buf_len - 1) / (period_len + 1);
 121 +       d->frames = buf_len / period_len;
 122
 123         d->cb_list = kcalloc(d->frames, sizeof(*d->cb_list), GFP_KERNEL);
 124         if (!d->cb_list) {
 125 @@ -463,171 +441,17 @@ static struct dma_async_tx_descriptor *b
 126                                 BCM2835_DMA_PER_MAP(c->dreq);
 127
 128                 /* Length of a frame */
 129 -               if (frame != d->frames - 1)
 130 -                       control_block->length = period_len;
 131 -               else
 132 -                       control_block->length = buf_len - (d->frames - 1) *
 133 -                                               period_len;
 134 +               control_block->length = period_len;
 135                 d->size += control_block->length;
 136
 137                 /*
 138                  * Next block is the next frame.
 139 -                * This function is called on cyclic DMA transfers.
 140 +                * This DMA engine driver currently only supports cyclic DMA.
 141                  * Therefore, wrap around at number of frames.
 142                  */
 143                 control_block->next = d->cb_list[((frame + 1) % d->frames)].paddr;
 144         }
 145
 146 -       c->cyclic = true;
 147 -
 148 -       return vchan_tx_prep(&c->vc, &d->vd, flags);
 149 -}
 150 -
 151 -static struct dma_async_tx_descriptor *
 152 -bcm2835_dma_prep_slave_sg(struct dma_chan *chan,
 153 -                         struct scatterlist *sgl,
 154 -                         unsigned int sg_len,
 155 -                         enum dma_transfer_direction direction,
 156 -                         unsigned long flags, void *context)
 157 -{
 158 -       struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
 159 -       enum dma_slave_buswidth dev_width;
 160 -       struct bcm2835_desc *d;
 161 -       dma_addr_t dev_addr;
 162 -       struct scatterlist *sgent;
 163 -       unsigned int i, sync_type, split_cnt, max_size;
 164 -
 165 -       if (!is_slave_direction(direction)) {
 166 -               dev_err(chan->device->dev, "direction not supported\n");
 167 -               return NULL;
 168 -       }
 169 -
 170 -       if (direction == DMA_DEV_TO_MEM) {
 171 -               dev_addr = c->cfg.src_addr;
 172 -               dev_width = c->cfg.src_addr_width;
 173 -               sync_type = BCM2835_DMA_S_DREQ;
 174 -       } else {
 175 -               dev_addr = c->cfg.dst_addr;
 176 -               dev_width = c->cfg.dst_addr_width;
 177 -               sync_type = BCM2835_DMA_D_DREQ;
 178 -       }
 179 -
 180 -       /* Bus width translates to the element size (ES) */
 181 -       switch (dev_width) {
 182 -       case DMA_SLAVE_BUSWIDTH_4_BYTES:
 183 -               break;
 184 -       default:
 185 -               dev_err(chan->device->dev, "buswidth not supported: %i\n",
 186 -                       dev_width);
 187 -               return NULL;
 188 -       }
 189 -
 190 -       /* Allocate and setup the descriptor. */
 191 -       d = kzalloc(sizeof(*d), GFP_NOWAIT);
 192 -       if (!d)
 193 -               return NULL;
 194 -
 195 -       d->dir = direction;
 196 -
 197 -       if (c->ch >= 8) /* LITE channel */
 198 -               max_size = MAX_LITE_TRANSFER;
 199 -       else
 200 -               max_size = MAX_NORMAL_TRANSFER;
 201 -
 202 -       /*
 203 -        * Store the length of the SG list in d->frames
 204 -        * taking care to account for splitting up transfers
 205 -        * too large for a LITE channel
 206 -        */
 207 -       d->frames = 0;
 208 -       for_each_sg(sgl, sgent, sg_len, i) {
 209 -               unsigned int len = sg_dma_len(sgent);
 210 -
 211 -               d->frames += len / max_size + 1;
 212 -       }
 213 -
 214 -       /* Allocate memory for control blocks */
 215 -       d->control_block_size = d->frames * sizeof(struct bcm2835_dma_cb);
 216 -       d->control_block_base = dma_zalloc_coherent(chan->device->dev,
 217 -                       d->control_block_size, &d->control_block_base_phys,
 218 -                       GFP_NOWAIT);
 219 -       if (!d->control_block_base) {
 220 -               kfree(d);
 221 -               return NULL;
 222 -       }
 223 -
 224 -       /*
 225 -        * Iterate over all SG entries, create a control block
 226 -        * for each frame and link them together.
 227 -        * Count the number of times an SG entry had to be split
 228 -        * as a result of using a LITE channel
 229 -        */
 230 -       split_cnt = 0;
 231 -
 232 -       for_each_sg(sgl, sgent, sg_len, i) {
 233 -               unsigned int j;
 234 -               dma_addr_t addr = sg_dma_address(sgent);
 235 -               unsigned int len = sg_dma_len(sgent);
 236 -
 237 -               for (j = 0; j < len; j += max_size) {
 238 -                       struct bcm2835_dma_cb *control_block =
 239 -                               &d->control_block_base[i + split_cnt];
 240 -
 241 -                       /* Setup addresses */
 242 -                       if (d->dir == DMA_DEV_TO_MEM) {
 243 -                               control_block->info = BCM2835_DMA_D_INC |
 244 -                                                     BCM2835_DMA_D_WIDTH |
 245 -                                                     BCM2835_DMA_S_DREQ;
 246 -                               control_block->src = dev_addr;
 247 -                               control_block->dst = addr + (dma_addr_t)j;
 248 -                       } else {
 249 -                               control_block->info = BCM2835_DMA_S_INC |
 250 -                                                     BCM2835_DMA_S_WIDTH |
 251 -                                                     BCM2835_DMA_D_DREQ;
 252 -                               control_block->src = addr + (dma_addr_t)j;
 253 -                               control_block->dst = dev_addr;
 254 -                       }
 255 -
 256 -                       /* Common part */
 257 -                       control_block->info |=
 258 -                               BCM2835_DMA_WAITS(BCM2835_DMA_WAIT_CYCLES);
 259 -                       control_block->info |= BCM2835_DMA_WAIT_RESP;
 260 -
 261 -                       /* Enable */
 262 -                       if (i == sg_len - 1 && len - j <= max_size)
 263 -                               control_block->info |= BCM2835_DMA_INT_EN;
 264 -
 265 -                       /* Setup synchronization */
 266 -                       if (sync_type)
 267 -                               control_block->info |= sync_type;
 268 -
 269 -                       /* Setup DREQ channel */
 270 -                       if (c->dreq)
 271 -                               control_block->info |=
 272 -                                       BCM2835_DMA_PER_MAP(c->dreq);
 273 -
 274 -                       /* Length of a frame */
 275 -                       control_block->length = min(len - j, max_size);
 276 -                       d->size += control_block->length;
 277 -
 278 -                       if (i < sg_len - 1 || len - j > max_size) {
 279 -                               /* Next block is the next frame. */
 280 -                               control_block->next =
 281 -                                       d->control_block_base_phys +
 282 -                                       sizeof(struct bcm2835_dma_cb) *
 283 -                                       (i + split_cnt + 1);
 284 -                       } else {
 285 -                               /* Next block is empty. */
 286 -                               control_block->next = 0;
 287 -                       }
 288 -
 289 -                       if (len - j > max_size)
 290 -                               split_cnt++;
 291 -               }
 292 -       }
 293 -
 294 -       c->cyclic = false;
 295 -
 296         return vchan_tx_prep(&c->vc, &d->vd, flags);
 297  error_cb:
 298         i--;
 299 @@ -796,7 +620,6 @@ static int bcm2835_dma_probe(struct plat
 300         od->ddev.device_tx_status = bcm2835_dma_tx_status;
 301         od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
 302         od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
 303 -       od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
 304         od->ddev.device_config = bcm2835_dma_slave_config;
 305         od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
 306         od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
 307 @@ -886,5 +709,4 @@ module_platform_driver(bcm2835_dma_drive
 308  MODULE_ALIAS("platform:bcm2835-dma");
 309  MODULE_DESCRIPTION("BCM2835 DMA engine driver");
 310  MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
 311 -MODULE_AUTHOR("Gellert Weisz <gellert@raspberrypi.org>");
 312  MODULE_LICENSE("GPL v2");