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brcm2708: update linux 4.4 patches to latest version
[openwrt/staging/dedeckeh.git] / target / linux / brcm2708 / patches-4.4 / 0443-drm-vc4-Add-DSI1-driver.patch
1 From 7e409fcf8006642edc6f817b6832f27b66debc44 Mon Sep 17 00:00:00 2001
2 From: Eric Anholt <eric@anholt.net>
3 Date: Wed, 10 Feb 2016 11:42:32 -0800
4 Subject: [PATCH] drm/vc4: Add DSI1 driver
5
6 The DSI0 and DSI1 blocks on the 2835 are different but very similar
7 hardware blocks. Some registers move around, and the featureset is
8 slightly different, but they're clearly related. This doesn't enable
9 DSI0, but some of the infrastructure is present.
10
11 Also, this driver doesn't initialize the DSI successfully from
12 poweron, so we currently require that the Raspberry Pi firmware enable
13 it at boot time. From there, we just keep the same settings forever,
14 and when poweroff is requested we just scan out black instead.
15
16 Signed-off-by: Eric Anholt <eric@anholt.net>
17 ---
18 drivers/gpu/drm/vc4/Kconfig | 2 +
19 drivers/gpu/drm/vc4/Makefile | 1 +
20 drivers/gpu/drm/vc4/vc4_crtc.c | 41 +-
21 drivers/gpu/drm/vc4/vc4_debugfs.c | 2 +
22 drivers/gpu/drm/vc4/vc4_drv.c | 1 +
23 drivers/gpu/drm/vc4/vc4_drv.h | 8 +
24 drivers/gpu/drm/vc4/vc4_dsi.c | 1737 +++++++++++++++++++++++++++++++++++++
25 7 files changed, 1780 insertions(+), 12 deletions(-)
26 create mode 100644 drivers/gpu/drm/vc4/vc4_dsi.c
27
28 --- a/drivers/gpu/drm/vc4/Kconfig
29 +++ b/drivers/gpu/drm/vc4/Kconfig
30 @@ -6,6 +6,8 @@ config DRM_VC4
31 select DRM_KMS_CMA_HELPER
32 select DRM_GEM_CMA_HELPER
33 select DRM_PANEL
34 + select DRM_MIPI_DSI
35 + select CLKSRC_OF
36 help
37 Choose this option if you have a system that has a Broadcom
38 VC4 GPU, such as the Raspberry Pi or other BCM2708/BCM2835.
39 --- a/drivers/gpu/drm/vc4/Makefile
40 +++ b/drivers/gpu/drm/vc4/Makefile
41 @@ -8,6 +8,7 @@ vc4-y := \
42 vc4_crtc.o \
43 vc4_drv.o \
44 vc4_dpi.o \
45 + vc4_dsi.o \
46 vc4_kms.o \
47 vc4_gem.o \
48 vc4_hdmi.o \
49 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
50 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
51 @@ -231,7 +231,7 @@ static void vc4_crtc_mode_set_nofb(struc
52 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
53 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
54 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
55 - bool debug_dump_regs = true;
56 + bool debug_dump_regs = false;
57
58 if (debug_dump_regs) {
59 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
60 @@ -327,6 +327,19 @@ static void vc4_crtc_disable(struct drm_
61 int ret;
62 require_hvs_enabled(dev);
63
64 + if (VC4_DSI_USE_FIRMWARE_SETUP &&
65 + (CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_DSI)) {
66 + /* Skip disabling the PV/HVS for the channel if it was
67 + * connected to the DSI panel and we're using the
68 + * firmware setup. Instead, just set it to stuff
69 + * black in the composite output buffer.
70 + */
71 + HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
72 + HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) |
73 + SCALER_DISPBKGND_FILL);
74 + return;
75 + }
76 +
77 CRTC_WRITE(PV_V_CONTROL,
78 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
79 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
80 @@ -396,17 +409,19 @@ static int vc4_crtc_atomic_check(struct
81 if (drm_atomic_connectors_for_crtc(state->state, crtc) > 1)
82 return -EINVAL;
83
84 - drm_atomic_crtc_state_for_each_plane(plane, state) {
85 - struct drm_plane_state *plane_state =
86 - state->state->plane_states[drm_plane_index(plane)];
87 -
88 - /* plane might not have changed, in which case take
89 - * current state:
90 - */
91 - if (!plane_state)
92 - plane_state = plane->state;
93 + if (state->active) {
94 + drm_atomic_crtc_state_for_each_plane(plane, state) {
95 + struct drm_plane_state *plane_state =
96 + state->state->plane_states[drm_plane_index(plane)];
97 +
98 + /* plane might not have changed, in which case take
99 + * current state:
100 + */
101 + if (!plane_state)
102 + plane_state = plane->state;
103
104 - dlist_count += vc4_plane_dlist_size(plane_state);
105 + dlist_count += vc4_plane_dlist_size(plane_state);
106 + }
107 }
108
109 dlist_count++; /* Account for SCALER_CTL0_END. */
110 @@ -439,8 +454,10 @@ static void vc4_crtc_atomic_flush(struct
111 }
112
113 /* Copy all the active planes' dlist contents to the hardware dlist. */
114 - drm_atomic_crtc_for_each_plane(plane, crtc) {
115 - dlist_next += vc4_plane_write_dlist(plane, dlist_next);
116 + if (crtc->state->active) {
117 + drm_atomic_crtc_for_each_plane(plane, crtc) {
118 + dlist_next += vc4_plane_write_dlist(plane, dlist_next);
119 + }
120 }
121
122 writel(SCALER_CTL0_END, dlist_next);
123 --- a/drivers/gpu/drm/vc4/vc4_debugfs.c
124 +++ b/drivers/gpu/drm/vc4/vc4_debugfs.c
125 @@ -19,6 +19,8 @@ static const struct drm_info_list vc4_de
126 {"bo_stats", vc4_bo_stats_debugfs, 0},
127 {"dpi_regs", vc4_dpi_debugfs_regs, 0},
128 {"gem_exec", vc4_gem_exec_debugfs, 0},
129 + {"dsi0_regs", vc4_dsi_debugfs_regs, 0, (void *)(uintptr_t)0},
130 + {"dsi1_regs", vc4_dsi_debugfs_regs, 0, (void *)(uintptr_t)1},
131 {"hdmi_regs", vc4_hdmi_debugfs_regs, 0},
132 {"hvs_regs", vc4_hvs_debugfs_regs, 0},
133 {"crtc0_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)0},
134 --- a/drivers/gpu/drm/vc4/vc4_drv.c
135 +++ b/drivers/gpu/drm/vc4/vc4_drv.c
136 @@ -294,6 +294,7 @@ static const struct component_master_ops
137 static struct platform_driver *const component_drivers[] = {
138 &vc4_hdmi_driver,
139 &vc4_dpi_driver,
140 + &vc4_dsi_driver,
141 &vc4_crtc_driver,
142 &vc4_hvs_driver,
143 &vc4_v3d_driver,
144 --- a/drivers/gpu/drm/vc4/vc4_drv.h
145 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
146 @@ -19,6 +19,8 @@ struct vc4_dev {
147 struct vc4_crtc *crtc[3];
148 struct vc4_v3d *v3d;
149 struct vc4_dpi *dpi;
150 + struct vc4_dsi *dsi0;
151 + struct vc4_dsi *dsi1;
152
153 struct drm_fbdev_cma *fbdev;
154 struct rpi_firmware *firmware;
155 @@ -192,6 +194,8 @@ enum vc4_encoder_type {
156 VC4_ENCODER_TYPE_DPI,
157 };
158
159 +#define VC4_DSI_USE_FIRMWARE_SETUP true
160 +
161 struct vc4_encoder {
162 struct drm_encoder base;
163 enum vc4_encoder_type type;
164 @@ -429,6 +433,10 @@ void vc4_dump_regs32(const struct debugf
165 extern struct platform_driver vc4_dpi_driver;
166 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused);
167
168 +/* vc4_dsi.c */
169 +extern struct platform_driver vc4_dsi_driver;
170 +int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused);
171 +
172 /* vc4_gem.c */
173 void vc4_gem_init(struct drm_device *dev);
174 void vc4_gem_destroy(struct drm_device *dev);
175 --- /dev/null
176 +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
177 @@ -0,0 +1,1737 @@
178 + /*
179 + * Copyright (C) 2016 Broadcom Limited
180 + *
181 + * This program is free software; you can redistribute it and/or modify it
182 + * under the terms of the GNU General Public License version 2 as published by
183 + * the Free Software Foundation.
184 + *
185 + * This program is distributed in the hope that it will be useful, but WITHOUT
186 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
187 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
188 + * more details.
189 + *
190 + * You should have received a copy of the GNU General Public License along with
191 + * this program. If not, see <http://www.gnu.org/licenses/>.
192 + */
193 +
194 +/**
195 + * DOC: VC4 DSI0 module
196 + */
197 +
198 +#include "drm_atomic_helper.h"
199 +#include "drm_crtc_helper.h"
200 +#include "drm_edid.h"
201 +#include "drm_mipi_dsi.h"
202 +#include "drm_panel.h"
203 +#include "linux/clk.h"
204 +#include "linux/clk-provider.h"
205 +#include "linux/completion.h"
206 +#include "linux/component.h"
207 +#include "linux/debugfs.h"
208 +#include "linux/dmaengine.h"
209 +#include "linux/i2c.h"
210 +#include "linux/of_address.h"
211 +#include "linux/of_gpio.h"
212 +#include "linux/of_platform.h"
213 +#include "vc4_drv.h"
214 +#include "vc4_regs.h"
215 +
216 +#define DSI_CMD_FIFO_DEPTH 16
217 +#define DSI_PIX_FIFO_DEPTH 256
218 +#define DSI_PIX_FIFO_WIDTH 4
219 +
220 +#define DSI0_CTRL 0x00
221 +
222 +/* Command packet control. */
223 +#define DSI0_TXPKT1C 0x04 /* AKA PKTC */
224 +#define DSI1_TXPKT1C 0x04
225 +# define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24)
226 +# define DSI_TXPKT1C_TRIG_CMD_SHIFT 24
227 +# define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10)
228 +# define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10
229 +
230 +# define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8)
231 +# define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8
232 +/* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */
233 +# define DSI_TXPKT1C_DISPLAY_NO_SHORT 0
234 +/* Primary display where cmdfifo provides part of the payload and
235 + * pixelvalve the rest.
236 + */
237 +# define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1
238 +/* Secondary display where cmdfifo provides part of the payload and
239 + * pixfifo the rest.
240 + */
241 +# define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2
242 +
243 +# define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6)
244 +# define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6
245 +# define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4)
246 +# define DSI_TXPKT1C_CMD_CTRL_SHIFT 4
247 +/* Command only. Uses TXPKT1H and DISPLAY_NO */
248 +# define DSI_TXPKT1C_CMD_CTRL_TX 0
249 +/* Command with BTA for either ack or read data. */
250 +# define DSI_TXPKT1C_CMD_CTRL_RX 1
251 +/* Trigger according to TRIG_CMD */
252 +# define DSI_TXPKT1C_CMD_CTRL_TRIG 2
253 +/* BTA alone for getting error status after a command, or a TE trigger
254 + * without a previous command.
255 + */
256 +# define DSI_TXPKT1C_CMD_CTRL_BTA 3
257 +
258 +# define DSI_TXPKT1C_CMD_MODE_LP BIT(3)
259 +# define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2)
260 +# define DSI_TXPKT1C_CMD_TE_EN BIT(1)
261 +# define DSI_TXPKT1C_CMD_EN BIT(0)
262 +
263 +/* Command packet header. */
264 +#define DSI0_TXPKT1H 0x08 /* AKA PKTH */
265 +#define DSI1_TXPKT1H 0x08
266 +# define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24)
267 +# define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24
268 +# define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
269 +# define DSI_TXPKT1H_BC_PARAM_SHIFT 8
270 +# define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0)
271 +# define DSI_TXPKT1H_BC_DT_SHIFT 0
272 +
273 +#define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */
274 +#define DSI1_RXPKT1H 0x14
275 +# define DSI_RXPKT1H_CRC_ERR BIT(31)
276 +# define DSI_RXPKT1H_DET_ERR BIT(30)
277 +# define DSI_RXPKT1H_ECC_ERR BIT(29)
278 +# define DSI_RXPKT1H_COR_ERR BIT(28)
279 +# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
280 +# define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24)
281 +/* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */
282 +# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
283 +# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
284 +/* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */
285 +# define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16)
286 +# define DSI_RXPKT1H_SHORT_1_SHIFT 16
287 +# define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8)
288 +# define DSI_RXPKT1H_SHORT_0_SHIFT 8
289 +# define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0)
290 +# define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0
291 +
292 +#define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */
293 +#define DSI1_RXPKT2H 0x18
294 +# define DSI_RXPKT1H_DET_ERR BIT(30)
295 +# define DSI_RXPKT1H_ECC_ERR BIT(29)
296 +# define DSI_RXPKT1H_COR_ERR BIT(28)
297 +# define DSI_RXPKT1H_INCOMP_PKT BIT(25)
298 +# define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8)
299 +# define DSI_RXPKT1H_BC_PARAM_SHIFT 8
300 +# define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0)
301 +# define DSI_RXPKT1H_DT_SHIFT 0
302 +
303 +#define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */
304 +#define DSI1_TXPKT_CMD_FIFO 0x1c
305 +
306 +#define DSI0_DISP0_CTRL 0x18
307 +# define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13)
308 +# define DSI_DISP0_PIX_CLK_DIV_SHIFT 13
309 +# define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11)
310 +# define DSI_DISP0_LP_STOP_CTRL_SHIFT 11
311 +# define DSI_DISP0_LP_STOP_DISABLE 0
312 +# define DSI_DISP0_LP_STOP_PERLINE 1
313 +# define DSI_DISP0_LP_STOP_PERFRAME 2
314 +
315 +/* Transmit RGB pixels and null packets only during HACTIVE, instead
316 + * of going to LP-STOP.
317 + */
318 +# define DSI_DISP_HACTIVE_NULL BIT(10)
319 +/* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */
320 +# define DSI_DISP_VBLP_CTRL BIT(9)
321 +/* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */
322 +# define DSI_DISP_HFP_CTRL BIT(8)
323 +/* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */
324 +# define DSI_DISP_HBP_CTRL BIT(7)
325 +# define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5)
326 +# define DSI_DISP0_CHANNEL_SHIFT 5
327 +/* Enables and end events for HSYNC/VSYNC, not just start events. */
328 +# define DSI_DISP0_ST_END BIT(4)
329 +# define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2)
330 +# define DSI_DISP0_PFORMAT_SHIFT 2
331 +# define DSI_PFORMAT_RGB565 0
332 +# define DSI_PFORMAT_RGB666_PACKED 1
333 +# define DSI_PFORMAT_RGB666 2
334 +# define DSI_PFORMAT_RGB888 3
335 +/* Default is VIDEO mode. */
336 +# define DSI_DISP0_COMMAND_MODE BIT(1)
337 +# define DSI_DISP0_ENABLE BIT(0)
338 +
339 +#define DSI0_DISP1_CTRL 0x1c
340 +#define DSI1_DISP1_CTRL 0x2c
341 +/* Format of the data written to TXPKT_PIX_FIFO. */
342 +# define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1)
343 +# define DSI_DISP1_PFORMAT_SHIFT 1
344 +# define DSI_DISP1_PFORMAT_16BIT 0
345 +# define DSI_DISP1_PFORMAT_24BIT 1
346 +# define DSI_DISP1_PFORMAT_32BIT_LE 2
347 +# define DSI_DISP1_PFORMAT_32BIT_BE 3
348 +
349 +/* DISP1 is always command mode. */
350 +# define DSI_DISP1_ENABLE BIT(0)
351 +
352 +#define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */
353 +
354 +#define DSI0_INT_STAT 0x24
355 +#define DSI0_INT_EN 0x28
356 +# define DSI1_INT_PHY_D3_ULPS BIT(30)
357 +# define DSI1_INT_PHY_D3_STOP BIT(29)
358 +# define DSI1_INT_PHY_D2_ULPS BIT(28)
359 +# define DSI1_INT_PHY_D2_STOP BIT(27)
360 +# define DSI1_INT_PHY_D1_ULPS BIT(26)
361 +# define DSI1_INT_PHY_D1_STOP BIT(25)
362 +# define DSI1_INT_PHY_D0_ULPS BIT(24)
363 +# define DSI1_INT_PHY_D0_STOP BIT(23)
364 +# define DSI1_INT_FIFO_ERR BIT(22)
365 +# define DSI1_INT_PHY_DIR_RTF BIT(21)
366 +# define DSI1_INT_PHY_RXLPDT BIT(20)
367 +# define DSI1_INT_PHY_RXTRIG BIT(19)
368 +# define DSI1_INT_PHY_D0_LPDT BIT(18)
369 +# define DSI1_INT_PHY_DIR_FTR BIT(17)
370 +
371 +/* Signaled when the clock lane enters the given state. */
372 +# define DSI1_INT_PHY_CLOCK_ULPS BIT(16)
373 +# define DSI1_INT_PHY_CLOCK_HS BIT(15)
374 +# define DSI1_INT_PHY_CLOCK_STOP BIT(14)
375 +
376 +/* Signaled on timeouts */
377 +# define DSI1_INT_PR_TO BIT(13)
378 +# define DSI1_INT_TA_TO BIT(12)
379 +# define DSI1_INT_LPRX_TO BIT(11)
380 +# define DSI1_INT_HSTX_TO BIT(10)
381 +
382 +/* Contention on a line when trying to drive the line low */
383 +# define DSI1_INT_ERR_CONT_LP1 BIT(9)
384 +# define DSI1_INT_ERR_CONT_LP0 BIT(8)
385 +
386 +/* Control error: incorrect line state sequence on data lane 0. */
387 +# define DSI1_INT_ERR_CONTROL BIT(7)
388 +/* LPDT synchronization error (bits received not a multiple of 8. */
389 +
390 +# define DSI1_INT_ERR_SYNC_ESC BIT(6)
391 +/* Signaled after receiving an error packet from the display in
392 + * response to a read.
393 + */
394 +# define DSI1_INT_RXPKT2 BIT(5)
395 +/* Signaled after receiving a packet. The header and optional short
396 + * response will be in RXPKT1H, and a long response will be in the
397 + * RXPKT_FIFO.
398 + */
399 +# define DSI1_INT_RXPKT1 BIT(4)
400 +# define DSI1_INT_TXPKT2_DONE BIT(3)
401 +# define DSI1_INT_TXPKT2_END BIT(2)
402 +/* Signaled after all repeats of TXPKT1 are transferred. */
403 +# define DSI1_INT_TXPKT1_DONE BIT(1)
404 +/* Signaled after each TXPKT1 repeat is scheduled. */
405 +# define DSI1_INT_TXPKT1_END BIT(0)
406 +
407 +#define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \
408 + DSI1_INT_ERR_CONTROL | \
409 + DSI1_INT_ERR_CONT_LP0 | \
410 + DSI1_INT_ERR_CONT_LP1 | \
411 + DSI1_INT_HSTX_TO | \
412 + DSI1_INT_LPRX_TO | \
413 + DSI1_INT_TA_TO | \
414 + DSI1_INT_PR_TO)
415 +
416 +#define DSI0_STAT 0x2c
417 +#define DSI0_HSTX_TO_CNT 0x30
418 +#define DSI0_LPRX_TO_CNT 0x34
419 +#define DSI0_TA_TO_CNT 0x38
420 +#define DSI0_PR_TO_CNT 0x3c
421 +#define DSI0_PHYC 0x40
422 +# define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20)
423 +# define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20
424 +# define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18)
425 +# define DSI1_PHYC_CLANE_ULPS BIT(17)
426 +# define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12)
427 +# define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12
428 +# define DSI1_PHYC_CLANE_ENABLE BIT(16)
429 +# define DSI_PHYC_DLANE3_ULPS BIT(13)
430 +# define DSI_PHYC_DLANE3_ENABLE BIT(12)
431 +# define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10)
432 +# define DSI0_PHYC_CLANE_ULPS BIT(9)
433 +# define DSI_PHYC_DLANE2_ULPS BIT(9)
434 +# define DSI0_PHYC_CLANE_ENABLE BIT(8)
435 +# define DSI_PHYC_DLANE2_ENABLE BIT(8)
436 +# define DSI_PHYC_DLANE1_ULPS BIT(5)
437 +# define DSI_PHYC_DLANE1_ENABLE BIT(4)
438 +# define DSI_PHYC_DLANE0_FORCE_STOP BIT(2)
439 +# define DSI_PHYC_DLANE0_ULPS BIT(1)
440 +# define DSI_PHYC_DLANE0_ENABLE BIT(0)
441 +
442 +#define DSI0_HS_CLT0 0x44
443 +#define DSI0_HS_CLT1 0x48
444 +#define DSI0_HS_CLT2 0x4c
445 +#define DSI0_HS_DLT3 0x50
446 +#define DSI0_HS_DLT4 0x54
447 +#define DSI0_HS_DLT5 0x58
448 +#define DSI0_HS_DLT6 0x5c
449 +#define DSI0_HS_DLT7 0x60
450 +
451 +#define DSI0_PHY_AFEC0 0x64
452 +# define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26)
453 +# define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25)
454 +# define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24)
455 +# define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29)
456 +# define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29
457 +# define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26)
458 +# define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26
459 +# define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23)
460 +# define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23
461 +# define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20)
462 +# define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20
463 +# define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17)
464 +# define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17
465 +# define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20)
466 +# define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20
467 +# define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16)
468 +# define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16
469 +# define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12)
470 +# define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12
471 +# define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16)
472 +# define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15)
473 +# define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14)
474 +# define DSI1_PHY_AFEC0_RESET BIT(13)
475 +# define DSI1_PHY_AFEC0_PD BIT(12)
476 +# define DSI0_PHY_AFEC0_RESET BIT(11)
477 +# define DSI1_PHY_AFEC0_PD_BG BIT(11)
478 +# define DSI0_PHY_AFEC0_PD BIT(10)
479 +# define DSI1_PHY_AFEC0_PD_DLANE3 BIT(10)
480 +# define DSI0_PHY_AFEC0_PD_BG BIT(9)
481 +# define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9)
482 +# define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8)
483 +# define DSI1_PHY_AFEC0_PD_DLANE1 BIT(8)
484 +# define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4)
485 +# define DSI_PHY_AFEC0_PTATADJ_SHIFT 4
486 +# define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0)
487 +# define DSI_PHY_AFEC0_CTATADJ_SHIFT 0
488 +
489 +#define DSI0_PHY_AFEC1 0x68
490 +# define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8)
491 +# define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8
492 +# define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4)
493 +# define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4
494 +# define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0)
495 +# define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0
496 +
497 +#define DSI0_TST_SEL 0x6c
498 +#define DSI0_TST_MON 0x70
499 +#define DSI0_ID 0x74
500 +# define DSI_ID_VALUE 0x00647369
501 +
502 +
503 +#define DSI1_CTRL 0x00
504 +# define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14)
505 +# define DSI_CTRL_HS_CLKC_SHIFT 14
506 +# define DSI_CTRL_HS_CLKC_BYTE 0
507 +# define DSI_CTRL_HS_CLKC_DDR2 1
508 +# define DSI_CTRL_HS_CLKC_DDR 2
509 +
510 +# define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13)
511 +# define DSI_CTRL_LPDT_EOT_DISABLE BIT(12)
512 +# define DSI_CTRL_HSDT_EOT_DISABLE BIT(11)
513 +# define DSI_CTRL_SOFT_RESET_CFG BIT(10)
514 +# define DSI_CTRL_CAL_BYTE BIT(9)
515 +# define DSI_CTRL_INV_BYTE BIT(8)
516 +# define DSI_CTRL_CLR_LDF BIT(7)
517 +# define DSI0_CTRL_CLR_PBCF BIT(6)
518 +# define DSI1_CTRL_CLR_RXF BIT(6)
519 +# define DSI0_CTRL_CLR_CPBCF BIT(5)
520 +# define DSI1_CTRL_CLR_PDF BIT(5)
521 +# define DSI0_CTRL_CLR_PDF BIT(4)
522 +# define DSI1_CTRL_CLR_CDF BIT(4)
523 +# define DSI0_CTRL_CLR_CDF BIT(3)
524 +# define DSI0_CTRL_CTRL2 BIT(2)
525 +# define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2)
526 +# define DSI0_CTRL_CTRL1 BIT(1)
527 +# define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1)
528 +# define DSI0_CTRL_CTRL0 BIT(0)
529 +# define DSI1_CTRL_EN BIT(0)
530 +# define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
531 + DSI0_CTRL_CLR_PBCF | \
532 + DSI0_CTRL_CLR_CPBCF | \
533 + DSI0_CTRL_CLR_PDF | \
534 + DSI0_CTRL_CLR_CDF)
535 +# define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \
536 + DSI1_CTRL_CLR_RXF | \
537 + DSI1_CTRL_CLR_PDF | \
538 + DSI1_CTRL_CLR_CDF)
539 +
540 +#define DSI1_TXPKT2C 0x0c
541 +#define DSI1_TXPKT2H 0x10
542 +#define DSI1_TXPKT_PIX_FIFO 0x20
543 +#define DSI1_RXPKT_FIFO 0x24
544 +#define DSI1_DISP0_CTRL 0x28
545 +#define DSI1_INT_STAT 0x30
546 +#define DSI1_INT_EN 0x34
547 +
548 +/* State reporting bits. These mostly behave like INT_STAT, where
549 + * writing a 1 clears the bit.
550 + */
551 +#define DSI1_STAT 0x38
552 +# define DSI1_STAT_PHY_D3_ULPS BIT(31)
553 +# define DSI1_STAT_PHY_D3_STOP BIT(30)
554 +# define DSI1_STAT_PHY_D2_ULPS BIT(29)
555 +# define DSI1_STAT_PHY_D2_STOP BIT(28)
556 +# define DSI1_STAT_PHY_D1_ULPS BIT(27)
557 +# define DSI1_STAT_PHY_D1_STOP BIT(26)
558 +# define DSI1_STAT_PHY_D0_ULPS BIT(25)
559 +# define DSI1_STAT_PHY_D0_STOP BIT(24)
560 +# define DSI1_STAT_FIFO_ERR BIT(23)
561 +# define DSI1_STAT_PHY_RXLPDT BIT(22)
562 +# define DSI1_STAT_PHY_RXTRIG BIT(21)
563 +# define DSI1_STAT_PHY_D0_LPDT BIT(20)
564 +/* Set when in forward direction */
565 +# define DSI1_STAT_PHY_DIR BIT(19)
566 +# define DSI1_STAT_PHY_CLOCK_ULPS BIT(18)
567 +# define DSI1_STAT_PHY_CLOCK_HS BIT(17)
568 +# define DSI1_STAT_PHY_CLOCK_STOP BIT(16)
569 +# define DSI1_STAT_PR_TO BIT(15)
570 +# define DSI1_STAT_TA_TO BIT(14)
571 +# define DSI1_STAT_LPRX_TO BIT(13)
572 +# define DSI1_STAT_HSTX_TO BIT(12)
573 +# define DSI1_STAT_ERR_CONT_LP1 BIT(11)
574 +# define DSI1_STAT_ERR_CONT_LP0 BIT(10)
575 +# define DSI1_STAT_ERR_CONTROL BIT(9)
576 +# define DSI1_STAT_ERR_SYNC_ESC BIT(8)
577 +# define DSI1_STAT_RXPKT2 BIT(7)
578 +# define DSI1_STAT_RXPKT1 BIT(6)
579 +# define DSI1_STAT_TXPKT2_BUSY BIT(5)
580 +# define DSI1_STAT_TXPKT2_DONE BIT(4)
581 +# define DSI1_STAT_TXPKT2_END BIT(3)
582 +# define DSI1_STAT_TXPKT1_BUSY BIT(2)
583 +# define DSI1_STAT_TXPKT1_DONE BIT(1)
584 +# define DSI1_STAT_TXPKT1_END BIT(0)
585 +
586 +#define DSI1_HSTX_TO_CNT 0x3c
587 +#define DSI1_LPRX_TO_CNT 0x40
588 +#define DSI1_TA_TO_CNT 0x44
589 +#define DSI1_PR_TO_CNT 0x48
590 +#define DSI1_PHYC 0x4c
591 +
592 +#define DSI1_HS_CLT0 0x50
593 +# define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18)
594 +# define DSI_HS_CLT0_CZERO_SHIFT 18
595 +# define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9)
596 +# define DSI_HS_CLT0_CPRE_SHIFT 9
597 +# define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0)
598 +# define DSI_HS_CLT0_CPREP_SHIFT 0
599 +
600 +#define DSI1_HS_CLT1 0x54
601 +# define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9)
602 +# define DSI_HS_CLT1_CTRAIL_SHIFT 9
603 +# define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0)
604 +# define DSI_HS_CLT1_CPOST_SHIFT 0
605 +
606 +#define DSI1_HS_CLT2 0x58
607 +# define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0)
608 +# define DSI_HS_CLT2_WUP_SHIFT 0
609 +
610 +#define DSI1_HS_DLT3 0x5c
611 +# define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18)
612 +# define DSI_HS_DLT3_EXIT_SHIFT 18
613 +# define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9)
614 +# define DSI_HS_DLT3_ZERO_SHIFT 9
615 +# define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0)
616 +# define DSI_HS_DLT3_PRE_SHIFT 0
617 +
618 +#define DSI1_HS_DLT4 0x60
619 +# define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18)
620 +# define DSI_HS_DLT4_ANLAT_SHIFT 18
621 +# define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9)
622 +# define DSI_HS_DLT4_TRAIL_SHIFT 9
623 +# define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0)
624 +# define DSI_HS_DLT4_LPX_SHIFT 0
625 +
626 +#define DSI1_HS_DLT5 0x64
627 +# define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0)
628 +# define DSI_HS_DLT5_INIT_SHIFT 0
629 +
630 +#define DSI1_HS_DLT6 0x68
631 +# define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24)
632 +# define DSI_HS_DLT6_TA_GET_SHIFT 24
633 +# define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16)
634 +# define DSI_HS_DLT6_TA_SURE_SHIFT 16
635 +# define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8)
636 +# define DSI_HS_DLT6_TA_GO_SHIFT 8
637 +# define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0)
638 +# define DSI_HS_DLT6_LP_LPX_SHIFT 0
639 +
640 +#define DSI1_HS_DLT7 0x6c
641 +# define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0)
642 +# define DSI_HS_DLT7_LP_WUP_SHIFT 0
643 +
644 +#define DSI1_PHY_AFEC0 0x70
645 +
646 +#define DSI1_PHY_AFEC1 0x74
647 +# define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16)
648 +# define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16
649 +# define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12)
650 +# define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12
651 +# define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8)
652 +# define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8
653 +# define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4)
654 +# define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4
655 +# define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0)
656 +# define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0
657 +
658 +#define DSI1_TST_SEL 0x78
659 +#define DSI1_TST_MON 0x7c
660 +#define DSI1_PHY_TST1 0x80
661 +#define DSI1_PHY_TST2 0x84
662 +#define DSI1_PHY_FIFO_STAT 0x88
663 +/* Actually, all registers in the range that aren't otherwise claimed
664 + * will return the ID.
665 + */
666 +#define DSI1_ID 0x8c
667 +
668 +/* General DSI hardware state. */
669 +struct vc4_dsi {
670 + struct platform_device *pdev;
671 +
672 + struct mipi_dsi_host dsi_host;
673 + struct drm_encoder *encoder;
674 + struct drm_connector *connector;
675 + struct drm_panel *panel;
676 +
677 + void __iomem *regs;
678 +
679 + struct dma_chan *reg_dma_chan;
680 + dma_addr_t reg_dma_paddr;
681 + u32 *reg_dma_mem;
682 + dma_addr_t reg_paddr;
683 +
684 + /* Whether we're on bcm2835's DSI0 or DSI1. */
685 + int port;
686 +
687 + /* DSI channel for the panel we're connected to. */
688 + u32 channel;
689 + u32 lanes;
690 + enum mipi_dsi_pixel_format format;
691 + u32 mode_flags;
692 +
693 + /* Input clock to the PHY, for the DSI escape clock. */
694 + struct clk *escape_clock;
695 +
696 + /* Input clock to the PHY, used to generate the DSI bit
697 + * clock.
698 + */
699 + struct clk *pll_phy_clock;
700 +
701 + /* Byte clock generated within the DSI PHY. */
702 + struct clk_hw phy_byte_clock;
703 +
704 + struct clk_onecell_data clk_onecell;
705 +
706 + /* Pixel clock output to the pixelvalve, generated from the
707 + * byte clock.
708 + */
709 + struct clk *pixel_clock;
710 +
711 + struct completion xfer_completion;
712 + int xfer_result;
713 +
714 + bool use_firmware_setup;
715 +};
716 +
717 +static inline void
718 +dsi_write(struct vc4_dsi *dsi, u32 offset, u32 val)
719 +{
720 + struct dma_chan *chan = dsi->reg_dma_chan;
721 + struct dma_async_tx_descriptor *tx;
722 + dma_cookie_t cookie;
723 + int ret;
724 +
725 +#if 0 /* XXX */
726 + dev_info(&dsi->pdev->dev, "WRITE 0x%04x -> 0x%08x\n", offset, val);
727 +#endif
728 +
729 + if (!chan) {
730 + writel(val, dsi->regs + offset);
731 + return;
732 + }
733 +
734 + *dsi->reg_dma_mem = val;
735 +
736 + tx = chan->device->device_prep_dma_memcpy(chan,
737 + dsi->reg_paddr + offset,
738 + dsi->reg_dma_paddr,
739 + 4, 0);
740 + if (!tx) {
741 + DRM_ERROR("Failed to set up DMA register write\n");
742 + return;
743 + }
744 +
745 + cookie = tx->tx_submit(tx);
746 + ret = dma_submit_error(cookie);
747 + if (ret) {
748 + DRM_ERROR("Failed to submit DMA: %d\n", ret);
749 + return;
750 + }
751 + ret = dma_sync_wait(chan, cookie);
752 + if (ret)
753 + DRM_ERROR("Failed to wait for DMA: %d\n", ret);
754 +
755 +#if 0 /* XXX */
756 + if (offset != DSI1_TXPKT_CMD_FIFO &&
757 + offset != DSI1_TXPKT_PIX_FIFO) {
758 + dev_info(&dsi->pdev->dev,
759 + " -> 0x%08x\n",
760 + readl(dsi->regs + (offset)));
761 + }
762 +#endif
763 +}
764 +
765 +#define DSI_READ(offset) readl(dsi->regs + (offset))
766 +#define DSI_WRITE(offset, val) dsi_write(dsi, offset, val)
767 +#define DSI_PORT_READ(offset) \
768 + DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset)
769 +#define DSI_PORT_WRITE(offset, val) \
770 + DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val)
771 +#define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit)
772 +
773 +/* VC4 DSI encoder KMS struct */
774 +struct vc4_dsi_encoder {
775 + struct vc4_encoder base;
776 + struct vc4_dsi *dsi;
777 +};
778 +
779 +static inline struct vc4_dsi_encoder *
780 +to_vc4_dsi_encoder(struct drm_encoder *encoder)
781 +{
782 + return container_of(encoder, struct vc4_dsi_encoder, base.base);
783 +}
784 +#define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host)
785 +
786 +/* VC4 DSI connector KMS struct */
787 +struct vc4_dsi_connector {
788 + struct drm_connector base;
789 + struct vc4_dsi *dsi;
790 +
791 + /* Since the connector is attached to just the one encoder,
792 + * this is the reference to it so we can do the best_encoder()
793 + * hook.
794 + */
795 + struct drm_encoder *encoder;
796 +};
797 +
798 +static inline struct vc4_dsi_connector *
799 +to_vc4_dsi_connector(struct drm_connector *connector)
800 +{
801 + return container_of(connector, struct vc4_dsi_connector, base);
802 +}
803 +
804 +static const struct debugfs_reg32 dsi0_regs[] = {
805 + VC4_DEBUG_REG(DSI0_CTRL),
806 + VC4_DEBUG_REG(DSI0_STAT),
807 + VC4_DEBUG_REG(DSI0_DISP0_CTRL),
808 + VC4_DEBUG_REG(DSI0_DISP1_CTRL),
809 + VC4_DEBUG_REG(DSI0_PHYC),
810 + VC4_DEBUG_REG(DSI0_STAT),
811 + VC4_DEBUG_REG(DSI0_HS_CLT0),
812 + VC4_DEBUG_REG(DSI0_HS_CLT1),
813 + VC4_DEBUG_REG(DSI0_HS_CLT2),
814 + VC4_DEBUG_REG(DSI0_HS_DLT3),
815 + VC4_DEBUG_REG(DSI0_HS_DLT4),
816 + VC4_DEBUG_REG(DSI0_HS_DLT5),
817 + VC4_DEBUG_REG(DSI0_HS_DLT6),
818 + VC4_DEBUG_REG(DSI0_HS_DLT7),
819 + VC4_DEBUG_REG(DSI0_PHY_AFEC0),
820 + VC4_DEBUG_REG(DSI0_PHY_AFEC1),
821 + VC4_DEBUG_REG(DSI0_ID),
822 +};
823 +
824 +static const struct debugfs_reg32 dsi1_regs[] = {
825 + VC4_DEBUG_REG(DSI1_CTRL),
826 + VC4_DEBUG_REG(DSI1_STAT),
827 + VC4_DEBUG_REG(DSI1_DISP0_CTRL),
828 + VC4_DEBUG_REG(DSI1_DISP1_CTRL),
829 + VC4_DEBUG_REG(DSI1_PHYC),
830 + VC4_DEBUG_REG(DSI1_STAT),
831 + VC4_DEBUG_REG(DSI1_HS_CLT0),
832 + VC4_DEBUG_REG(DSI1_HS_CLT1),
833 + VC4_DEBUG_REG(DSI1_HS_CLT2),
834 + VC4_DEBUG_REG(DSI1_HS_DLT3),
835 + VC4_DEBUG_REG(DSI1_HS_DLT4),
836 + VC4_DEBUG_REG(DSI1_HS_DLT5),
837 + VC4_DEBUG_REG(DSI1_HS_DLT6),
838 + VC4_DEBUG_REG(DSI1_HS_DLT7),
839 + VC4_DEBUG_REG(DSI1_PHY_AFEC0),
840 + VC4_DEBUG_REG(DSI1_PHY_AFEC1),
841 + VC4_DEBUG_REG(DSI1_ID),
842 +};
843 +
844 +static void vc4_dsi_dump_regs(struct vc4_dsi *dsi, const char *prefix)
845 +{
846 + if (dsi->port == 0) {
847 + vc4_dump_regs32(dsi0_regs, ARRAY_SIZE(dsi0_regs), dsi->regs,
848 + prefix);
849 + } else {
850 + vc4_dump_regs32(dsi1_regs, ARRAY_SIZE(dsi1_regs), dsi->regs,
851 + prefix);
852 + }
853 +}
854 +
855 +#ifdef CONFIG_DEBUG_FS
856 +int vc4_dsi_debugfs_regs(struct seq_file *m, void *number)
857 +{
858 + struct drm_info_node *node = (struct drm_info_node *)m->private;
859 + struct drm_device *dev = node->minor->dev;
860 + struct vc4_dev *vc4 = to_vc4_dev(dev);
861 + struct vc4_dsi *dsi;
862 + int port = (uintptr_t)number;
863 +
864 + if (port == 0) {
865 + dsi = vc4->dsi0;
866 + debugfs_print_regs32(m, dsi0_regs, ARRAY_SIZE(dsi0_regs),
867 + dsi->regs, "");
868 + } else {
869 + dsi = vc4->dsi1;
870 + debugfs_print_regs32(m, dsi1_regs, ARRAY_SIZE(dsi1_regs),
871 + dsi->regs, "");
872 + }
873 +
874 + return 0;
875 +}
876 +#endif
877 +
878 +static enum drm_connector_status
879 +vc4_dsi_connector_detect(struct drm_connector *connector, bool force)
880 +{
881 + struct vc4_dsi_connector *vc4_connector =
882 + to_vc4_dsi_connector(connector);
883 + struct vc4_dsi *dsi = vc4_connector->dsi;
884 +
885 + if (dsi->panel)
886 + return connector_status_connected;
887 + else
888 + return connector_status_disconnected;
889 +}
890 +
891 +static void vc4_dsi_connector_destroy(struct drm_connector *connector)
892 +{
893 + drm_connector_unregister(connector);
894 + drm_connector_cleanup(connector);
895 +}
896 +
897 +static int vc4_dsi_connector_get_modes(struct drm_connector *connector)
898 +{
899 + struct vc4_dsi_connector *vc4_connector =
900 + to_vc4_dsi_connector(connector);
901 + struct vc4_dsi *dsi = vc4_connector->dsi;
902 +
903 + if (dsi->panel)
904 + return drm_panel_get_modes(dsi->panel);
905 +
906 + return 0;
907 +}
908 +
909 +static struct drm_encoder *
910 +vc4_dsi_connector_best_encoder(struct drm_connector *connector)
911 +{
912 + struct vc4_dsi_connector *dsi_connector =
913 + to_vc4_dsi_connector(connector);
914 + return dsi_connector->encoder;
915 +}
916 +
917 +static const struct drm_connector_funcs vc4_dsi_connector_funcs = {
918 + .dpms = drm_atomic_helper_connector_dpms,
919 + .detect = vc4_dsi_connector_detect,
920 + .fill_modes = drm_helper_probe_single_connector_modes,
921 + .destroy = vc4_dsi_connector_destroy,
922 + .reset = drm_atomic_helper_connector_reset,
923 + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
924 + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
925 +};
926 +
927 +static const struct drm_connector_helper_funcs vc4_dsi_connector_helper_funcs = {
928 + .get_modes = vc4_dsi_connector_get_modes,
929 + .best_encoder = vc4_dsi_connector_best_encoder,
930 +};
931 +
932 +static struct drm_connector *vc4_dsi_connector_init(struct drm_device *dev,
933 + struct vc4_dsi *dsi)
934 +{
935 + struct drm_connector *connector = NULL;
936 + struct vc4_dsi_connector *dsi_connector;
937 + int ret = 0;
938 +
939 + dsi_connector = devm_kzalloc(dev->dev, sizeof(*dsi_connector),
940 + GFP_KERNEL);
941 + if (!dsi_connector) {
942 + ret = -ENOMEM;
943 + goto fail;
944 + }
945 + connector = &dsi_connector->base;
946 +
947 + dsi_connector->encoder = dsi->encoder;
948 + dsi_connector->dsi = dsi;
949 +
950 + drm_connector_init(dev, connector, &vc4_dsi_connector_funcs,
951 + DRM_MODE_CONNECTOR_DSI);
952 + drm_connector_helper_add(connector, &vc4_dsi_connector_helper_funcs);
953 +
954 + connector->polled = 0;
955 + connector->interlace_allowed = 0;
956 + connector->doublescan_allowed = 0;
957 +
958 + drm_mode_connector_attach_encoder(connector, dsi->encoder);
959 +
960 + return connector;
961 +
962 + fail:
963 + if (connector)
964 + vc4_dsi_connector_destroy(connector);
965 +
966 + return ERR_PTR(ret);
967 +}
968 +
969 +static void vc4_dsi_encoder_destroy(struct drm_encoder *encoder)
970 +{
971 + drm_encoder_cleanup(encoder);
972 +}
973 +
974 +static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = {
975 + .destroy = vc4_dsi_encoder_destroy,
976 +};
977 +
978 +static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch)
979 +{
980 + u32 afec0 = DSI_PORT_READ(PHY_AFEC0);
981 +
982 + if (latch)
983 + afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
984 + else
985 + afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS);
986 +
987 + DSI_PORT_WRITE(PHY_AFEC0, afec0);
988 +}
989 +
990 +/* Enters or exits Ultra Low Power State. */
991 +static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps)
992 +{
993 + u32 phyc_ulps = (DSI_PORT_BIT(PHYC_CLANE_ULPS) |
994 + DSI_PHYC_DLANE0_ULPS |
995 + (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) |
996 + (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) |
997 + (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0));
998 + u32 stat_ulps = (DSI1_STAT_PHY_CLOCK_ULPS |
999 + DSI1_STAT_PHY_D0_ULPS |
1000 + (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) |
1001 + (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) |
1002 + (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0));
1003 + u32 stat_stop = (DSI1_STAT_PHY_CLOCK_STOP |
1004 + DSI1_STAT_PHY_D0_STOP |
1005 + (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) |
1006 + (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) |
1007 + (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0));
1008 + int ret;
1009 +
1010 + DSI_PORT_WRITE(STAT, stat_ulps);
1011 + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps);
1012 + ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 20);
1013 + if (ret) {
1014 + dev_warn(&dsi->pdev->dev,
1015 + "Timeout waiting for DSI ULPS entry: STAT 0x%08x",
1016 + DSI_PORT_READ(STAT));
1017 + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
1018 + vc4_dsi_latch_ulps(dsi, false);
1019 + return;
1020 + }
1021 +
1022 + /* The DSI module can't be disabled while the module is
1023 + * generating ULPS state. So, to be able to disable the
1024 + * module, we have the AFE latch the ULPS state and continue
1025 + * on to having the module enter STOP.
1026 + */
1027 + vc4_dsi_latch_ulps(dsi, ulps);
1028 +
1029 + DSI_PORT_WRITE(STAT, stat_stop);
1030 + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
1031 + ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 20);
1032 + if (ret) {
1033 + dev_warn(&dsi->pdev->dev,
1034 + "Timeout waiting for DSI STOP entry: STAT 0x%08x",
1035 + DSI_PORT_READ(STAT));
1036 + DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps);
1037 + return;
1038 + }
1039 +}
1040 +
1041 +static uint32_t
1042 +dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui)
1043 +{
1044 + /* The HS timings have to be rounded up to a multiple of 8
1045 + * because we're using the byte clock.
1046 + */
1047 + return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8);
1048 +}
1049 +
1050 +/* ESC always runs at 100Mhz. */
1051 +#define ESC_TIME_NS 10
1052 +
1053 +static uint32_t
1054 +dsi_esc_timing(u32 ns)
1055 +{
1056 + return DIV_ROUND_UP(ns, ESC_TIME_NS);
1057 +}
1058 +
1059 +static void vc4_dsi_encoder_disable(struct drm_encoder *encoder)
1060 +{
1061 + struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
1062 + struct vc4_dsi *dsi = vc4_encoder->dsi;
1063 +
1064 + drm_panel_disable(dsi->panel);
1065 +
1066 + if (!dsi->use_firmware_setup)
1067 + vc4_dsi_ulps(dsi, true);
1068 +
1069 + drm_panel_unprepare(dsi->panel);
1070 +
1071 + if (dsi->use_firmware_setup) {
1072 + /* Since we're using the firmware setup and aren't
1073 + * communicating with the panel to bring the link
1074 + * down, we need to just keep the clocks and DSI
1075 + * module running.
1076 + */
1077 + } else {
1078 + clk_disable_unprepare(dsi->pll_phy_clock);
1079 + clk_disable_unprepare(dsi->escape_clock);
1080 + clk_disable_unprepare(dsi->pixel_clock);
1081 + }
1082 +}
1083 +
1084 +static void vc4_dsi_encoder_enable(struct drm_encoder *encoder)
1085 +{
1086 + struct drm_display_mode *mode = &encoder->crtc->mode;
1087 + struct vc4_dsi_encoder *vc4_encoder = to_vc4_dsi_encoder(encoder);
1088 + struct vc4_dsi *dsi = vc4_encoder->dsi;
1089 + struct device *dev = &dsi->pdev->dev;
1090 + uint32_t format = 0, divider = 0;
1091 + bool debug_dump_regs = false;
1092 + unsigned long hs_clock;
1093 + uint32_t ui_ns;
1094 + /* Minimum LP state duration in escape clock cycles. */
1095 + uint32_t lpx = dsi_esc_timing(60);
1096 + uint32_t phyc;
1097 + int ret;
1098 +
1099 + ret = drm_panel_prepare(dsi->panel);
1100 + if (ret) {
1101 + DRM_ERROR("Panel failed to prepare\n");
1102 + return;
1103 + }
1104 +
1105 + if (debug_dump_regs)
1106 + vc4_dsi_dump_regs(dsi, "DSI before: ");
1107 +
1108 + /* XXX */
1109 + if (!dsi->use_firmware_setup) {
1110 + ret = clk_set_rate(dsi->pll_phy_clock, 2020000000 / 3);
1111 + if (ret)
1112 + dev_err(&dsi->pdev->dev, "Failed to set phy clock: %d\n", ret);
1113 + dev_info(&dsi->pdev->dev, "Tried to set clock to: %d\n", 2000000000 / 3);
1114 +
1115 + ret = clk_prepare_enable(dsi->escape_clock);
1116 + if (ret) {
1117 + DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
1118 + return;
1119 + }
1120 +
1121 + ret = clk_prepare_enable(dsi->pll_phy_clock);
1122 + if (ret) {
1123 + DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
1124 + return;
1125 + }
1126 +
1127 + ret = clk_set_rate(dsi->pixel_clock, mode->clock * 1000);
1128 + if (ret)
1129 + dev_err(dev, "Failed to set pixel clock: %d\n", ret);
1130 + dev_info(&dsi->pdev->dev, "Tried to set pixel clock to: %d\n", mode->clock * 1000);
1131 +
1132 + ret = clk_prepare_enable(dsi->pixel_clock);
1133 + if (ret) {
1134 + DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret);
1135 + return;
1136 + }
1137 + }
1138 +
1139 + hs_clock = clk_get_rate(dsi->pll_phy_clock);
1140 +
1141 + /* Reset the DSI and all its fifos. */
1142 + if (dsi->port == 0) {
1143 + DSI_PORT_WRITE(CTRL,
1144 + DSI_CTRL_SOFT_RESET_CFG |
1145 + DSI0_CTRL_RESET_FIFOS);
1146 + } else {
1147 + DSI_PORT_WRITE(CTRL,
1148 + DSI_CTRL_SOFT_RESET_CFG |
1149 + DSI1_CTRL_RESET_FIFOS);
1150 + }
1151 +
1152 + DSI_PORT_WRITE(CTRL,
1153 + DSI_CTRL_HSDT_EOT_DISABLE |
1154 + DSI_CTRL_RX_LPDT_EOT_DISABLE);
1155 +
1156 + switch (dsi->format) {
1157 + case MIPI_DSI_FMT_RGB888:
1158 + format = DSI_PFORMAT_RGB888;
1159 + divider = 24 / dsi->lanes;
1160 + break;
1161 + case MIPI_DSI_FMT_RGB666:
1162 + format = DSI_PFORMAT_RGB666;
1163 + divider = 24 / dsi->lanes;
1164 + break;
1165 + case MIPI_DSI_FMT_RGB666_PACKED:
1166 + format = DSI_PFORMAT_RGB666_PACKED;
1167 + divider = 18 / dsi->lanes;
1168 + break;
1169 + case MIPI_DSI_FMT_RGB565:
1170 + format = DSI_PFORMAT_RGB565;
1171 + divider = 16 / dsi->lanes;
1172 + break;
1173 + }
1174 +
1175 + /* Set AFE CTR00/CTR1 to release powerdown of analog. */
1176 + if (dsi->port == 0) {
1177 + u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
1178 + VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ));
1179 +
1180 + if (dsi->lanes < 2)
1181 + afec0 |= DSI0_PHY_AFEC0_PD_DLANE1;
1182 +
1183 + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
1184 + afec0 |= DSI0_PHY_AFEC0_RESET;
1185 +
1186 + DSI_PORT_WRITE(PHY_AFEC0, afec0);
1187 +
1188 + DSI_PORT_WRITE(PHY_AFEC1,
1189 + VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) |
1190 + VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) |
1191 + VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE));
1192 + } else {
1193 + u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) |
1194 + VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) |
1195 + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) |
1196 + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) |
1197 + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) |
1198 + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) |
1199 + VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3));
1200 +
1201 + if (dsi->lanes < 4)
1202 + afec0 |= DSI1_PHY_AFEC0_PD_DLANE3;
1203 + if (dsi->lanes < 3)
1204 + afec0 |= DSI1_PHY_AFEC0_PD_DLANE2;
1205 + if (dsi->lanes < 2)
1206 + afec0 |= DSI1_PHY_AFEC0_PD_DLANE1;
1207 +
1208 + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO))
1209 + afec0 |= DSI1_PHY_AFEC0_RESET;
1210 +
1211 + DSI_PORT_WRITE(PHY_AFEC0, afec0);
1212 +
1213 + DSI_PORT_WRITE(PHY_AFEC1, 0);
1214 + }
1215 +
1216 + /* How many ns one DSI unit interval is. Note that the clock
1217 + * is DDR, so there's an extra divide by 2.
1218 + */
1219 + ui_ns = DIV_ROUND_UP(500000000, hs_clock);
1220 +
1221 + DSI_PORT_WRITE(HS_CLT0,
1222 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0),
1223 + DSI_HS_CLT0_CZERO) |
1224 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8),
1225 + DSI_HS_CLT0_CPRE) |
1226 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0),
1227 + DSI_HS_CLT0_CPREP));
1228 +
1229 + DSI_PORT_WRITE(HS_CLT1,
1230 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0),
1231 + DSI_HS_CLT1_CTRAIL) |
1232 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52),
1233 + DSI_HS_CLT1_CPOST));
1234 +
1235 + DSI_PORT_WRITE(HS_CLT2,
1236 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0),
1237 + DSI_HS_CLT2_WUP));
1238 +
1239 + DSI_PORT_WRITE(HS_DLT3,
1240 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0),
1241 + DSI_HS_DLT3_EXIT) |
1242 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6),
1243 + DSI_HS_DLT3_ZERO) |
1244 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4),
1245 + DSI_HS_DLT3_PRE));
1246 +
1247 + DSI_PORT_WRITE(HS_DLT4,
1248 + VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0),
1249 + DSI_HS_DLT4_LPX) |
1250 + VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8),
1251 + dsi_hs_timing(ui_ns, 60, 4)),
1252 + DSI_HS_DLT4_TRAIL) |
1253 + VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT));
1254 +
1255 + DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000, 5000),
1256 + DSI_HS_DLT5_INIT));
1257 +
1258 + DSI_PORT_WRITE(HS_DLT6,
1259 + VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) |
1260 + VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) |
1261 + VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) |
1262 + VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX));
1263 +
1264 + DSI_PORT_WRITE(HS_DLT7,
1265 + VC4_SET_FIELD(dsi_esc_timing(1000000),
1266 + DSI_HS_DLT7_LP_WUP));
1267 +
1268 + /* Define EOT PKT in EOT reg. */
1269 +
1270 + phyc = (DSI_PHYC_DLANE0_ENABLE |
1271 + (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) |
1272 + (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) |
1273 + (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) |
1274 + (dsi->port == 0 ?
1275 + VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) :
1276 + VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT)) |
1277 + DSI_PORT_BIT(PHYC_CLANE_ENABLE));
1278 +
1279 + DSI_PORT_WRITE(CTRL,
1280 + DSI_PORT_READ(CTRL) |
1281 + DSI_CTRL_CAL_BYTE);
1282 +
1283 + /* HS timeout in HS clock cycles: disabled. */
1284 + DSI_PORT_WRITE(HSTX_TO_CNT, 0);
1285 + /* LP receive timeout in HS clocks. */
1286 + DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff);
1287 + /* Bus turnaround timeout */
1288 + DSI_PORT_WRITE(TA_TO_CNT, 100000);
1289 + /* Display reset sequence timeout */
1290 + DSI_PORT_WRITE(TA_TO_CNT, 100000);
1291 +
1292 + if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
1293 + DSI_PORT_WRITE(DISP0_CTRL,
1294 + VC4_SET_FIELD(divider, DSI_DISP0_PIX_CLK_DIV) |
1295 + VC4_SET_FIELD(format, DSI_DISP0_PFORMAT) |
1296 + VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME,
1297 + DSI_DISP0_LP_STOP_CTRL) |
1298 + DSI_DISP0_ST_END |
1299 + DSI_DISP0_ENABLE);
1300 + } else {
1301 + DSI_PORT_WRITE(DISP0_CTRL,
1302 + DSI_DISP0_COMMAND_MODE |
1303 + DSI_DISP0_ENABLE);
1304 + }
1305 +
1306 + /* Set up DISP1 for transferring long command payloads through
1307 + * the pixfifo.
1308 + */
1309 + DSI_PORT_WRITE(DISP1_CTRL,
1310 + VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE,
1311 + DSI_DISP1_PFORMAT) |
1312 + DSI_DISP1_ENABLE);
1313 +
1314 + if (!(dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
1315 + phyc |= DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS);
1316 +
1317 + DSI_PORT_WRITE(PHYC, phyc);
1318 +
1319 + /* Ungate the block. */
1320 + if (dsi->port == 0)
1321 + DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0);
1322 + else {
1323 + DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN);
1324 + }
1325 +
1326 + if (!dsi->use_firmware_setup)
1327 + vc4_dsi_ulps(dsi, false);
1328 +
1329 + if (debug_dump_regs)
1330 + vc4_dsi_dump_regs(dsi, "DSI after: ");
1331 +
1332 + ret = drm_panel_enable(dsi->panel);
1333 + if (ret) {
1334 + DRM_ERROR("Panel failed to enable\n");
1335 + drm_panel_unprepare(dsi->panel);
1336 + return;
1337 + }
1338 +}
1339 +
1340 +static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host,
1341 + const struct mipi_dsi_msg *msg)
1342 +{
1343 + struct vc4_dsi *dsi = host_to_dsi(host);
1344 + struct mipi_dsi_packet packet;
1345 + u32 pkth = 0, pktc = 0;
1346 + int i, ret;
1347 + bool is_long = mipi_dsi_packet_format_is_long(msg->type);
1348 + u32 cmd_fifo_len = 0, pix_fifo_len = 0;
1349 +
1350 + mipi_dsi_create_packet(&packet, msg);
1351 + pr_err("DSI host xfer %db, %s\n",
1352 + packet.payload_length,
1353 + is_long ? "long" : "short");
1354 +
1355 + pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT);
1356 + pkth |= VC4_SET_FIELD(packet.header[1] |
1357 + (packet.header[2] << 8),
1358 + DSI_TXPKT1H_BC_PARAM);
1359 + if (is_long) {
1360 + /* Divide data across the various FIFOs we have available.
1361 + * The command FIFO takes byte-oriented data, but is of
1362 + * limited size. The pixel FIFO (never actually used for
1363 + * pixel data in reality) is word oriented, and substantially
1364 + * larger. So, we use the pixel FIFO for most of the data,
1365 + * sending the residual bytes in the command FIFO at the start.
1366 + *
1367 + * With this arrangement, the command FIFO will never get full.
1368 + */
1369 + cmd_fifo_len = packet.payload_length % DSI_PIX_FIFO_WIDTH;
1370 + pix_fifo_len = ((packet.payload_length - cmd_fifo_len) /
1371 + DSI_PIX_FIFO_WIDTH);
1372 +
1373 + WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH);
1374 +
1375 + pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO);
1376 + }
1377 +
1378 + if (msg->rx_len) {
1379 + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX,
1380 + DSI_TXPKT1C_CMD_CTRL);
1381 + } else {
1382 + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX,
1383 + DSI_TXPKT1C_CMD_CTRL);
1384 + }
1385 +
1386 + dev_info(&dsi->pdev->dev, "FIFO setup: %d, %d\n",
1387 + cmd_fifo_len, pix_fifo_len);
1388 +
1389 + for (i = 0; i < cmd_fifo_len; i++)
1390 + DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]);
1391 + for (i = 0; i < pix_fifo_len; i++) {
1392 + const uint8_t *pix = packet.payload + cmd_fifo_len + i * 4;
1393 + DSI_PORT_WRITE(TXPKT_PIX_FIFO,
1394 + pix[0] |
1395 + pix[1] << 8 |
1396 + pix[2] << 16 |
1397 + pix[3] << 24);
1398 + }
1399 +
1400 + if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1401 + pktc |= DSI_TXPKT1C_CMD_MODE_LP;
1402 + if (is_long)
1403 + pktc |= DSI_TXPKT1C_CMD_TYPE_LONG;
1404 +
1405 + /* Send one copy of the packet. Larger repeats are used for pixel
1406 + * data in command mode.
1407 + */
1408 + pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT);
1409 +
1410 + pktc |= DSI_TXPKT1C_CMD_EN;
1411 + if (pix_fifo_len) {
1412 + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY,
1413 + DSI_TXPKT1C_DISPLAY_NO);
1414 + } else {
1415 + pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT,
1416 + DSI_TXPKT1C_DISPLAY_NO);
1417 + }
1418 +
1419 + /* Enable the appropriate interrupt for the transfer completion. */
1420 + dsi->xfer_result = 0;
1421 + reinit_completion(&dsi->xfer_completion);
1422 + DSI_PORT_WRITE(INT_STAT, DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF);
1423 + if (msg->rx_len) {
1424 + DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1425 + DSI1_INT_PHY_DIR_RTF));
1426 + } else {
1427 + DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED |
1428 + DSI1_INT_TXPKT1_DONE));
1429 + }
1430 +
1431 + /* Send the packet. */
1432 + DSI_PORT_WRITE(TXPKT1H, pkth);
1433 + DSI_PORT_WRITE(TXPKT1C, pktc);
1434 +
1435 + if (!wait_for_completion_timeout(&dsi->xfer_completion,
1436 + msecs_to_jiffies(100))) {
1437 + u32 stat = DSI_PORT_READ(STAT);
1438 +
1439 + dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout");
1440 + dev_err(&dsi->pdev->dev, "INT_STAT: 0x%08x, STAT: 0x%08x\n",
1441 + DSI_PORT_READ(INT_STAT), stat);
1442 +
1443 + if (stat & DSI1_STAT_TXPKT1_DONE) {
1444 + dev_info(&dsi->pdev->dev,
1445 + "STAT reports DONE, though.\n");
1446 + ret = 0;
1447 + } else {
1448 + ret = -ETIMEDOUT;
1449 + }
1450 + } else {
1451 + ret = dsi->xfer_result;
1452 + }
1453 +
1454 + DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1455 + if (ret)
1456 + goto reset_fifo_and_return;
1457 +
1458 + if (ret == 0 && msg->rx_len) {
1459 + u32 rxpkt1h = DSI_PORT_READ(RXPKT1H);
1460 + u8 *msg_rx = msg->rx_buf;
1461 +
1462 + if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) {
1463 + u32 rxlen = VC4_GET_FIELD(rxpkt1h, DSI_RXPKT1H_BC_PARAM);
1464 +
1465 + if (rxlen != msg->rx_len) {
1466 + DRM_ERROR("DSI returned %db, expecting %db\n",
1467 + rxlen, msg->rx_len);
1468 + ret = -ENXIO;
1469 + goto reset_fifo_and_return;
1470 + }
1471 +
1472 + for (i = 0; i < msg->rx_len; i++)
1473 + msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO);
1474 + } else {
1475 + /* XXX: AWER */
1476 +
1477 + msg_rx[0] = VC4_GET_FIELD(rxpkt1h,
1478 + DSI_RXPKT1H_SHORT_0);
1479 + if (msg->rx_len > 1) {
1480 + msg_rx[1] = VC4_GET_FIELD(rxpkt1h,
1481 + DSI_RXPKT1H_SHORT_1);
1482 + }
1483 + }
1484 + }
1485 +
1486 + return ret;
1487 +
1488 +reset_fifo_and_return:
1489 + DRM_ERROR("DSI TRANSFER failed, resetting: %d\n", ret);
1490 +
1491 + DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN);
1492 + udelay(1);
1493 + if (dsi->port == 0) {
1494 + DSI_PORT_WRITE(CTRL,
1495 + DSI_PORT_READ(CTRL) | DSI0_CTRL_RESET_FIFOS);
1496 + } else {
1497 + DSI_PORT_WRITE(CTRL,
1498 + DSI_PORT_READ(CTRL) | DSI1_CTRL_RESET_FIFOS);
1499 + }
1500 +
1501 + DSI_PORT_WRITE(TXPKT1C, 0);
1502 + DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1503 +
1504 +
1505 + return ret;
1506 +}
1507 +
1508 +static int vc4_dsi_host_attach(struct mipi_dsi_host *host,
1509 + struct mipi_dsi_device *device)
1510 +{
1511 + struct vc4_dsi *dsi = host_to_dsi(host);
1512 +
1513 + dsi->lanes = device->lanes;
1514 + dsi->channel = device->channel;
1515 + dsi->format = device->format;
1516 + dsi->mode_flags = device->mode_flags;
1517 +
1518 + if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) {
1519 + dev_err(&dsi->pdev->dev,
1520 + "Only VIDEO mode panels supported currently.\n");
1521 + return 0;
1522 + }
1523 +
1524 + dsi->panel = of_drm_find_panel(device->dev.of_node);
1525 + if (dsi->panel)
1526 + return drm_panel_attach(dsi->panel, dsi->connector);
1527 +
1528 + drm_helper_hpd_irq_event(dsi->connector->dev);
1529 +
1530 + return 0;
1531 +}
1532 +
1533 +static int vc4_dsi_host_detach(struct mipi_dsi_host *host,
1534 + struct mipi_dsi_device *device)
1535 +{
1536 + struct vc4_dsi *dsi = host_to_dsi(host);
1537 +
1538 + if (dsi->panel) {
1539 + int ret = drm_panel_detach(dsi->panel);
1540 + if (ret)
1541 + return ret;
1542 +
1543 + dsi->panel = NULL;
1544 + }
1545 +
1546 + drm_helper_hpd_irq_event(dsi->connector->dev);
1547 +
1548 + return 0;
1549 +}
1550 +
1551 +static const struct mipi_dsi_host_ops vc4_dsi_host_ops = {
1552 + .attach = vc4_dsi_host_attach,
1553 + .detach = vc4_dsi_host_detach,
1554 + .transfer = vc4_dsi_host_transfer,
1555 +};
1556 +
1557 +static const struct drm_encoder_helper_funcs vc4_dsi_encoder_helper_funcs = {
1558 + .disable = vc4_dsi_encoder_disable,
1559 + .enable = vc4_dsi_encoder_enable,
1560 +};
1561 +
1562 +static const struct of_device_id vc4_dsi_dt_match[] = {
1563 + { .compatible = "brcm,bcm2835-dsi0", (void *)(uintptr_t)0 },
1564 + { .compatible = "brcm,bcm2835-dsi1", (void *)(uintptr_t)1 },
1565 + {}
1566 +};
1567 +
1568 +static long vc4_dsi_byte_clock_round_rate(struct clk_hw *hw, unsigned long rate,
1569 + unsigned long *parent_rate)
1570 +{
1571 + return *parent_rate / 8;
1572 +}
1573 +
1574 +static unsigned long vc4_dsi_byte_clock_get_rate(struct clk_hw *hw,
1575 + unsigned long parent_rate)
1576 +{
1577 + return parent_rate / 8;
1578 +}
1579 +
1580 +static int vc4_dsi_byte_clock_set_rate(struct clk_hw *hw,
1581 + unsigned long rate,
1582 + unsigned long parent_rate)
1583 +{
1584 + return 0;
1585 +}
1586 +
1587 +/* The byte clock has *no* ops filled. It's always running when the
1588 + * PHY is.
1589 + */
1590 +static const struct clk_ops vc4_dsi_byte_clock_ops = {
1591 + .recalc_rate = vc4_dsi_byte_clock_get_rate,
1592 + .set_rate = vc4_dsi_byte_clock_set_rate,
1593 + .round_rate = vc4_dsi_byte_clock_round_rate,
1594 +};
1595 +
1596 +static void dsi_handle_error(struct vc4_dsi *dsi,
1597 + irqreturn_t *ret, u32 stat, u32 bit,
1598 + const char *type)
1599 +{
1600 + if (!(stat & bit))
1601 + return;
1602 +
1603 + DRM_ERROR("DSI%d: %s error\n", dsi->port, type);
1604 + *ret = IRQ_HANDLED;
1605 +}
1606 +
1607 +static irqreturn_t vc4_dsi_irq_handler(int irq, void *data)
1608 +{
1609 + struct vc4_dsi *dsi = data;
1610 + u32 stat = DSI_PORT_READ(INT_STAT);
1611 + irqreturn_t ret = IRQ_NONE;
1612 +
1613 + DSI_PORT_WRITE(INT_STAT, stat);
1614 +
1615 + dsi_handle_error(dsi, &ret, stat,
1616 + DSI1_INT_ERR_SYNC_ESC, "LPDT sync");
1617 + dsi_handle_error(dsi, &ret, stat,
1618 + DSI1_INT_ERR_CONTROL, "data lane 0 sequence");
1619 + dsi_handle_error(dsi, &ret, stat,
1620 + DSI1_INT_ERR_CONT_LP0, "LP0 contention");
1621 + dsi_handle_error(dsi, &ret, stat,
1622 + DSI1_INT_ERR_CONT_LP1, "LP1 contention");
1623 + dsi_handle_error(dsi, &ret, stat,
1624 + DSI1_INT_HSTX_TO, "HSTX timeout");
1625 + dsi_handle_error(dsi, &ret, stat,
1626 + DSI1_INT_LPRX_TO, "LPRX timeout");
1627 + dsi_handle_error(dsi, &ret, stat,
1628 + DSI1_INT_TA_TO, "turnaround timeout");
1629 + dsi_handle_error(dsi, &ret, stat,
1630 + DSI1_INT_PR_TO, "peripheral reset timeout");
1631 +
1632 + if (stat & (DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF)) {
1633 + complete(&dsi->xfer_completion);
1634 + ret = IRQ_HANDLED;
1635 + } else if (stat & DSI1_INT_HSTX_TO) {
1636 + complete(&dsi->xfer_completion);
1637 + dsi->xfer_result = -ETIMEDOUT;
1638 + ret = IRQ_HANDLED;
1639 + }
1640 +
1641 + return ret;
1642 +}
1643 +
1644 +static int
1645 +vc4_dsi_init_phy_byte_clock(struct vc4_dsi *dsi)
1646 +{
1647 + struct device *dev = &dsi->pdev->dev;
1648 + const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
1649 + struct clk_init_data init;
1650 + struct clk *clk;
1651 +
1652 + memset(&init, 0, sizeof(init));
1653 + init.parent_names = &parent_name;
1654 + init.num_parents = 1;
1655 + if (dsi->port == 1)
1656 + init.name = "dsi1_byte";
1657 + else
1658 + init.name = "dsi0_byte";
1659 + init.ops = &vc4_dsi_byte_clock_ops;
1660 + init.flags = 0;
1661 +
1662 + dsi->phy_byte_clock.init = &init;
1663 + clk = devm_clk_register(dev, &dsi->phy_byte_clock);
1664 + if (IS_ERR(clk))
1665 + return PTR_ERR(clk);
1666 +
1667 + /* Use the onecell provider because we may need to expose the
1668 + * DDR and DDR2 clocks at some point, which we'd want to put
1669 + * in slots 1 and 2.
1670 + */
1671 + dsi->clk_onecell.clk_num = 1;
1672 + dsi->clk_onecell.clks = devm_kcalloc(dev,
1673 + dsi->clk_onecell.clk_num,
1674 + sizeof(*dsi->clk_onecell.clks),
1675 + GFP_KERNEL);
1676 + if (!dsi->clk_onecell.clks)
1677 + return -ENOMEM;
1678 +
1679 + dsi->clk_onecell.clks[0] = clk;
1680 +
1681 + return of_clk_add_provider(dev->of_node,
1682 + of_clk_src_onecell_get,
1683 + &dsi->clk_onecell);
1684 +}
1685 +
1686 +static int vc4_dsi_bind(struct device *dev, struct device *master, void *data)
1687 +{
1688 + struct platform_device *pdev = to_platform_device(dev);
1689 + struct drm_device *drm = dev_get_drvdata(master);
1690 + struct vc4_dev *vc4 = to_vc4_dev(drm);
1691 + struct vc4_dsi *dsi;
1692 + struct vc4_dsi_encoder *vc4_dsi_encoder;
1693 + const struct of_device_id *match;
1694 + dma_cap_mask_t dma_mask;
1695 + int ret;
1696 +
1697 + dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1698 + if (!dsi)
1699 + return -ENOMEM;
1700 +
1701 + match = of_match_device(vc4_dsi_dt_match, dev);
1702 + if (!match)
1703 + return -ENODEV;
1704 +
1705 + dsi->port = (uintptr_t)match->data;
1706 +
1707 + vc4_dsi_encoder = devm_kzalloc(dev, sizeof(*vc4_dsi_encoder),
1708 + GFP_KERNEL);
1709 + if (!vc4_dsi_encoder)
1710 + return -ENOMEM;
1711 + vc4_dsi_encoder->base.type = VC4_ENCODER_TYPE_DSI1;
1712 + vc4_dsi_encoder->dsi = dsi;
1713 + dsi->encoder = &vc4_dsi_encoder->base.base;
1714 +
1715 + dsi->pdev = pdev;
1716 + dsi->regs = vc4_ioremap_regs(pdev, 0);
1717 + if (IS_ERR(dsi->regs))
1718 + return PTR_ERR(dsi->regs);
1719 +
1720 + if (DSI_PORT_READ(ID) != DSI_ID_VALUE) {
1721 + dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n",
1722 + DSI_PORT_READ(ID), DSI_ID_VALUE);
1723 + return -ENODEV;
1724 + }
1725 +
1726 + if (DSI_PORT_READ(CTRL) == 0) {
1727 + dev_info(dev, "DSI not set up by firmware.\n");
1728 + return 0;
1729 + }
1730 +
1731 + /* Set this flag to indicate that we're relying on boot-time
1732 + * DSI state and can't successfully reconfigure DSI yet.
1733 + */
1734 + dsi->use_firmware_setup = VC4_DSI_USE_FIRMWARE_SETUP;
1735 +
1736 + if (dsi->use_firmware_setup) {
1737 + /* Increment references to the various clocks so that
1738 + * they stay always enabled and the clock framework
1739 + * doesn't disable their parents.
1740 + */
1741 + ret = clk_prepare_enable(dsi->escape_clock);
1742 + if (ret) {
1743 + DRM_ERROR("Failed to refcount DSI escape clock: %d\n", ret);
1744 + return ret;
1745 + }
1746 +
1747 + ret = clk_prepare_enable(dsi->pll_phy_clock);
1748 + if (ret) {
1749 + DRM_ERROR("Failed to refcount DSI PLL: %d\n", ret);
1750 + return ret;
1751 + }
1752 +
1753 + ret = clk_prepare_enable(dsi->pixel_clock);
1754 + if (ret) {
1755 + DRM_ERROR("Failed to refcount pixel clock: %d\n", ret);
1756 + return ret;
1757 + }
1758 + }
1759 +
1760 + /* DSI1 has a broken AXI slave that doesn't respond to writes
1761 + * from the ARM. It does handle writes from the DMA engine,
1762 + * so set up a channel for talking to it.
1763 + */
1764 + if (dsi->port == 1) {
1765 + dsi->reg_dma_mem = dma_alloc_coherent(dev, 4,
1766 + &dsi->reg_dma_paddr,
1767 + GFP_KERNEL);
1768 + if (!dsi->reg_dma_mem) {
1769 + DRM_ERROR("Failed to get DMA memory\n");
1770 + return -ENOMEM;
1771 + }
1772 +
1773 + dma_cap_zero(dma_mask);
1774 + dma_cap_set(DMA_MEMCPY, dma_mask);
1775 + dsi->reg_dma_chan = dma_request_channel(dma_mask, NULL, NULL);
1776 + if (IS_ERR(dsi->reg_dma_chan)) {
1777 + ret = PTR_ERR(dsi->reg_dma_chan);
1778 + if (ret != -EPROBE_DEFER)
1779 + DRM_ERROR("Failed to get DMA channel: %d\n",
1780 + ret);
1781 + return ret;
1782 + }
1783 +
1784 + /* Get the physical address of the device's registers. The
1785 + * struct resource for the regs gives us the bus address
1786 + * instead.
1787 + */
1788 + dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node,
1789 + 0, NULL, NULL));
1790 + }
1791 +
1792 + init_completion(&dsi->xfer_completion);
1793 + /* At startup enable error-reporting interrupts and nothing else. */
1794 + DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED);
1795 + /* Clear any existing interrupt state. */
1796 + DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT));
1797 +
1798 + ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1799 + vc4_dsi_irq_handler, 0, "vc4 dsi", dsi);
1800 + if (ret) {
1801 + if (ret != -EPROBE_DEFER)
1802 + dev_err(dev, "Failed to get interrupt: %d\n", ret);
1803 + return ret;
1804 + }
1805 +
1806 + dsi->escape_clock = devm_clk_get(dev, "escape");
1807 + if (IS_ERR(dsi->escape_clock)) {
1808 + ret = PTR_ERR(dsi->escape_clock);
1809 + if (ret != -EPROBE_DEFER)
1810 + dev_err(dev, "Failed to get escape clock: %d\n", ret);
1811 + return ret;
1812 + }
1813 +
1814 + dsi->pll_phy_clock = devm_clk_get(dev, "phy");
1815 + if (IS_ERR(dsi->pll_phy_clock)) {
1816 + ret = PTR_ERR(dsi->pll_phy_clock);
1817 + if (ret != -EPROBE_DEFER)
1818 + dev_err(dev, "Failed to get phy clock: %d\n", ret);
1819 + return ret;
1820 + }
1821 +
1822 + dsi->pixel_clock = devm_clk_get(dev, "pixel");
1823 + if (IS_ERR(dsi->pixel_clock)) {
1824 + ret = PTR_ERR(dsi->pixel_clock);
1825 + if (ret != -EPROBE_DEFER)
1826 + dev_err(dev, "Failed to get pixel clock: %d\n", ret);
1827 + return ret;
1828 + }
1829 +
1830 + /* The esc clock rate is supposed to always be 100Mhz. */
1831 + ret = clk_set_rate(dsi->escape_clock, 100 * 1000000);
1832 + if (ret) {
1833 + dev_err(dev, "Failed to set esc clock: %d\n", ret);
1834 + return ret;
1835 + }
1836 +
1837 + ret = vc4_dsi_init_phy_byte_clock(dsi);
1838 + if (ret)
1839 + return ret;
1840 +
1841 + if (dsi->port == 1)
1842 + vc4->dsi1 = dsi;
1843 +
1844 + drm_encoder_init(drm, dsi->encoder, &vc4_dsi_encoder_funcs,
1845 + DRM_MODE_ENCODER_DSI);
1846 + drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs);
1847 +
1848 + dsi->connector = vc4_dsi_connector_init(drm, dsi);
1849 + if (IS_ERR(dsi->connector)) {
1850 + ret = PTR_ERR(dsi->connector);
1851 + goto err_destroy_encoder;
1852 + }
1853 +
1854 + dsi->dsi_host.ops = &vc4_dsi_host_ops;
1855 + dsi->dsi_host.dev = dev;
1856 +
1857 + mipi_dsi_host_register(&dsi->dsi_host);
1858 +
1859 + dev_set_drvdata(dev, dsi);
1860 +
1861 + return 0;
1862 +
1863 +err_destroy_encoder:
1864 + vc4_dsi_encoder_destroy(dsi->encoder);
1865 +
1866 + return ret;
1867 +}
1868 +
1869 +static void vc4_dsi_unbind(struct device *dev, struct device *master,
1870 + void *data)
1871 +{
1872 + struct drm_device *drm = dev_get_drvdata(master);
1873 + struct vc4_dev *vc4 = to_vc4_dev(drm);
1874 + struct vc4_dsi *dsi = dev_get_drvdata(dev);
1875 +
1876 + vc4_dsi_connector_destroy(dsi->connector);
1877 + vc4_dsi_encoder_destroy(dsi->encoder);
1878 +
1879 + mipi_dsi_host_unregister(&dsi->dsi_host);
1880 +
1881 + if (!dsi->use_firmware_setup) {
1882 + clk_disable_unprepare(dsi->pll_phy_clock);
1883 + clk_disable_unprepare(dsi->escape_clock);
1884 + clk_disable_unprepare(dsi->pixel_clock);
1885 + }
1886 +
1887 + if (dsi->port == 1)
1888 + vc4->dsi1 = NULL;
1889 +}
1890 +
1891 +static const struct component_ops vc4_dsi_ops = {
1892 + .bind = vc4_dsi_bind,
1893 + .unbind = vc4_dsi_unbind,
1894 +};
1895 +
1896 +static int vc4_dsi_dev_probe(struct platform_device *pdev)
1897 +{
1898 + return component_add(&pdev->dev, &vc4_dsi_ops);
1899 +}
1900 +
1901 +static int vc4_dsi_dev_remove(struct platform_device *pdev)
1902 +{
1903 + component_del(&pdev->dev, &vc4_dsi_ops);
1904 + return 0;
1905 +}
1906 +
1907 +struct platform_driver vc4_dsi_driver = {
1908 + .probe = vc4_dsi_dev_probe,
1909 + .remove = vc4_dsi_dev_remove,
1910 + .driver = {
1911 + .name = "vc4_dsi",
1912 + .of_match_table = vc4_dsi_dt_match,
1913 + },
1914 +};
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