target/linux/brcm2708/patches-4.4/0452-drm-vc4-Make-pageflip-completion-handling-more-robus.patch

   1 From cb182bb6180c57b28636669a613861023fd8f03d Mon Sep 17 00:00:00 2001
   2 From: Mario Kleiner <mario.kleiner.de@gmail.com>
   3 Date: Wed, 18 May 2016 14:02:46 +0200
   4 Subject: [PATCH] drm/vc4: Make pageflip completion handling more robust.
   5
   6 Protect both the setup of the pageflip event and the
   7 latching of the new requested displaylist head pointer
   8 by the event lock, so we can't get into a situation
   9 where vc4_atomic_flush latches the new display list via
  10 HVS_WRITE, then immediately gets preempted before queueing
  11 the pageflip event, then the page-flip completes in hw and
  12 the vc4_crtc_handle_page_flip() runs and no-ops due to
  13 lack of a pending pageflip event, then vc4_atomic_flush
  14 continues and only then queues the pageflip event - after
  15 the page flip handling already no-oped. This would cause
  16 flip completion handling only at the next vblank - one
  17 frame too late.
  18
  19 In vc4_crtc_handle_page_flip() check the actual DL head
  20 pointer in SCALER_DISPLACTX against the requested pointer
  21 for page flip to make sure that the flip actually really
  22 completed in the current vblank and doesn't get deferred
  23 to the next one because the DL head pointer was written
  24 a bit too late into SCALER_DISPLISTX, after start of
  25 vblank, and missed the boat. This avoids handling a
  26 pageflip completion too early - one frame too early.
  27
  28 According to Eric, DL head pointer updates which were
  29 written into the HVS DISPLISTX reg get committed to hardware
  30 at the last pixel of active scanout. Our vblank interrupt
  31 handler, as triggered by PV_INT_VFP_START irq, gets to run
  32 earliest at the first pixel of HBLANK at the end of the
  33 last scanline of active scanout, ie. vblank irq handling
  34 runs at least 1 pixel duration after a potential pageflip
  35 completion happened in hardware.
  36
  37 This ordering of events in the hardware, together with the
  38 lock protection and SCALER_DISPLACTX sampling of this patch,
  39 guarantees that pageflip completion handling only runs at
  40 exactly the vblank irq of actual pageflip completion in all
  41 cases.
  42
  43 Background info from Eric about the relative timing of
  44 HVS, PV's and trigger points for interrupts, DL updates:
  45
  46 https://lists.freedesktop.org/archives/dri-devel/2016-May/107510.html
  47
  48 Tested on RPi 2B with hardware timing measurement equipment
  49 and shown to no longer complete flips too early or too late.
  50
  51 Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com>
  52 Reviewed-by: Eric Anholt <eric@anholt.net>
  53 (cherry picked from commit 56d1fe0979dc9b73c1c12ee07722ac380d42a0c4)
  54 ---
  55  drivers/gpu/drm/vc4/vc4_crtc.c | 28 ++++++++++++++++++----------
  56  drivers/gpu/drm/vc4/vc4_regs.h |  4 ++++
  57  2 files changed, 22 insertions(+), 10 deletions(-)
  58
  59 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  60 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  61 @@ -465,14 +465,6 @@ static void vc4_crtc_atomic_flush(struct
  62
  63         WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
  64
  65 -       HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
  66 -                 vc4_state->mm.start);
  67 -
  68 -       if (debug_dump_regs) {
  69 -               DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
  70 -               vc4_hvs_dump_state(dev);
  71 -       }
  72 -
  73         if (crtc->state->event) {
  74                 unsigned long flags;
  75
  76 @@ -482,8 +474,20 @@ static void vc4_crtc_atomic_flush(struct
  77
  78                 spin_lock_irqsave(&dev->event_lock, flags);
  79                 vc4_crtc->event = crtc->state->event;
  80 -               spin_unlock_irqrestore(&dev->event_lock, flags);
  81                 crtc->state->event = NULL;
  82 +
  83 +               HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
  84 +                         vc4_state->mm.start);
  85 +
  86 +               spin_unlock_irqrestore(&dev->event_lock, flags);
  87 +       } else {
  88 +               HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
  89 +                         vc4_state->mm.start);
  90 +       }
  91 +
  92 +       if (debug_dump_regs) {
  93 +               DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
  94 +               vc4_hvs_dump_state(dev);
  95         }
  96  }
  97
  98 @@ -509,10 +513,14 @@ static void vc4_crtc_handle_page_flip(st
  99  {
 100         struct drm_crtc *crtc = &vc4_crtc->base;
 101         struct drm_device *dev = crtc->dev;
 102 +       struct vc4_dev *vc4 = to_vc4_dev(dev);
 103 +       struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
 104 +       u32 chan = vc4_crtc->channel;
 105         unsigned long flags;
 106
 107         spin_lock_irqsave(&dev->event_lock, flags);
 108 -       if (vc4_crtc->event) {
 109 +       if (vc4_crtc->event &&
 110 +           (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
 111                 drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
 112                 vc4_crtc->event = NULL;
 113                 drm_crtc_vblank_put(crtc);
 114 --- a/drivers/gpu/drm/vc4/vc4_regs.h
 115 +++ b/drivers/gpu/drm/vc4/vc4_regs.h
 116 @@ -343,6 +343,10 @@
 117  #define SCALER_DISPLACT0                        0x00000030
 118  #define SCALER_DISPLACT1                        0x00000034
 119  #define SCALER_DISPLACT2                        0x00000038
 120 +#define SCALER_DISPLACTX(x)                    (SCALER_DISPLACT0 +     \
 121 +                                                (x) * (SCALER_DISPLACT1 - \
 122 +                                                       SCALER_DISPLACT0))
 123 +
 124  #define SCALER_DISPCTRL0                        0x00000040
 125  # define SCALER_DISPCTRLX_ENABLE               BIT(31)
 126  # define SCALER_DISPCTRLX_RESET                        BIT(30)