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generic: ar8216: group MIB counters and use two basic ones only by default
[openwrt/staging/dedeckeh.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
39
40 #include "ar8216.h"
41
42 extern const struct ar8xxx_chip ar8327_chip;
43 extern const struct ar8xxx_chip ar8337_chip;
44
45 #define MIB_DESC_BASIC(_s , _o, _n) \
46 { \
47 .size = (_s), \
48 .offset = (_o), \
49 .name = (_n), \
50 .type = AR8XXX_MIB_BASIC, \
51 }
52
53 #define MIB_DESC_EXT(_s , _o, _n) \
54 { \
55 .size = (_s), \
56 .offset = (_o), \
57 .name = (_n), \
58 .type = AR8XXX_MIB_EXTENDED, \
59 }
60
61 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
62 MIB_DESC_EXT(1, AR8216_STATS_RXBROAD, "RxBroad"),
63 MIB_DESC_EXT(1, AR8216_STATS_RXPAUSE, "RxPause"),
64 MIB_DESC_EXT(1, AR8216_STATS_RXMULTI, "RxMulti"),
65 MIB_DESC_EXT(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
66 MIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
67 MIB_DESC_EXT(1, AR8216_STATS_RXRUNT, "RxRunt"),
68 MIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
69 MIB_DESC_EXT(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
70 MIB_DESC_EXT(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
71 MIB_DESC_EXT(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
72 MIB_DESC_EXT(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
73 MIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
74 MIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
75 MIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
76 MIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
77 MIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
78 MIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
79 MIB_DESC_EXT(1, AR8216_STATS_FILTERED, "Filtered"),
80 MIB_DESC_EXT(1, AR8216_STATS_TXBROAD, "TxBroad"),
81 MIB_DESC_EXT(1, AR8216_STATS_TXPAUSE, "TxPause"),
82 MIB_DESC_EXT(1, AR8216_STATS_TXMULTI, "TxMulti"),
83 MIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
84 MIB_DESC_EXT(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
85 MIB_DESC_EXT(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
86 MIB_DESC_EXT(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
87 MIB_DESC_EXT(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
88 MIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
89 MIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
90 MIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
91 MIB_DESC_BASIC(2, AR8216_STATS_TXBYTE, "TxByte"),
92 MIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
93 MIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
94 MIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
95 MIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
96 MIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
97 MIB_DESC_EXT(1, AR8216_STATS_TXDEFER, "TxDefer"),
98 MIB_DESC_EXT(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
99 };
100
101 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
102 MIB_DESC_EXT(1, AR8236_STATS_RXBROAD, "RxBroad"),
103 MIB_DESC_EXT(1, AR8236_STATS_RXPAUSE, "RxPause"),
104 MIB_DESC_EXT(1, AR8236_STATS_RXMULTI, "RxMulti"),
105 MIB_DESC_EXT(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
106 MIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
107 MIB_DESC_EXT(1, AR8236_STATS_RXRUNT, "RxRunt"),
108 MIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
109 MIB_DESC_EXT(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
110 MIB_DESC_EXT(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
111 MIB_DESC_EXT(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
112 MIB_DESC_EXT(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
113 MIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
114 MIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
115 MIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
116 MIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
117 MIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
118 MIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
119 MIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
120 MIB_DESC_EXT(1, AR8236_STATS_FILTERED, "Filtered"),
121 MIB_DESC_EXT(1, AR8236_STATS_TXBROAD, "TxBroad"),
122 MIB_DESC_EXT(1, AR8236_STATS_TXPAUSE, "TxPause"),
123 MIB_DESC_EXT(1, AR8236_STATS_TXMULTI, "TxMulti"),
124 MIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
125 MIB_DESC_EXT(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
126 MIB_DESC_EXT(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
127 MIB_DESC_EXT(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
128 MIB_DESC_EXT(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
129 MIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
130 MIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
131 MIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
132 MIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
133 MIB_DESC_BASIC(2, AR8236_STATS_TXBYTE, "TxByte"),
134 MIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
135 MIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
136 MIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
137 MIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
138 MIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
139 MIB_DESC_EXT(1, AR8236_STATS_TXDEFER, "TxDefer"),
140 MIB_DESC_EXT(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
141 };
142
143 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
144 static LIST_HEAD(ar8xxx_dev_list);
145
146 static void
147 ar8xxx_mib_start(struct ar8xxx_priv *priv);
148 static void
149 ar8xxx_mib_stop(struct ar8xxx_priv *priv);
150
151 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
152 static int
153 ar8xxx_phy_poll_reset(struct mii_bus *bus)
154 {
155 unsigned int sleep_msecs = 20;
156 int ret, elapsed, i;
157
158 for (elapsed = sleep_msecs; elapsed <= 600;
159 elapsed += sleep_msecs) {
160 msleep(sleep_msecs);
161 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
162 ret = mdiobus_read(bus, i, MII_BMCR);
163 if (ret < 0)
164 return ret;
165 if (ret & BMCR_RESET)
166 break;
167 if (i == AR8XXX_NUM_PHYS - 1) {
168 usleep_range(1000, 2000);
169 return 0;
170 }
171 }
172 }
173 return -ETIMEDOUT;
174 }
175
176 static int
177 ar8xxx_phy_check_aneg(struct phy_device *phydev)
178 {
179 int ret;
180
181 if (phydev->autoneg != AUTONEG_ENABLE)
182 return 0;
183 /*
184 * BMCR_ANENABLE might have been cleared
185 * by phy_init_hw in certain kernel versions
186 * therefore check for it
187 */
188 ret = phy_read(phydev, MII_BMCR);
189 if (ret < 0)
190 return ret;
191 if (ret & BMCR_ANENABLE)
192 return 0;
193
194 dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
195 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
196 return phy_write(phydev, MII_BMCR, ret);
197 }
198
199 void
200 ar8xxx_phy_init(struct ar8xxx_priv *priv)
201 {
202 int i;
203 struct mii_bus *bus;
204
205 bus = priv->sw_mii_bus ?: priv->mii_bus;
206 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
207 if (priv->chip->phy_fixup)
208 priv->chip->phy_fixup(priv, i);
209
210 /* initialize the port itself */
211 mdiobus_write(bus, i, MII_ADVERTISE,
212 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
213 if (ar8xxx_has_gige(priv))
214 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
215 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
216 }
217
218 ar8xxx_phy_poll_reset(bus);
219 }
220
221 u32
222 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
223 {
224 struct mii_bus *bus = priv->mii_bus;
225 u16 lo, hi;
226
227 lo = bus->read(bus, phy_id, regnum);
228 hi = bus->read(bus, phy_id, regnum + 1);
229
230 return (hi << 16) | lo;
231 }
232
233 void
234 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
235 {
236 struct mii_bus *bus = priv->mii_bus;
237 u16 lo, hi;
238
239 lo = val & 0xffff;
240 hi = (u16) (val >> 16);
241
242 if (priv->chip->mii_lo_first)
243 {
244 bus->write(bus, phy_id, regnum, lo);
245 bus->write(bus, phy_id, regnum + 1, hi);
246 } else {
247 bus->write(bus, phy_id, regnum + 1, hi);
248 bus->write(bus, phy_id, regnum, lo);
249 }
250 }
251
252 u32
253 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
254 {
255 struct mii_bus *bus = priv->mii_bus;
256 u16 r1, r2, page;
257 u32 val;
258
259 split_addr((u32) reg, &r1, &r2, &page);
260
261 mutex_lock(&bus->mdio_lock);
262
263 bus->write(bus, 0x18, 0, page);
264 wait_for_page_switch();
265 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
266
267 mutex_unlock(&bus->mdio_lock);
268
269 return val;
270 }
271
272 void
273 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
274 {
275 struct mii_bus *bus = priv->mii_bus;
276 u16 r1, r2, page;
277
278 split_addr((u32) reg, &r1, &r2, &page);
279
280 mutex_lock(&bus->mdio_lock);
281
282 bus->write(bus, 0x18, 0, page);
283 wait_for_page_switch();
284 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
285
286 mutex_unlock(&bus->mdio_lock);
287 }
288
289 u32
290 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
291 {
292 struct mii_bus *bus = priv->mii_bus;
293 u16 r1, r2, page;
294 u32 ret;
295
296 split_addr((u32) reg, &r1, &r2, &page);
297
298 mutex_lock(&bus->mdio_lock);
299
300 bus->write(bus, 0x18, 0, page);
301 wait_for_page_switch();
302
303 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
304 ret &= ~mask;
305 ret |= val;
306 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
307
308 mutex_unlock(&bus->mdio_lock);
309
310 return ret;
311 }
312 void
313 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
314 u16 dbg_addr, u16 *dbg_data)
315 {
316 struct mii_bus *bus = priv->mii_bus;
317
318 mutex_lock(&bus->mdio_lock);
319 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
320 *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
321 mutex_unlock(&bus->mdio_lock);
322 }
323
324 void
325 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
326 u16 dbg_addr, u16 dbg_data)
327 {
328 struct mii_bus *bus = priv->mii_bus;
329
330 mutex_lock(&bus->mdio_lock);
331 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
332 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
333 mutex_unlock(&bus->mdio_lock);
334 }
335
336 static inline void
337 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
338 {
339 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
340 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
341 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
342 }
343
344 void
345 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
346 {
347 struct mii_bus *bus = priv->mii_bus;
348
349 mutex_lock(&bus->mdio_lock);
350 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
351 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
352 mutex_unlock(&bus->mdio_lock);
353 }
354
355 u16
356 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
357 {
358 struct mii_bus *bus = priv->mii_bus;
359 u16 data;
360
361 mutex_lock(&bus->mdio_lock);
362 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
363 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
364 mutex_unlock(&bus->mdio_lock);
365
366 return data;
367 }
368
369 static int
370 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
371 unsigned timeout)
372 {
373 int i;
374
375 for (i = 0; i < timeout; i++) {
376 u32 t;
377
378 t = ar8xxx_read(priv, reg);
379 if ((t & mask) == val)
380 return 0;
381
382 usleep_range(1000, 2000);
383 cond_resched();
384 }
385
386 return -ETIMEDOUT;
387 }
388
389 static int
390 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
391 {
392 unsigned mib_func = priv->chip->mib_func;
393 int ret;
394
395 lockdep_assert_held(&priv->mib_lock);
396
397 /* Capture the hardware statistics for all ports */
398 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
399
400 /* Wait for the capturing to complete. */
401 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
402 if (ret)
403 goto out;
404
405 ret = 0;
406
407 out:
408 return ret;
409 }
410
411 static int
412 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
413 {
414 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
415 }
416
417 static int
418 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
419 {
420 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
421 }
422
423 static void
424 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
425 {
426 unsigned int base;
427 u64 *mib_stats;
428 int i;
429
430 WARN_ON(port >= priv->dev.ports);
431
432 lockdep_assert_held(&priv->mib_lock);
433
434 base = priv->chip->reg_port_stats_start +
435 priv->chip->reg_port_stats_length * port;
436
437 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
438 for (i = 0; i < priv->chip->num_mibs; i++) {
439 const struct ar8xxx_mib_desc *mib;
440 u64 t;
441
442 mib = &priv->chip->mib_decs[i];
443 if (mib->type > priv->mib_type)
444 continue;
445 t = ar8xxx_read(priv, base + mib->offset);
446 if (mib->size == 2) {
447 u64 hi;
448
449 hi = ar8xxx_read(priv, base + mib->offset + 4);
450 t |= hi << 32;
451 }
452
453 if (flush)
454 mib_stats[i] = 0;
455 else
456 mib_stats[i] += t;
457 cond_resched();
458 }
459 }
460
461 static void
462 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
463 struct switch_port_link *link)
464 {
465 u32 status;
466 u32 speed;
467
468 memset(link, '\0', sizeof(*link));
469
470 status = priv->chip->read_port_status(priv, port);
471
472 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
473 if (link->aneg) {
474 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
475 } else {
476 link->link = true;
477
478 if (priv->get_port_link) {
479 int err;
480
481 err = priv->get_port_link(port);
482 if (err >= 0)
483 link->link = !!err;
484 }
485 }
486
487 if (!link->link)
488 return;
489
490 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
491 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
492 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
493
494 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
495 link->eee = priv->chip->read_port_eee_status(priv, port);
496
497 speed = (status & AR8216_PORT_STATUS_SPEED) >>
498 AR8216_PORT_STATUS_SPEED_S;
499
500 switch (speed) {
501 case AR8216_PORT_SPEED_10M:
502 link->speed = SWITCH_PORT_SPEED_10;
503 break;
504 case AR8216_PORT_SPEED_100M:
505 link->speed = SWITCH_PORT_SPEED_100;
506 break;
507 case AR8216_PORT_SPEED_1000M:
508 link->speed = SWITCH_PORT_SPEED_1000;
509 break;
510 default:
511 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
512 break;
513 }
514 }
515
516 static struct sk_buff *
517 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
518 {
519 struct ar8xxx_priv *priv = dev->phy_ptr;
520 unsigned char *buf;
521
522 if (unlikely(!priv))
523 goto error;
524
525 if (!priv->vlan)
526 goto send;
527
528 if (unlikely(skb_headroom(skb) < 2)) {
529 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
530 goto error;
531 }
532
533 buf = skb_push(skb, 2);
534 buf[0] = 0x10;
535 buf[1] = 0x80;
536
537 send:
538 return skb;
539
540 error:
541 dev_kfree_skb_any(skb);
542 return NULL;
543 }
544
545 static void
546 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
547 {
548 struct ar8xxx_priv *priv;
549 unsigned char *buf;
550 int port, vlan;
551
552 priv = dev->phy_ptr;
553 if (!priv)
554 return;
555
556 /* don't strip the header if vlan mode is disabled */
557 if (!priv->vlan)
558 return;
559
560 /* strip header, get vlan id */
561 buf = skb->data;
562 skb_pull(skb, 2);
563
564 /* check for vlan header presence */
565 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
566 return;
567
568 port = buf[0] & 0x7;
569
570 /* no need to fix up packets coming from a tagged source */
571 if (priv->vlan_tagged & (1 << port))
572 return;
573
574 /* lookup port vid from local table, the switch passes an invalid vlan id */
575 vlan = priv->vlan_id[priv->pvid[port]];
576
577 buf[14 + 2] &= 0xf0;
578 buf[14 + 2] |= vlan >> 8;
579 buf[15 + 2] = vlan & 0xff;
580 }
581
582 int
583 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
584 {
585 int timeout = 20;
586 u32 t = 0;
587
588 while (1) {
589 t = ar8xxx_read(priv, reg);
590 if ((t & mask) == val)
591 return 0;
592
593 if (timeout-- <= 0)
594 break;
595
596 udelay(10);
597 cond_resched();
598 }
599
600 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
601 (unsigned int) reg, t, mask, val);
602 return -ETIMEDOUT;
603 }
604
605 static void
606 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
607 {
608 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
609 return;
610 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
611 val &= AR8216_VTUDATA_MEMBER;
612 val |= AR8216_VTUDATA_VALID;
613 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
614 }
615 op |= AR8216_VTU_ACTIVE;
616 ar8xxx_write(priv, AR8216_REG_VTU, op);
617 }
618
619 static void
620 ar8216_vtu_flush(struct ar8xxx_priv *priv)
621 {
622 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
623 }
624
625 static void
626 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
627 {
628 u32 op;
629
630 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
631 ar8216_vtu_op(priv, op, port_mask);
632 }
633
634 static int
635 ar8216_atu_flush(struct ar8xxx_priv *priv)
636 {
637 int ret;
638
639 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
640 if (!ret)
641 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
642 AR8216_ATU_ACTIVE);
643
644 return ret;
645 }
646
647 static int
648 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
649 {
650 u32 t;
651 int ret;
652
653 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
654 if (!ret) {
655 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
656 t |= AR8216_ATU_ACTIVE;
657 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
658 }
659
660 return ret;
661 }
662
663 static u32
664 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
665 {
666 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
667 }
668
669 static void
670 __ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members,
671 bool ath_hdr_en)
672 {
673 u32 header;
674 u32 egress, ingress;
675 u32 pvid;
676
677 if (priv->vlan) {
678 pvid = priv->vlan_id[priv->pvid[port]];
679 if (priv->vlan_tagged & (1 << port))
680 egress = AR8216_OUT_ADD_VLAN;
681 else
682 egress = AR8216_OUT_STRIP_VLAN;
683 ingress = AR8216_IN_SECURE;
684 } else {
685 pvid = port;
686 egress = AR8216_OUT_KEEP;
687 ingress = AR8216_IN_PORT_ONLY;
688 }
689
690 header = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0;
691
692 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
693 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
694 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
695 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
696 AR8216_PORT_CTRL_LEARN | header |
697 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
698 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
699
700 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
701 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
702 AR8216_PORT_VLAN_DEFAULT_ID,
703 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
704 (ingress << AR8216_PORT_VLAN_MODE_S) |
705 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
706 }
707
708 static void
709 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
710 {
711 return __ar8216_setup_port(priv, port, members,
712 chip_is_ar8216(priv) && priv->vlan &&
713 port == AR8216_PORT_CPU);
714 }
715
716 static int
717 ar8216_hw_init(struct ar8xxx_priv *priv)
718 {
719 if (priv->initialized)
720 return 0;
721
722 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
723 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
724
725 ar8xxx_phy_init(priv);
726
727 priv->initialized = true;
728 return 0;
729 }
730
731 static void
732 ar8216_init_globals(struct ar8xxx_priv *priv)
733 {
734 /* standard atheros magic */
735 ar8xxx_write(priv, 0x38, 0xc000050e);
736
737 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
738 AR8216_GCTRL_MTU, 1518 + 8 + 2);
739 }
740
741 static void
742 __ar8216_init_port(struct ar8xxx_priv *priv, int port,
743 bool cpu_ge, bool flow_en)
744 {
745 /* Enable port learning and tx */
746 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
747 AR8216_PORT_CTRL_LEARN |
748 (4 << AR8216_PORT_CTRL_STATE_S));
749
750 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
751
752 if (port == AR8216_PORT_CPU) {
753 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
754 AR8216_PORT_STATUS_LINK_UP |
755 (cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
756 AR8216_PORT_STATUS_TXMAC |
757 AR8216_PORT_STATUS_RXMAC |
758 (flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |
759 (flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |
760 AR8216_PORT_STATUS_DUPLEX);
761 } else {
762 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
763 AR8216_PORT_STATUS_LINK_AUTO);
764 }
765 }
766
767 static void
768 ar8216_init_port(struct ar8xxx_priv *priv, int port)
769 {
770 __ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
771 chip_is_ar8316(priv));
772 }
773
774 static void
775 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
776 {
777 int timeout = 20;
778
779 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
780 udelay(10);
781 cond_resched();
782 }
783
784 if (!timeout)
785 pr_err("ar8216: timeout waiting for atu to become ready\n");
786 }
787
788 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
789 struct arl_entry *a, u32 *status, enum arl_op op)
790 {
791 struct mii_bus *bus = priv->mii_bus;
792 u16 r2, page;
793 u16 r1_func0, r1_func1, r1_func2;
794 u32 t, val0, val1, val2;
795
796 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
797 r2 |= 0x10;
798
799 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
800 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
801
802 switch (op) {
803 case AR8XXX_ARL_INITIALIZE:
804 /* all ATU registers are on the same page
805 * therefore set page only once
806 */
807 bus->write(bus, 0x18, 0, page);
808 wait_for_page_switch();
809
810 ar8216_wait_atu_ready(priv, r2, r1_func0);
811
812 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
813 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
814 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
815 break;
816 case AR8XXX_ARL_GET_NEXT:
817 t = ar8xxx_mii_read32(priv, r2, r1_func0);
818 t |= AR8216_ATU_ACTIVE;
819 ar8xxx_mii_write32(priv, r2, r1_func0, t);
820 ar8216_wait_atu_ready(priv, r2, r1_func0);
821
822 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
823 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
824 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
825
826 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
827 if (!*status)
828 break;
829
830 a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
831 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
832 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
833 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
834 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
835 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
836 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
837 break;
838 }
839 }
840
841 static int
842 ar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum)
843 {
844 u32 t, val = 0xffff;
845 int err;
846
847 if (addr >= AR8216_NUM_PORTS)
848 return 0xffff;
849 t = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
850 (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
851 AR8216_MDIO_CTRL_MASTER_EN |
852 AR8216_MDIO_CTRL_BUSY |
853 AR8216_MDIO_CTRL_CMD_READ;
854
855 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
856 err = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
857 AR8216_MDIO_CTRL_BUSY, 0, 5);
858 if (!err)
859 val = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL);
860
861 return val & AR8216_MDIO_CTRL_DATA_M;
862 }
863
864 static int
865 ar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val)
866 {
867 u32 t;
868 int ret;
869
870 if (addr >= AR8216_NUM_PORTS)
871 return -EINVAL;
872
873 t = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
874 (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
875 AR8216_MDIO_CTRL_MASTER_EN |
876 AR8216_MDIO_CTRL_BUSY |
877 AR8216_MDIO_CTRL_CMD_WRITE |
878 val;
879
880 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
881 ret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
882 AR8216_MDIO_CTRL_BUSY, 0, 5);
883
884 return ret;
885 }
886
887 static int
888 ar8229_hw_init(struct ar8xxx_priv *priv)
889 {
890 int phy_if_mode;
891
892 if (priv->initialized)
893 return 0;
894
895 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
896 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
897
898 phy_if_mode = of_get_phy_mode(priv->pdev->of_node);
899
900 if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
901 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
902 AR8229_OPER_MODE0_MAC_GMII_EN);
903 } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
904 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
905 AR8229_OPER_MODE0_PHY_MII_EN);
906 } else {
907 pr_err("ar8229: unsupported mii mode\n");
908 return -EINVAL;
909 }
910
911 if (priv->port4_phy) {
912 ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
913 AR8229_REG_OPER_MODE1_PHY4_MII_EN);
914 /* disable port5 to prevent mii conflict */
915 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
916 }
917
918 ar8xxx_phy_init(priv);
919
920 priv->initialized = true;
921 return 0;
922 }
923
924 static void
925 ar8229_init_globals(struct ar8xxx_priv *priv)
926 {
927
928 /* Enable CPU port, and disable mirror port */
929 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
930 AR8216_GLOBAL_CPUPORT_EN |
931 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
932
933 /* Setup TAG priority mapping */
934 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
935
936 /* Enable aging, MAC replacing */
937 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
938 0x2b /* 5 min age time */ |
939 AR8216_ATU_CTRL_AGE_EN |
940 AR8216_ATU_CTRL_LEARN_CHANGE);
941
942 /* Enable ARP frame acknowledge */
943 ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
944 AR8229_QM_CTRL_ARP_EN);
945
946 /* Enable Broadcast/Multicast frames transmitted to the CPU */
947 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
948 AR8229_FLOOD_MASK_BC_DP(0) |
949 AR8229_FLOOD_MASK_MC_DP(0));
950
951 /* setup MTU */
952 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
953 AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);
954
955 /* Enable MIB counters */
956 ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,
957 AR8236_MIB_EN);
958
959 /* setup Service TAG */
960 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
961 }
962
963 static void
964 ar8229_init_port(struct ar8xxx_priv *priv, int port)
965 {
966 __ar8216_init_port(priv, port, true, true);
967 }
968
969
970 static int
971 ar7240sw_hw_init(struct ar8xxx_priv *priv)
972 {
973 if (priv->initialized)
974 return 0;
975
976 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
977 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
978
979 priv->port4_phy = 1;
980 /* disable port5 to prevent mii conflict */
981 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
982
983 ar8xxx_phy_init(priv);
984
985 priv->initialized = true;
986 return 0;
987 }
988
989 static void
990 ar7240sw_init_globals(struct ar8xxx_priv *priv)
991 {
992
993 /* Enable CPU port, and disable mirror port */
994 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
995 AR8216_GLOBAL_CPUPORT_EN |
996 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
997
998 /* Setup TAG priority mapping */
999 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
1000
1001 /* Enable ARP frame acknowledge, aging, MAC replacing */
1002 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
1003 AR8216_ATU_CTRL_RESERVED |
1004 0x2b /* 5 min age time */ |
1005 AR8216_ATU_CTRL_AGE_EN |
1006 AR8216_ATU_CTRL_ARP_EN |
1007 AR8216_ATU_CTRL_LEARN_CHANGE);
1008
1009 /* Enable Broadcast frames transmitted to the CPU */
1010 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
1011 AR8236_FM_CPU_BROADCAST_EN);
1012
1013 /* setup MTU */
1014 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1015 AR8216_GCTRL_MTU,
1016 AR8216_GCTRL_MTU);
1017
1018 /* setup Service TAG */
1019 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
1020 }
1021
1022 static void
1023 ar7240sw_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1024 {
1025 return __ar8216_setup_port(priv, port, members, false);
1026 }
1027
1028 static void
1029 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1030 {
1031 u32 egress, ingress;
1032 u32 pvid;
1033
1034 if (priv->vlan) {
1035 pvid = priv->vlan_id[priv->pvid[port]];
1036 if (priv->vlan_tagged & (1 << port))
1037 egress = AR8216_OUT_ADD_VLAN;
1038 else
1039 egress = AR8216_OUT_STRIP_VLAN;
1040 ingress = AR8216_IN_SECURE;
1041 } else {
1042 pvid = port;
1043 egress = AR8216_OUT_KEEP;
1044 ingress = AR8216_IN_PORT_ONLY;
1045 }
1046
1047 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1048 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
1049 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
1050 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
1051 AR8216_PORT_CTRL_LEARN |
1052 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
1053 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
1054
1055 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
1056 AR8236_PORT_VLAN_DEFAULT_ID,
1057 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
1058
1059 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
1060 AR8236_PORT_VLAN2_VLAN_MODE |
1061 AR8236_PORT_VLAN2_MEMBER,
1062 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
1063 (members << AR8236_PORT_VLAN2_MEMBER_S));
1064 }
1065
1066 static void
1067 ar8236_init_globals(struct ar8xxx_priv *priv)
1068 {
1069 /* enable jumbo frames */
1070 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1071 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1072
1073 /* enable cpu port to receive arp frames */
1074 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
1075 AR8236_ATU_CTRL_RES);
1076
1077 /* enable cpu port to receive multicast and broadcast frames */
1078 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
1079 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
1080
1081 /* Enable MIB counters */
1082 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1083 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1084 AR8236_MIB_EN);
1085 }
1086
1087 static int
1088 ar8316_hw_init(struct ar8xxx_priv *priv)
1089 {
1090 u32 val, newval;
1091
1092 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
1093
1094 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1095 if (priv->port4_phy) {
1096 /* value taken from Ubiquiti RouterStation Pro */
1097 newval = 0x81461bea;
1098 pr_info("ar8316: Using port 4 as PHY\n");
1099 } else {
1100 newval = 0x01261be2;
1101 pr_info("ar8316: Using port 4 as switch port\n");
1102 }
1103 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
1104 /* value taken from AVM Fritz!Box 7390 sources */
1105 newval = 0x010e5b71;
1106 } else {
1107 /* no known value for phy interface */
1108 pr_err("ar8316: unsupported mii mode: %d.\n",
1109 priv->phy->interface);
1110 return -EINVAL;
1111 }
1112
1113 if (val == newval)
1114 goto out;
1115
1116 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
1117
1118 if (priv->port4_phy &&
1119 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1120 /* work around for phy4 rgmii mode */
1121 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1122 /* rx delay */
1123 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1124 /* tx delay */
1125 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1126 msleep(1000);
1127 }
1128
1129 ar8xxx_phy_init(priv);
1130
1131 out:
1132 priv->initialized = true;
1133 return 0;
1134 }
1135
1136 static void
1137 ar8316_init_globals(struct ar8xxx_priv *priv)
1138 {
1139 /* standard atheros magic */
1140 ar8xxx_write(priv, 0x38, 0xc000050e);
1141
1142 /* enable cpu port to receive multicast and broadcast frames */
1143 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1144
1145 /* enable jumbo frames */
1146 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1147 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1148
1149 /* Enable MIB counters */
1150 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1151 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1152 AR8236_MIB_EN);
1153 }
1154
1155 int
1156 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1157 struct switch_val *val)
1158 {
1159 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1160 priv->vlan = !!val->value.i;
1161 return 0;
1162 }
1163
1164 int
1165 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1166 struct switch_val *val)
1167 {
1168 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1169 val->value.i = priv->vlan;
1170 return 0;
1171 }
1172
1173
1174 int
1175 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1176 {
1177 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1178
1179 /* make sure no invalid PVIDs get set */
1180
1181 if (vlan < 0 || vlan >= dev->vlans ||
1182 port < 0 || port >= AR8X16_MAX_PORTS)
1183 return -EINVAL;
1184
1185 priv->pvid[port] = vlan;
1186 return 0;
1187 }
1188
1189 int
1190 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1191 {
1192 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1193
1194 if (port < 0 || port >= AR8X16_MAX_PORTS)
1195 return -EINVAL;
1196
1197 *vlan = priv->pvid[port];
1198 return 0;
1199 }
1200
1201 static int
1202 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1203 struct switch_val *val)
1204 {
1205 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1206
1207 if (val->port_vlan >= AR8X16_MAX_VLANS)
1208 return -EINVAL;
1209
1210 priv->vlan_id[val->port_vlan] = val->value.i;
1211 return 0;
1212 }
1213
1214 static int
1215 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1216 struct switch_val *val)
1217 {
1218 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1219 val->value.i = priv->vlan_id[val->port_vlan];
1220 return 0;
1221 }
1222
1223 int
1224 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1225 struct switch_port_link *link)
1226 {
1227 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1228
1229 ar8216_read_port_link(priv, port, link);
1230 return 0;
1231 }
1232
1233 static int
1234 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1235 {
1236 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1237 u8 ports;
1238 int i;
1239
1240 if (val->port_vlan >= AR8X16_MAX_VLANS)
1241 return -EINVAL;
1242
1243 ports = priv->vlan_table[val->port_vlan];
1244 val->len = 0;
1245 for (i = 0; i < dev->ports; i++) {
1246 struct switch_port *p;
1247
1248 if (!(ports & (1 << i)))
1249 continue;
1250
1251 p = &val->value.ports[val->len++];
1252 p->id = i;
1253 if (priv->vlan_tagged & (1 << i))
1254 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1255 else
1256 p->flags = 0;
1257 }
1258 return 0;
1259 }
1260
1261 static int
1262 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1263 {
1264 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1265 u8 *vt = &priv->vlan_table[val->port_vlan];
1266 int i, j;
1267
1268 *vt = 0;
1269 for (i = 0; i < val->len; i++) {
1270 struct switch_port *p = &val->value.ports[i];
1271
1272 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1273 priv->vlan_tagged |= (1 << p->id);
1274 } else {
1275 priv->vlan_tagged &= ~(1 << p->id);
1276 priv->pvid[p->id] = val->port_vlan;
1277
1278 /* make sure that an untagged port does not
1279 * appear in other vlans */
1280 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1281 if (j == val->port_vlan)
1282 continue;
1283 priv->vlan_table[j] &= ~(1 << p->id);
1284 }
1285 }
1286
1287 *vt |= 1 << p->id;
1288 }
1289 return 0;
1290 }
1291
1292 static void
1293 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1294 {
1295 int port;
1296
1297 /* reset all mirror registers */
1298 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1299 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1300 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1301 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1302 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1303 AR8216_PORT_CTRL_MIRROR_RX);
1304
1305 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1306 AR8216_PORT_CTRL_MIRROR_TX);
1307 }
1308
1309 /* now enable mirroring if necessary */
1310 if (priv->source_port >= AR8216_NUM_PORTS ||
1311 priv->monitor_port >= AR8216_NUM_PORTS ||
1312 priv->source_port == priv->monitor_port) {
1313 return;
1314 }
1315
1316 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1317 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1318 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1319
1320 if (priv->mirror_rx)
1321 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1322 AR8216_PORT_CTRL_MIRROR_RX);
1323
1324 if (priv->mirror_tx)
1325 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1326 AR8216_PORT_CTRL_MIRROR_TX);
1327 }
1328
1329 static inline u32
1330 ar8xxx_age_time_val(int age_time)
1331 {
1332 return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1333 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1334 }
1335
1336 static inline void
1337 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1338 {
1339 u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1340 ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1341 }
1342
1343 int
1344 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1345 {
1346 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1347 const struct ar8xxx_chip *chip = priv->chip;
1348 u8 portmask[AR8X16_MAX_PORTS];
1349 int i, j;
1350
1351 mutex_lock(&priv->reg_mutex);
1352 /* flush all vlan translation unit entries */
1353 priv->chip->vtu_flush(priv);
1354
1355 memset(portmask, 0, sizeof(portmask));
1356 if (!priv->init) {
1357 /* calculate the port destination masks and load vlans
1358 * into the vlan translation unit */
1359 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1360 u8 vp = priv->vlan_table[j];
1361
1362 if (!vp)
1363 continue;
1364
1365 for (i = 0; i < dev->ports; i++) {
1366 u8 mask = (1 << i);
1367 if (vp & mask)
1368 portmask[i] |= vp & ~mask;
1369 }
1370
1371 chip->vtu_load_vlan(priv, priv->vlan_id[j],
1372 priv->vlan_table[j]);
1373 }
1374 } else {
1375 /* vlan disabled:
1376 * isolate all ports, but connect them to the cpu port */
1377 for (i = 0; i < dev->ports; i++) {
1378 if (i == AR8216_PORT_CPU)
1379 continue;
1380
1381 portmask[i] = 1 << AR8216_PORT_CPU;
1382 portmask[AR8216_PORT_CPU] |= (1 << i);
1383 }
1384 }
1385
1386 /* update the port destination mask registers and tag settings */
1387 for (i = 0; i < dev->ports; i++) {
1388 chip->setup_port(priv, i, portmask[i]);
1389 }
1390
1391 chip->set_mirror_regs(priv);
1392
1393 /* set age time */
1394 if (chip->reg_arl_ctrl)
1395 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1396
1397 mutex_unlock(&priv->reg_mutex);
1398 return 0;
1399 }
1400
1401 int
1402 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1403 {
1404 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1405 const struct ar8xxx_chip *chip = priv->chip;
1406 int i;
1407
1408 mutex_lock(&priv->reg_mutex);
1409 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1410 offsetof(struct ar8xxx_priv, vlan));
1411
1412 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1413 priv->vlan_id[i] = i;
1414
1415 /* Configure all ports */
1416 for (i = 0; i < dev->ports; i++)
1417 chip->init_port(priv, i);
1418
1419 priv->mirror_rx = false;
1420 priv->mirror_tx = false;
1421 priv->source_port = 0;
1422 priv->monitor_port = 0;
1423 priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1424
1425 chip->init_globals(priv);
1426 chip->atu_flush(priv);
1427
1428 mutex_unlock(&priv->reg_mutex);
1429
1430 return chip->sw_hw_apply(dev);
1431 }
1432
1433 int
1434 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1435 const struct switch_attr *attr,
1436 struct switch_val *val)
1437 {
1438 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1439 unsigned int len;
1440 int ret;
1441
1442 if (!ar8xxx_has_mib_counters(priv))
1443 return -EOPNOTSUPP;
1444
1445 mutex_lock(&priv->mib_lock);
1446
1447 len = priv->dev.ports * priv->chip->num_mibs *
1448 sizeof(*priv->mib_stats);
1449 memset(priv->mib_stats, '\0', len);
1450 ret = ar8xxx_mib_flush(priv);
1451 if (ret)
1452 goto unlock;
1453
1454 ret = 0;
1455
1456 unlock:
1457 mutex_unlock(&priv->mib_lock);
1458 return ret;
1459 }
1460
1461 int
1462 ar8xxx_sw_set_mib_poll_interval(struct switch_dev *dev,
1463 const struct switch_attr *attr,
1464 struct switch_val *val)
1465 {
1466 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1467
1468 if (!ar8xxx_has_mib_counters(priv))
1469 return -EOPNOTSUPP;
1470
1471 ar8xxx_mib_stop(priv);
1472 priv->mib_poll_interval = val->value.i;
1473 ar8xxx_mib_start(priv);
1474
1475 return 0;
1476 }
1477
1478 int
1479 ar8xxx_sw_get_mib_poll_interval(struct switch_dev *dev,
1480 const struct switch_attr *attr,
1481 struct switch_val *val)
1482 {
1483 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1484
1485 if (!ar8xxx_has_mib_counters(priv))
1486 return -EOPNOTSUPP;
1487 val->value.i = priv->mib_poll_interval;
1488 return 0;
1489 }
1490
1491 int
1492 ar8xxx_sw_set_mib_type(struct switch_dev *dev,
1493 const struct switch_attr *attr,
1494 struct switch_val *val)
1495 {
1496 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1497
1498 if (!ar8xxx_has_mib_counters(priv))
1499 return -EOPNOTSUPP;
1500 priv->mib_type = val->value.i;
1501 return 0;
1502 }
1503
1504 int
1505 ar8xxx_sw_get_mib_type(struct switch_dev *dev,
1506 const struct switch_attr *attr,
1507 struct switch_val *val)
1508 {
1509 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1510
1511 if (!ar8xxx_has_mib_counters(priv))
1512 return -EOPNOTSUPP;
1513 val->value.i = priv->mib_type;
1514 return 0;
1515 }
1516
1517 int
1518 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1519 const struct switch_attr *attr,
1520 struct switch_val *val)
1521 {
1522 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1523
1524 mutex_lock(&priv->reg_mutex);
1525 priv->mirror_rx = !!val->value.i;
1526 priv->chip->set_mirror_regs(priv);
1527 mutex_unlock(&priv->reg_mutex);
1528
1529 return 0;
1530 }
1531
1532 int
1533 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1534 const struct switch_attr *attr,
1535 struct switch_val *val)
1536 {
1537 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1538 val->value.i = priv->mirror_rx;
1539 return 0;
1540 }
1541
1542 int
1543 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1544 const struct switch_attr *attr,
1545 struct switch_val *val)
1546 {
1547 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1548
1549 mutex_lock(&priv->reg_mutex);
1550 priv->mirror_tx = !!val->value.i;
1551 priv->chip->set_mirror_regs(priv);
1552 mutex_unlock(&priv->reg_mutex);
1553
1554 return 0;
1555 }
1556
1557 int
1558 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1559 const struct switch_attr *attr,
1560 struct switch_val *val)
1561 {
1562 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1563 val->value.i = priv->mirror_tx;
1564 return 0;
1565 }
1566
1567 int
1568 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1569 const struct switch_attr *attr,
1570 struct switch_val *val)
1571 {
1572 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1573
1574 mutex_lock(&priv->reg_mutex);
1575 priv->monitor_port = val->value.i;
1576 priv->chip->set_mirror_regs(priv);
1577 mutex_unlock(&priv->reg_mutex);
1578
1579 return 0;
1580 }
1581
1582 int
1583 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1584 const struct switch_attr *attr,
1585 struct switch_val *val)
1586 {
1587 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1588 val->value.i = priv->monitor_port;
1589 return 0;
1590 }
1591
1592 int
1593 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1594 const struct switch_attr *attr,
1595 struct switch_val *val)
1596 {
1597 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1598
1599 mutex_lock(&priv->reg_mutex);
1600 priv->source_port = val->value.i;
1601 priv->chip->set_mirror_regs(priv);
1602 mutex_unlock(&priv->reg_mutex);
1603
1604 return 0;
1605 }
1606
1607 int
1608 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1609 const struct switch_attr *attr,
1610 struct switch_val *val)
1611 {
1612 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1613 val->value.i = priv->source_port;
1614 return 0;
1615 }
1616
1617 int
1618 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1619 const struct switch_attr *attr,
1620 struct switch_val *val)
1621 {
1622 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1623 int port;
1624 int ret;
1625
1626 if (!ar8xxx_has_mib_counters(priv))
1627 return -EOPNOTSUPP;
1628
1629 port = val->port_vlan;
1630 if (port >= dev->ports)
1631 return -EINVAL;
1632
1633 mutex_lock(&priv->mib_lock);
1634 ret = ar8xxx_mib_capture(priv);
1635 if (ret)
1636 goto unlock;
1637
1638 ar8xxx_mib_fetch_port_stat(priv, port, true);
1639
1640 ret = 0;
1641
1642 unlock:
1643 mutex_unlock(&priv->mib_lock);
1644 return ret;
1645 }
1646
1647 static void
1648 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1649 {
1650 unsigned long b;
1651 const char *unit;
1652
1653 if (byte >= 0x40000000) { /* 1 GiB */
1654 b = byte * 10 / 0x40000000;
1655 unit = "GiB";
1656 } else if (byte >= 0x100000) { /* 1 MiB */
1657 b = byte * 10 / 0x100000;
1658 unit = "MiB";
1659 } else if (byte >= 0x400) { /* 1 KiB */
1660 b = byte * 10 / 0x400;
1661 unit = "KiB";
1662 } else {
1663 b = byte;
1664 unit = "Byte";
1665 }
1666 if (strcmp(unit, "Byte"))
1667 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1668 else
1669 snprintf(buf, len, "%lu %s", b, unit);
1670 }
1671
1672 int
1673 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1674 const struct switch_attr *attr,
1675 struct switch_val *val)
1676 {
1677 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1678 const struct ar8xxx_chip *chip = priv->chip;
1679 u64 *mib_stats, mib_data;
1680 unsigned int port;
1681 int ret;
1682 char *buf = priv->buf;
1683 char buf1[64];
1684 const char *mib_name;
1685 int i, len = 0;
1686 bool mib_stats_empty = true;
1687
1688 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
1689 return -EOPNOTSUPP;
1690
1691 port = val->port_vlan;
1692 if (port >= dev->ports)
1693 return -EINVAL;
1694
1695 mutex_lock(&priv->mib_lock);
1696 ret = ar8xxx_mib_capture(priv);
1697 if (ret)
1698 goto unlock;
1699
1700 ar8xxx_mib_fetch_port_stat(priv, port, false);
1701
1702 len += snprintf(buf + len, sizeof(priv->buf) - len,
1703 "MIB counters\n");
1704
1705 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1706 for (i = 0; i < chip->num_mibs; i++) {
1707 if (chip->mib_decs[i].type > priv->mib_type)
1708 continue;
1709 mib_name = chip->mib_decs[i].name;
1710 mib_data = mib_stats[i];
1711 len += snprintf(buf + len, sizeof(priv->buf) - len,
1712 "%-12s: %llu\n", mib_name, mib_data);
1713 if ((!strcmp(mib_name, "TxByte") ||
1714 !strcmp(mib_name, "RxGoodByte")) &&
1715 mib_data >= 1024) {
1716 ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1717 --len; /* discard newline at the end of buf */
1718 len += snprintf(buf + len, sizeof(priv->buf) - len,
1719 " (%s)\n", buf1);
1720 }
1721 if (mib_stats_empty && mib_data)
1722 mib_stats_empty = false;
1723 }
1724
1725 if (mib_stats_empty)
1726 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1727
1728 val->value.s = buf;
1729 val->len = len;
1730
1731 ret = 0;
1732
1733 unlock:
1734 mutex_unlock(&priv->mib_lock);
1735 return ret;
1736 }
1737
1738 int
1739 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1740 struct switch_val *val)
1741 {
1742 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1743 int age_time = val->value.i;
1744 u32 age_time_val;
1745
1746 if (age_time < 0)
1747 return -EINVAL;
1748
1749 age_time_val = ar8xxx_age_time_val(age_time);
1750 if (age_time_val == 0 || age_time_val > 0xffff)
1751 return -EINVAL;
1752
1753 priv->arl_age_time = age_time;
1754 return 0;
1755 }
1756
1757 int
1758 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1759 struct switch_val *val)
1760 {
1761 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1762 val->value.i = priv->arl_age_time;
1763 return 0;
1764 }
1765
1766 int
1767 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1768 const struct switch_attr *attr,
1769 struct switch_val *val)
1770 {
1771 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1772 struct mii_bus *bus = priv->mii_bus;
1773 const struct ar8xxx_chip *chip = priv->chip;
1774 char *buf = priv->arl_buf;
1775 int i, j, k, len = 0;
1776 struct arl_entry *a, *a1;
1777 u32 status;
1778
1779 if (!chip->get_arl_entry)
1780 return -EOPNOTSUPP;
1781
1782 mutex_lock(&priv->reg_mutex);
1783 mutex_lock(&bus->mdio_lock);
1784
1785 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1786
1787 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1788 a = &priv->arl_table[i];
1789 duplicate:
1790 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1791
1792 if (!status)
1793 break;
1794
1795 /* avoid duplicates
1796 * ARL table can include multiple valid entries
1797 * per MAC, just with differing status codes
1798 */
1799 for (j = 0; j < i; ++j) {
1800 a1 = &priv->arl_table[j];
1801 if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
1802 /* ignore ports already seen in former entry */
1803 a->portmap &= ~a1->portmap;
1804 if (!a->portmap)
1805 goto duplicate;
1806 }
1807 }
1808 }
1809
1810 mutex_unlock(&bus->mdio_lock);
1811
1812 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1813 "address resolution table\n");
1814
1815 if (i == AR8XXX_NUM_ARL_RECORDS)
1816 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1817 "Too many entries found, displaying the first %d only!\n",
1818 AR8XXX_NUM_ARL_RECORDS);
1819
1820 for (j = 0; j < priv->dev.ports; ++j) {
1821 for (k = 0; k < i; ++k) {
1822 a = &priv->arl_table[k];
1823 if (!(a->portmap & BIT(j)))
1824 continue;
1825 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1826 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1827 j,
1828 a->mac[5], a->mac[4], a->mac[3],
1829 a->mac[2], a->mac[1], a->mac[0]);
1830 }
1831 }
1832
1833 val->value.s = buf;
1834 val->len = len;
1835
1836 mutex_unlock(&priv->reg_mutex);
1837
1838 return 0;
1839 }
1840
1841 int
1842 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1843 const struct switch_attr *attr,
1844 struct switch_val *val)
1845 {
1846 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1847 int ret;
1848
1849 mutex_lock(&priv->reg_mutex);
1850 ret = priv->chip->atu_flush(priv);
1851 mutex_unlock(&priv->reg_mutex);
1852
1853 return ret;
1854 }
1855
1856 int
1857 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1858 const struct switch_attr *attr,
1859 struct switch_val *val)
1860 {
1861 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1862 int port, ret;
1863
1864 port = val->port_vlan;
1865 if (port >= dev->ports)
1866 return -EINVAL;
1867
1868 mutex_lock(&priv->reg_mutex);
1869 ret = priv->chip->atu_flush_port(priv, port);
1870 mutex_unlock(&priv->reg_mutex);
1871
1872 return ret;
1873 }
1874
1875 int
1876 ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
1877 struct switch_port_stats *stats)
1878 {
1879 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1880 u64 *mib_stats;
1881
1882 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
1883 return -EOPNOTSUPP;
1884
1885 if (!(priv->chip->mib_rxb_id || priv->chip->mib_txb_id))
1886 return -EOPNOTSUPP;
1887
1888 if (port >= dev->ports)
1889 return -EINVAL;
1890
1891 mutex_lock(&priv->mib_lock);
1892
1893 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
1894
1895 stats->tx_bytes = mib_stats[priv->chip->mib_txb_id];
1896 stats->rx_bytes = mib_stats[priv->chip->mib_rxb_id];
1897
1898 mutex_unlock(&priv->mib_lock);
1899 return 0;
1900 }
1901
1902 static int
1903 ar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
1904 {
1905 struct ar8xxx_priv *priv = bus->priv;
1906 return priv->chip->phy_read(priv, phy_addr, reg_addr);
1907 }
1908
1909 static int
1910 ar8xxx_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr,
1911 u16 reg_val)
1912 {
1913 struct ar8xxx_priv *priv = bus->priv;
1914 return priv->chip->phy_write(priv, phy_addr, reg_addr, reg_val);
1915 }
1916
1917 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1918 {
1919 .type = SWITCH_TYPE_INT,
1920 .name = "enable_vlan",
1921 .description = "Enable VLAN mode",
1922 .set = ar8xxx_sw_set_vlan,
1923 .get = ar8xxx_sw_get_vlan,
1924 .max = 1
1925 },
1926 {
1927 .type = SWITCH_TYPE_NOVAL,
1928 .name = "reset_mibs",
1929 .description = "Reset all MIB counters",
1930 .set = ar8xxx_sw_set_reset_mibs,
1931 },
1932 {
1933 .type = SWITCH_TYPE_INT,
1934 .name = "ar8xxx_mib_poll_interval",
1935 .description = "MIB polling interval in msecs (0 to disable)",
1936 .set = ar8xxx_sw_set_mib_poll_interval,
1937 .get = ar8xxx_sw_get_mib_poll_interval
1938 },
1939 {
1940 .type = SWITCH_TYPE_INT,
1941 .name = "ar8xxx_mib_type",
1942 .description = "MIB type (0=basic 1=extended)",
1943 .set = ar8xxx_sw_set_mib_type,
1944 .get = ar8xxx_sw_get_mib_type
1945 },
1946 {
1947 .type = SWITCH_TYPE_INT,
1948 .name = "enable_mirror_rx",
1949 .description = "Enable mirroring of RX packets",
1950 .set = ar8xxx_sw_set_mirror_rx_enable,
1951 .get = ar8xxx_sw_get_mirror_rx_enable,
1952 .max = 1
1953 },
1954 {
1955 .type = SWITCH_TYPE_INT,
1956 .name = "enable_mirror_tx",
1957 .description = "Enable mirroring of TX packets",
1958 .set = ar8xxx_sw_set_mirror_tx_enable,
1959 .get = ar8xxx_sw_get_mirror_tx_enable,
1960 .max = 1
1961 },
1962 {
1963 .type = SWITCH_TYPE_INT,
1964 .name = "mirror_monitor_port",
1965 .description = "Mirror monitor port",
1966 .set = ar8xxx_sw_set_mirror_monitor_port,
1967 .get = ar8xxx_sw_get_mirror_monitor_port,
1968 .max = AR8216_NUM_PORTS - 1
1969 },
1970 {
1971 .type = SWITCH_TYPE_INT,
1972 .name = "mirror_source_port",
1973 .description = "Mirror source port",
1974 .set = ar8xxx_sw_set_mirror_source_port,
1975 .get = ar8xxx_sw_get_mirror_source_port,
1976 .max = AR8216_NUM_PORTS - 1
1977 },
1978 {
1979 .type = SWITCH_TYPE_STRING,
1980 .name = "arl_table",
1981 .description = "Get ARL table",
1982 .set = NULL,
1983 .get = ar8xxx_sw_get_arl_table,
1984 },
1985 {
1986 .type = SWITCH_TYPE_NOVAL,
1987 .name = "flush_arl_table",
1988 .description = "Flush ARL table",
1989 .set = ar8xxx_sw_set_flush_arl_table,
1990 },
1991 };
1992
1993 const struct switch_attr ar8xxx_sw_attr_port[] = {
1994 {
1995 .type = SWITCH_TYPE_NOVAL,
1996 .name = "reset_mib",
1997 .description = "Reset single port MIB counters",
1998 .set = ar8xxx_sw_set_port_reset_mib,
1999 },
2000 {
2001 .type = SWITCH_TYPE_STRING,
2002 .name = "mib",
2003 .description = "Get port's MIB counters",
2004 .set = NULL,
2005 .get = ar8xxx_sw_get_port_mib,
2006 },
2007 {
2008 .type = SWITCH_TYPE_NOVAL,
2009 .name = "flush_arl_table",
2010 .description = "Flush port's ARL table entries",
2011 .set = ar8xxx_sw_set_flush_port_arl_table,
2012 },
2013 };
2014
2015 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
2016 {
2017 .type = SWITCH_TYPE_INT,
2018 .name = "vid",
2019 .description = "VLAN ID (0-4094)",
2020 .set = ar8xxx_sw_set_vid,
2021 .get = ar8xxx_sw_get_vid,
2022 .max = 4094,
2023 },
2024 };
2025
2026 static const struct switch_dev_ops ar8xxx_sw_ops = {
2027 .attr_global = {
2028 .attr = ar8xxx_sw_attr_globals,
2029 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2030 },
2031 .attr_port = {
2032 .attr = ar8xxx_sw_attr_port,
2033 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2034 },
2035 .attr_vlan = {
2036 .attr = ar8xxx_sw_attr_vlan,
2037 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2038 },
2039 .get_port_pvid = ar8xxx_sw_get_pvid,
2040 .set_port_pvid = ar8xxx_sw_set_pvid,
2041 .get_vlan_ports = ar8xxx_sw_get_ports,
2042 .set_vlan_ports = ar8xxx_sw_set_ports,
2043 .apply_config = ar8xxx_sw_hw_apply,
2044 .reset_switch = ar8xxx_sw_reset_switch,
2045 .get_port_link = ar8xxx_sw_get_port_link,
2046 .get_port_stats = ar8xxx_sw_get_port_stats,
2047 };
2048
2049 static const struct ar8xxx_chip ar7240sw_chip = {
2050 .caps = AR8XXX_CAP_MIB_COUNTERS,
2051
2052 .reg_port_stats_start = 0x20000,
2053 .reg_port_stats_length = 0x100,
2054 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2055
2056 .name = "Atheros AR724X/AR933X built-in",
2057 .ports = AR7240SW_NUM_PORTS,
2058 .vlans = AR8216_NUM_VLANS,
2059 .swops = &ar8xxx_sw_ops,
2060
2061 .hw_init = ar7240sw_hw_init,
2062 .init_globals = ar7240sw_init_globals,
2063 .init_port = ar8229_init_port,
2064 .phy_read = ar8216_phy_read,
2065 .phy_write = ar8216_phy_write,
2066 .setup_port = ar7240sw_setup_port,
2067 .read_port_status = ar8216_read_port_status,
2068 .atu_flush = ar8216_atu_flush,
2069 .atu_flush_port = ar8216_atu_flush_port,
2070 .vtu_flush = ar8216_vtu_flush,
2071 .vtu_load_vlan = ar8216_vtu_load_vlan,
2072 .set_mirror_regs = ar8216_set_mirror_regs,
2073 .get_arl_entry = ar8216_get_arl_entry,
2074 .sw_hw_apply = ar8xxx_sw_hw_apply,
2075
2076 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2077 .mib_decs = ar8236_mibs,
2078 .mib_func = AR8216_REG_MIB_FUNC,
2079 .mib_rxb_id = AR8236_MIB_RXB_ID,
2080 .mib_txb_id = AR8236_MIB_TXB_ID,
2081 };
2082
2083 static const struct ar8xxx_chip ar8216_chip = {
2084 .caps = AR8XXX_CAP_MIB_COUNTERS,
2085
2086 .reg_port_stats_start = 0x19000,
2087 .reg_port_stats_length = 0xa0,
2088 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2089
2090 .name = "Atheros AR8216",
2091 .ports = AR8216_NUM_PORTS,
2092 .vlans = AR8216_NUM_VLANS,
2093 .swops = &ar8xxx_sw_ops,
2094
2095 .hw_init = ar8216_hw_init,
2096 .init_globals = ar8216_init_globals,
2097 .init_port = ar8216_init_port,
2098 .setup_port = ar8216_setup_port,
2099 .read_port_status = ar8216_read_port_status,
2100 .atu_flush = ar8216_atu_flush,
2101 .atu_flush_port = ar8216_atu_flush_port,
2102 .vtu_flush = ar8216_vtu_flush,
2103 .vtu_load_vlan = ar8216_vtu_load_vlan,
2104 .set_mirror_regs = ar8216_set_mirror_regs,
2105 .get_arl_entry = ar8216_get_arl_entry,
2106 .sw_hw_apply = ar8xxx_sw_hw_apply,
2107
2108 .num_mibs = ARRAY_SIZE(ar8216_mibs),
2109 .mib_decs = ar8216_mibs,
2110 .mib_func = AR8216_REG_MIB_FUNC,
2111 .mib_rxb_id = AR8216_MIB_RXB_ID,
2112 .mib_txb_id = AR8216_MIB_TXB_ID,
2113 };
2114
2115 static const struct ar8xxx_chip ar8229_chip = {
2116 .caps = AR8XXX_CAP_MIB_COUNTERS,
2117
2118 .reg_port_stats_start = 0x20000,
2119 .reg_port_stats_length = 0x100,
2120 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2121
2122 .name = "Atheros AR8229",
2123 .ports = AR8216_NUM_PORTS,
2124 .vlans = AR8216_NUM_VLANS,
2125 .swops = &ar8xxx_sw_ops,
2126
2127 .hw_init = ar8229_hw_init,
2128 .init_globals = ar8229_init_globals,
2129 .init_port = ar8229_init_port,
2130 .phy_read = ar8216_phy_read,
2131 .phy_write = ar8216_phy_write,
2132 .setup_port = ar8236_setup_port,
2133 .read_port_status = ar8216_read_port_status,
2134 .atu_flush = ar8216_atu_flush,
2135 .atu_flush_port = ar8216_atu_flush_port,
2136 .vtu_flush = ar8216_vtu_flush,
2137 .vtu_load_vlan = ar8216_vtu_load_vlan,
2138 .set_mirror_regs = ar8216_set_mirror_regs,
2139 .get_arl_entry = ar8216_get_arl_entry,
2140 .sw_hw_apply = ar8xxx_sw_hw_apply,
2141
2142 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2143 .mib_decs = ar8236_mibs,
2144 .mib_func = AR8216_REG_MIB_FUNC,
2145 .mib_rxb_id = AR8236_MIB_RXB_ID,
2146 .mib_txb_id = AR8236_MIB_TXB_ID,
2147 };
2148
2149 static const struct ar8xxx_chip ar8236_chip = {
2150 .caps = AR8XXX_CAP_MIB_COUNTERS,
2151
2152 .reg_port_stats_start = 0x20000,
2153 .reg_port_stats_length = 0x100,
2154 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2155
2156 .name = "Atheros AR8236",
2157 .ports = AR8216_NUM_PORTS,
2158 .vlans = AR8216_NUM_VLANS,
2159 .swops = &ar8xxx_sw_ops,
2160
2161 .hw_init = ar8216_hw_init,
2162 .init_globals = ar8236_init_globals,
2163 .init_port = ar8216_init_port,
2164 .setup_port = ar8236_setup_port,
2165 .read_port_status = ar8216_read_port_status,
2166 .atu_flush = ar8216_atu_flush,
2167 .atu_flush_port = ar8216_atu_flush_port,
2168 .vtu_flush = ar8216_vtu_flush,
2169 .vtu_load_vlan = ar8216_vtu_load_vlan,
2170 .set_mirror_regs = ar8216_set_mirror_regs,
2171 .get_arl_entry = ar8216_get_arl_entry,
2172 .sw_hw_apply = ar8xxx_sw_hw_apply,
2173
2174 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2175 .mib_decs = ar8236_mibs,
2176 .mib_func = AR8216_REG_MIB_FUNC,
2177 .mib_rxb_id = AR8236_MIB_RXB_ID,
2178 .mib_txb_id = AR8236_MIB_TXB_ID,
2179 };
2180
2181 static const struct ar8xxx_chip ar8316_chip = {
2182 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2183
2184 .reg_port_stats_start = 0x20000,
2185 .reg_port_stats_length = 0x100,
2186 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2187
2188 .name = "Atheros AR8316",
2189 .ports = AR8216_NUM_PORTS,
2190 .vlans = AR8X16_MAX_VLANS,
2191 .swops = &ar8xxx_sw_ops,
2192
2193 .hw_init = ar8316_hw_init,
2194 .init_globals = ar8316_init_globals,
2195 .init_port = ar8216_init_port,
2196 .setup_port = ar8216_setup_port,
2197 .read_port_status = ar8216_read_port_status,
2198 .atu_flush = ar8216_atu_flush,
2199 .atu_flush_port = ar8216_atu_flush_port,
2200 .vtu_flush = ar8216_vtu_flush,
2201 .vtu_load_vlan = ar8216_vtu_load_vlan,
2202 .set_mirror_regs = ar8216_set_mirror_regs,
2203 .get_arl_entry = ar8216_get_arl_entry,
2204 .sw_hw_apply = ar8xxx_sw_hw_apply,
2205
2206 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2207 .mib_decs = ar8236_mibs,
2208 .mib_func = AR8216_REG_MIB_FUNC,
2209 .mib_rxb_id = AR8236_MIB_RXB_ID,
2210 .mib_txb_id = AR8236_MIB_TXB_ID,
2211 };
2212
2213 static int
2214 ar8xxx_read_id(struct ar8xxx_priv *priv)
2215 {
2216 u32 val;
2217 u16 id;
2218 int i;
2219
2220 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2221 if (val == ~0)
2222 return -ENODEV;
2223
2224 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2225 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2226 u16 t;
2227
2228 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2229 if (val == ~0)
2230 return -ENODEV;
2231
2232 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2233 if (t != id)
2234 return -ENODEV;
2235 }
2236
2237 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2238 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2239 return 0;
2240 }
2241
2242 static int
2243 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2244 {
2245 int ret;
2246
2247 ret = ar8xxx_read_id(priv);
2248 if(ret)
2249 return ret;
2250
2251 switch (priv->chip_ver) {
2252 case AR8XXX_VER_AR8216:
2253 priv->chip = &ar8216_chip;
2254 break;
2255 case AR8XXX_VER_AR8236:
2256 priv->chip = &ar8236_chip;
2257 break;
2258 case AR8XXX_VER_AR8316:
2259 priv->chip = &ar8316_chip;
2260 break;
2261 case AR8XXX_VER_AR8327:
2262 priv->chip = &ar8327_chip;
2263 break;
2264 case AR8XXX_VER_AR8337:
2265 priv->chip = &ar8337_chip;
2266 break;
2267 default:
2268 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2269 priv->chip_ver, priv->chip_rev);
2270
2271 return -ENODEV;
2272 }
2273
2274 return 0;
2275 }
2276
2277 static void
2278 ar8xxx_mib_work_func(struct work_struct *work)
2279 {
2280 struct ar8xxx_priv *priv;
2281 int err, i;
2282
2283 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2284
2285 mutex_lock(&priv->mib_lock);
2286
2287 err = ar8xxx_mib_capture(priv);
2288 if (err)
2289 goto next_attempt;
2290
2291 for (i = 0; i < priv->dev.ports; i++)
2292 ar8xxx_mib_fetch_port_stat(priv, i, false);
2293
2294 next_attempt:
2295 mutex_unlock(&priv->mib_lock);
2296 schedule_delayed_work(&priv->mib_work,
2297 msecs_to_jiffies(priv->mib_poll_interval));
2298 }
2299
2300 static int
2301 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2302 {
2303 unsigned int len;
2304
2305 if (!ar8xxx_has_mib_counters(priv))
2306 return 0;
2307
2308 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2309
2310 len = priv->dev.ports * priv->chip->num_mibs *
2311 sizeof(*priv->mib_stats);
2312 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2313
2314 if (!priv->mib_stats)
2315 return -ENOMEM;
2316
2317 return 0;
2318 }
2319
2320 static void
2321 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2322 {
2323 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
2324 return;
2325
2326 schedule_delayed_work(&priv->mib_work,
2327 msecs_to_jiffies(priv->mib_poll_interval));
2328 }
2329
2330 static void
2331 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2332 {
2333 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
2334 return;
2335
2336 cancel_delayed_work_sync(&priv->mib_work);
2337 }
2338
2339 static struct ar8xxx_priv *
2340 ar8xxx_create(void)
2341 {
2342 struct ar8xxx_priv *priv;
2343
2344 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2345 if (priv == NULL)
2346 return NULL;
2347
2348 mutex_init(&priv->reg_mutex);
2349 mutex_init(&priv->mib_lock);
2350 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2351
2352 return priv;
2353 }
2354
2355 static void
2356 ar8xxx_free(struct ar8xxx_priv *priv)
2357 {
2358 if (priv->chip && priv->chip->cleanup)
2359 priv->chip->cleanup(priv);
2360
2361 kfree(priv->chip_data);
2362 kfree(priv->mib_stats);
2363 kfree(priv);
2364 }
2365
2366 static int
2367 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2368 {
2369 const struct ar8xxx_chip *chip;
2370 struct switch_dev *swdev;
2371 int ret;
2372
2373 chip = priv->chip;
2374
2375 swdev = &priv->dev;
2376 swdev->cpu_port = AR8216_PORT_CPU;
2377 swdev->name = chip->name;
2378 swdev->vlans = chip->vlans;
2379 swdev->ports = chip->ports;
2380 swdev->ops = chip->swops;
2381
2382 ret = ar8xxx_mib_init(priv);
2383 if (ret)
2384 return ret;
2385
2386 return 0;
2387 }
2388
2389 static int
2390 ar8xxx_start(struct ar8xxx_priv *priv)
2391 {
2392 int ret;
2393
2394 priv->init = true;
2395
2396 ret = priv->chip->hw_init(priv);
2397 if (ret)
2398 return ret;
2399
2400 ret = ar8xxx_sw_reset_switch(&priv->dev);
2401 if (ret)
2402 return ret;
2403
2404 priv->init = false;
2405
2406 ar8xxx_mib_start(priv);
2407
2408 return 0;
2409 }
2410
2411 static int
2412 ar8xxx_phy_config_init(struct phy_device *phydev)
2413 {
2414 struct ar8xxx_priv *priv = phydev->priv;
2415 struct net_device *dev = phydev->attached_dev;
2416 int ret;
2417
2418 if (WARN_ON(!priv))
2419 return -ENODEV;
2420
2421 if (priv->chip->config_at_probe)
2422 return ar8xxx_phy_check_aneg(phydev);
2423
2424 priv->phy = phydev;
2425
2426 if (phydev->mdio.addr != 0) {
2427 if (chip_is_ar8316(priv)) {
2428 /* switch device has been initialized, reinit */
2429 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2430 priv->initialized = false;
2431 priv->port4_phy = true;
2432 ar8316_hw_init(priv);
2433 return 0;
2434 }
2435
2436 return 0;
2437 }
2438
2439 ret = ar8xxx_start(priv);
2440 if (ret)
2441 return ret;
2442
2443 /* VID fixup only needed on ar8216 */
2444 if (chip_is_ar8216(priv)) {
2445 dev->phy_ptr = priv;
2446 dev->priv_flags |= IFF_NO_IP_ALIGN;
2447 dev->eth_mangle_rx = ar8216_mangle_rx;
2448 dev->eth_mangle_tx = ar8216_mangle_tx;
2449 }
2450
2451 return 0;
2452 }
2453
2454 static bool
2455 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2456 {
2457 bool link_new, changed = false;
2458 u32 status;
2459 int i;
2460
2461 mutex_lock(&priv->reg_mutex);
2462
2463 for (i = 0; i < priv->dev.ports; i++) {
2464 status = priv->chip->read_port_status(priv, i);
2465 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2466 if (link_new == priv->link_up[i])
2467 continue;
2468
2469 priv->link_up[i] = link_new;
2470 changed = true;
2471 /* flush ARL entries for this port if it went down*/
2472 if (!link_new)
2473 priv->chip->atu_flush_port(priv, i);
2474 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2475 i, link_new ? "up" : "down");
2476 }
2477
2478 mutex_unlock(&priv->reg_mutex);
2479
2480 return changed;
2481 }
2482
2483 static int
2484 ar8xxx_phy_read_status(struct phy_device *phydev)
2485 {
2486 struct ar8xxx_priv *priv = phydev->priv;
2487 struct switch_port_link link;
2488
2489 /* check for switch port link changes */
2490 if (phydev->state == PHY_CHANGELINK)
2491 ar8xxx_check_link_states(priv);
2492
2493 if (phydev->mdio.addr != 0)
2494 return genphy_read_status(phydev);
2495
2496 ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2497 phydev->link = !!link.link;
2498 if (!phydev->link)
2499 return 0;
2500
2501 switch (link.speed) {
2502 case SWITCH_PORT_SPEED_10:
2503 phydev->speed = SPEED_10;
2504 break;
2505 case SWITCH_PORT_SPEED_100:
2506 phydev->speed = SPEED_100;
2507 break;
2508 case SWITCH_PORT_SPEED_1000:
2509 phydev->speed = SPEED_1000;
2510 break;
2511 default:
2512 phydev->speed = 0;
2513 }
2514 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2515
2516 phydev->state = PHY_RUNNING;
2517 netif_carrier_on(phydev->attached_dev);
2518 if (phydev->adjust_link)
2519 phydev->adjust_link(phydev->attached_dev);
2520
2521 return 0;
2522 }
2523
2524 static int
2525 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2526 {
2527 if (phydev->mdio.addr == 0)
2528 return 0;
2529
2530 return genphy_config_aneg(phydev);
2531 }
2532
2533 static const u32 ar8xxx_phy_ids[] = {
2534 0x004dd033,
2535 0x004dd034, /* AR8327 */
2536 0x004dd036, /* AR8337 */
2537 0x004dd041,
2538 0x004dd042,
2539 0x004dd043, /* AR8236 */
2540 };
2541
2542 static bool
2543 ar8xxx_phy_match(u32 phy_id)
2544 {
2545 int i;
2546
2547 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2548 if (phy_id == ar8xxx_phy_ids[i])
2549 return true;
2550
2551 return false;
2552 }
2553
2554 static bool
2555 ar8xxx_is_possible(struct mii_bus *bus)
2556 {
2557 unsigned int i, found_phys = 0;
2558
2559 for (i = 0; i < 5; i++) {
2560 u32 phy_id;
2561
2562 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2563 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2564 if (ar8xxx_phy_match(phy_id)) {
2565 found_phys++;
2566 } else if (phy_id) {
2567 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2568 dev_name(&bus->dev), i, phy_id);
2569 }
2570 }
2571 return !!found_phys;
2572 }
2573
2574 static int
2575 ar8xxx_phy_probe(struct phy_device *phydev)
2576 {
2577 struct ar8xxx_priv *priv;
2578 struct switch_dev *swdev;
2579 int ret;
2580
2581 /* skip PHYs at unused adresses */
2582 if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
2583 return -ENODEV;
2584
2585 if (!ar8xxx_is_possible(phydev->mdio.bus))
2586 return -ENODEV;
2587
2588 mutex_lock(&ar8xxx_dev_list_lock);
2589 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2590 if (priv->mii_bus == phydev->mdio.bus)
2591 goto found;
2592
2593 priv = ar8xxx_create();
2594 if (priv == NULL) {
2595 ret = -ENOMEM;
2596 goto unlock;
2597 }
2598
2599 priv->mii_bus = phydev->mdio.bus;
2600 priv->pdev = &phydev->mdio.dev;
2601
2602 ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
2603 &priv->mib_poll_interval);
2604 if (ret)
2605 priv->mib_poll_interval = 0;
2606
2607 ret = ar8xxx_id_chip(priv);
2608 if (ret)
2609 goto free_priv;
2610
2611 ret = ar8xxx_probe_switch(priv);
2612 if (ret)
2613 goto free_priv;
2614
2615 swdev = &priv->dev;
2616 swdev->alias = dev_name(&priv->mii_bus->dev);
2617 ret = register_switch(swdev, NULL);
2618 if (ret)
2619 goto free_priv;
2620
2621 pr_info("%s: %s rev. %u switch registered on %s\n",
2622 swdev->devname, swdev->name, priv->chip_rev,
2623 dev_name(&priv->mii_bus->dev));
2624
2625 list_add(&priv->list, &ar8xxx_dev_list);
2626
2627 found:
2628 priv->use_count++;
2629
2630 if (phydev->mdio.addr == 0) {
2631 if (ar8xxx_has_gige(priv)) {
2632 phydev->supported = SUPPORTED_1000baseT_Full;
2633 phydev->advertising = ADVERTISED_1000baseT_Full;
2634 } else {
2635 phydev->supported = SUPPORTED_100baseT_Full;
2636 phydev->advertising = ADVERTISED_100baseT_Full;
2637 }
2638
2639 if (priv->chip->config_at_probe) {
2640 priv->phy = phydev;
2641
2642 ret = ar8xxx_start(priv);
2643 if (ret)
2644 goto err_unregister_switch;
2645 }
2646 } else {
2647 if (ar8xxx_has_gige(priv)) {
2648 phydev->supported |= SUPPORTED_1000baseT_Full;
2649 phydev->advertising |= ADVERTISED_1000baseT_Full;
2650 }
2651 if (priv->chip->phy_rgmii_set)
2652 priv->chip->phy_rgmii_set(priv, phydev);
2653 }
2654
2655 phydev->priv = priv;
2656
2657 mutex_unlock(&ar8xxx_dev_list_lock);
2658
2659 return 0;
2660
2661 err_unregister_switch:
2662 if (--priv->use_count)
2663 goto unlock;
2664
2665 unregister_switch(&priv->dev);
2666
2667 free_priv:
2668 ar8xxx_free(priv);
2669 unlock:
2670 mutex_unlock(&ar8xxx_dev_list_lock);
2671 return ret;
2672 }
2673
2674 static void
2675 ar8xxx_phy_detach(struct phy_device *phydev)
2676 {
2677 struct net_device *dev = phydev->attached_dev;
2678
2679 if (!dev)
2680 return;
2681
2682 dev->phy_ptr = NULL;
2683 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2684 dev->eth_mangle_rx = NULL;
2685 dev->eth_mangle_tx = NULL;
2686 }
2687
2688 static void
2689 ar8xxx_phy_remove(struct phy_device *phydev)
2690 {
2691 struct ar8xxx_priv *priv = phydev->priv;
2692
2693 if (WARN_ON(!priv))
2694 return;
2695
2696 phydev->priv = NULL;
2697
2698 mutex_lock(&ar8xxx_dev_list_lock);
2699
2700 if (--priv->use_count > 0) {
2701 mutex_unlock(&ar8xxx_dev_list_lock);
2702 return;
2703 }
2704
2705 list_del(&priv->list);
2706 mutex_unlock(&ar8xxx_dev_list_lock);
2707
2708 unregister_switch(&priv->dev);
2709 ar8xxx_mib_stop(priv);
2710 ar8xxx_free(priv);
2711 }
2712
2713 static int
2714 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2715 {
2716 /* we don't need an extra reset */
2717 return 0;
2718 }
2719
2720 static struct phy_driver ar8xxx_phy_driver[] = {
2721 {
2722 .phy_id = 0x004d0000,
2723 .name = "Atheros AR8216/AR8236/AR8316",
2724 .phy_id_mask = 0xffff0000,
2725 .features = PHY_BASIC_FEATURES,
2726 .probe = ar8xxx_phy_probe,
2727 .remove = ar8xxx_phy_remove,
2728 .detach = ar8xxx_phy_detach,
2729 .config_init = ar8xxx_phy_config_init,
2730 .config_aneg = ar8xxx_phy_config_aneg,
2731 .read_status = ar8xxx_phy_read_status,
2732 .soft_reset = ar8xxx_phy_soft_reset,
2733 }
2734 };
2735
2736 static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
2737 {
2738 .compatible = "qca,ar7240sw",
2739 .data = &ar7240sw_chip,
2740 }, {
2741 .compatible = "qca,ar8229",
2742 .data = &ar8229_chip,
2743 }, {
2744 .compatible = "qca,ar8236",
2745 .data = &ar8236_chip,
2746 }, {
2747 .compatible = "qca,ar8327",
2748 .data = &ar8327_chip,
2749 },
2750 { /* sentinel */ },
2751 };
2752
2753 static int
2754 ar8xxx_mdiodev_probe(struct mdio_device *mdiodev)
2755 {
2756 const struct of_device_id *match;
2757 struct ar8xxx_priv *priv;
2758 struct switch_dev *swdev;
2759 struct device_node *mdio_node;
2760 int ret;
2761
2762 match = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev);
2763 if (!match)
2764 return -EINVAL;
2765
2766 priv = ar8xxx_create();
2767 if (priv == NULL)
2768 return -ENOMEM;
2769
2770 priv->mii_bus = mdiodev->bus;
2771 priv->pdev = &mdiodev->dev;
2772 priv->chip = (const struct ar8xxx_chip *) match->data;
2773
2774 ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
2775 &priv->mib_poll_interval);
2776 if (ret)
2777 priv->mib_poll_interval = 0;
2778
2779 ret = ar8xxx_read_id(priv);
2780 if (ret)
2781 goto free_priv;
2782
2783 ret = ar8xxx_probe_switch(priv);
2784 if (ret)
2785 goto free_priv;
2786
2787 if (priv->chip->phy_read && priv->chip->phy_write) {
2788 priv->sw_mii_bus = devm_mdiobus_alloc(&mdiodev->dev);
2789 priv->sw_mii_bus->name = "ar8xxx-mdio";
2790 priv->sw_mii_bus->read = ar8xxx_phy_read;
2791 priv->sw_mii_bus->write = ar8xxx_phy_write;
2792 priv->sw_mii_bus->priv = priv;
2793 priv->sw_mii_bus->parent = &mdiodev->dev;
2794 snprintf(priv->sw_mii_bus->id, MII_BUS_ID_SIZE, "%s",
2795 dev_name(&mdiodev->dev));
2796 mdio_node = of_get_child_by_name(priv->pdev->of_node, "mdio-bus");
2797 ret = of_mdiobus_register(priv->sw_mii_bus, mdio_node);
2798 if (ret)
2799 goto free_priv;
2800 }
2801
2802 swdev = &priv->dev;
2803 swdev->alias = dev_name(&mdiodev->dev);
2804
2805 if (of_property_read_bool(priv->pdev->of_node, "qca,phy4-mii-enable")) {
2806 priv->port4_phy = true;
2807 swdev->ports--;
2808 }
2809
2810 ret = register_switch(swdev, NULL);
2811 if (ret)
2812 goto free_priv;
2813
2814 pr_info("%s: %s rev. %u switch registered on %s\n",
2815 swdev->devname, swdev->name, priv->chip_rev,
2816 dev_name(&priv->mii_bus->dev));
2817
2818 mutex_lock(&ar8xxx_dev_list_lock);
2819 list_add(&priv->list, &ar8xxx_dev_list);
2820 mutex_unlock(&ar8xxx_dev_list_lock);
2821
2822 priv->use_count++;
2823
2824 ret = ar8xxx_start(priv);
2825 if (ret)
2826 goto err_unregister_switch;
2827
2828 dev_set_drvdata(&mdiodev->dev, priv);
2829
2830 return 0;
2831
2832 err_unregister_switch:
2833 if (--priv->use_count)
2834 return ret;
2835
2836 unregister_switch(&priv->dev);
2837
2838 free_priv:
2839 ar8xxx_free(priv);
2840 return ret;
2841 }
2842
2843 static void
2844 ar8xxx_mdiodev_remove(struct mdio_device *mdiodev)
2845 {
2846 struct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev);
2847
2848 if (WARN_ON(!priv))
2849 return;
2850
2851 mutex_lock(&ar8xxx_dev_list_lock);
2852
2853 if (--priv->use_count > 0) {
2854 mutex_unlock(&ar8xxx_dev_list_lock);
2855 return;
2856 }
2857
2858 list_del(&priv->list);
2859 mutex_unlock(&ar8xxx_dev_list_lock);
2860
2861 unregister_switch(&priv->dev);
2862 ar8xxx_mib_stop(priv);
2863 if(priv->sw_mii_bus)
2864 mdiobus_unregister(priv->sw_mii_bus);
2865 ar8xxx_free(priv);
2866 }
2867
2868 static struct mdio_driver ar8xxx_mdio_driver = {
2869 .probe = ar8xxx_mdiodev_probe,
2870 .remove = ar8xxx_mdiodev_remove,
2871 .mdiodrv.driver = {
2872 .name = "ar8xxx-switch",
2873 .of_match_table = ar8xxx_mdiodev_of_match,
2874 },
2875 };
2876
2877 static int __init ar8216_init(void)
2878 {
2879 int ret;
2880
2881 ret = phy_drivers_register(ar8xxx_phy_driver,
2882 ARRAY_SIZE(ar8xxx_phy_driver),
2883 THIS_MODULE);
2884 if (ret)
2885 return ret;
2886
2887 ret = mdio_driver_register(&ar8xxx_mdio_driver);
2888 if (ret)
2889 phy_drivers_unregister(ar8xxx_phy_driver,
2890 ARRAY_SIZE(ar8xxx_phy_driver));
2891
2892 return ret;
2893 }
2894 module_init(ar8216_init);
2895
2896 static void __exit ar8216_exit(void)
2897 {
2898 mdio_driver_unregister(&ar8xxx_mdio_driver);
2899 phy_drivers_unregister(ar8xxx_phy_driver,
2900 ARRAY_SIZE(ar8xxx_phy_driver));
2901 }
2902 module_exit(ar8216_exit);
2903
2904 MODULE_LICENSE("GPL");
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