2 * ar8216.c: AR8216 switch driver
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
42 extern const struct ar8xxx_chip ar8327_chip
;
43 extern const struct ar8xxx_chip ar8337_chip
;
45 #define MIB_DESC(_s , _o, _n) \
52 static const struct ar8xxx_mib_desc ar8216_mibs
[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD
, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE
, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI
, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR
, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR
, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT
, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT
, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE
, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE
, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE
, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE
, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE
, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE
, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG
, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE
, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE
, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW
, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED
, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD
, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE
, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI
, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN
, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE
, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE
, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE
, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE
, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE
, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE
, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE
, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE
, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION
, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL
, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL
, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL
, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER
, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER
, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL
, "TxLateCol"),
92 const struct ar8xxx_mib_desc ar8236_mibs
[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD
, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE
, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI
, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR
, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR
, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT
, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT
, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE
, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE
, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE
, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE
, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE
, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE
, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE
, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG
, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE
, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE
, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW
, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED
, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD
, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE
, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI
, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN
, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE
, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE
, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE
, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE
, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE
, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE
, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE
, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE
, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE
, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION
, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL
, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL
, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL
, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER
, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER
, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL
, "TxLateCol"),
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock
);
135 static LIST_HEAD(ar8xxx_dev_list
);
138 ar8xxx_mib_start(struct ar8xxx_priv
*priv
);
140 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
);
142 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
144 ar8xxx_phy_poll_reset(struct mii_bus
*bus
)
146 unsigned int sleep_msecs
= 20;
149 for (elapsed
= sleep_msecs
; elapsed
<= 600;
150 elapsed
+= sleep_msecs
) {
152 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
153 ret
= mdiobus_read(bus
, i
, MII_BMCR
);
156 if (ret
& BMCR_RESET
)
158 if (i
== AR8XXX_NUM_PHYS
- 1) {
159 usleep_range(1000, 2000);
168 ar8xxx_phy_check_aneg(struct phy_device
*phydev
)
172 if (phydev
->autoneg
!= AUTONEG_ENABLE
)
175 * BMCR_ANENABLE might have been cleared
176 * by phy_init_hw in certain kernel versions
177 * therefore check for it
179 ret
= phy_read(phydev
, MII_BMCR
);
182 if (ret
& BMCR_ANENABLE
)
185 dev_info(&phydev
->mdio
.dev
, "ANEG disabled, re-enabling ...\n");
186 ret
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
187 return phy_write(phydev
, MII_BMCR
, ret
);
191 ar8xxx_phy_init(struct ar8xxx_priv
*priv
)
196 bus
= priv
->sw_mii_bus
?: priv
->mii_bus
;
197 for (i
= 0; i
< AR8XXX_NUM_PHYS
; i
++) {
198 if (priv
->chip
->phy_fixup
)
199 priv
->chip
->phy_fixup(priv
, i
);
201 /* initialize the port itself */
202 mdiobus_write(bus
, i
, MII_ADVERTISE
,
203 ADVERTISE_ALL
| ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
);
204 if (ar8xxx_has_gige(priv
))
205 mdiobus_write(bus
, i
, MII_CTRL1000
, ADVERTISE_1000FULL
);
206 mdiobus_write(bus
, i
, MII_BMCR
, BMCR_RESET
| BMCR_ANENABLE
);
209 ar8xxx_phy_poll_reset(bus
);
213 ar8xxx_mii_read32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
)
215 struct mii_bus
*bus
= priv
->mii_bus
;
218 lo
= bus
->read(bus
, phy_id
, regnum
);
219 hi
= bus
->read(bus
, phy_id
, regnum
+ 1);
221 return (hi
<< 16) | lo
;
225 ar8xxx_mii_write32(struct ar8xxx_priv
*priv
, int phy_id
, int regnum
, u32 val
)
227 struct mii_bus
*bus
= priv
->mii_bus
;
231 hi
= (u16
) (val
>> 16);
233 if (priv
->chip
->mii_lo_first
)
235 bus
->write(bus
, phy_id
, regnum
, lo
);
236 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
238 bus
->write(bus
, phy_id
, regnum
+ 1, hi
);
239 bus
->write(bus
, phy_id
, regnum
, lo
);
244 ar8xxx_read(struct ar8xxx_priv
*priv
, int reg
)
246 struct mii_bus
*bus
= priv
->mii_bus
;
250 split_addr((u32
) reg
, &r1
, &r2
, &page
);
252 mutex_lock(&bus
->mdio_lock
);
254 bus
->write(bus
, 0x18, 0, page
);
255 wait_for_page_switch();
256 val
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
258 mutex_unlock(&bus
->mdio_lock
);
264 ar8xxx_write(struct ar8xxx_priv
*priv
, int reg
, u32 val
)
266 struct mii_bus
*bus
= priv
->mii_bus
;
269 split_addr((u32
) reg
, &r1
, &r2
, &page
);
271 mutex_lock(&bus
->mdio_lock
);
273 bus
->write(bus
, 0x18, 0, page
);
274 wait_for_page_switch();
275 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, val
);
277 mutex_unlock(&bus
->mdio_lock
);
281 ar8xxx_rmw(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
283 struct mii_bus
*bus
= priv
->mii_bus
;
287 split_addr((u32
) reg
, &r1
, &r2
, &page
);
289 mutex_lock(&bus
->mdio_lock
);
291 bus
->write(bus
, 0x18, 0, page
);
292 wait_for_page_switch();
294 ret
= ar8xxx_mii_read32(priv
, 0x10 | r2
, r1
);
297 ar8xxx_mii_write32(priv
, 0x10 | r2
, r1
, ret
);
299 mutex_unlock(&bus
->mdio_lock
);
304 ar8xxx_phy_dbg_read(struct ar8xxx_priv
*priv
, int phy_addr
,
305 u16 dbg_addr
, u16
*dbg_data
)
307 struct mii_bus
*bus
= priv
->mii_bus
;
309 mutex_lock(&bus
->mdio_lock
);
310 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
311 *dbg_data
= bus
->read(bus
, phy_addr
, MII_ATH_DBG_DATA
);
312 mutex_unlock(&bus
->mdio_lock
);
316 ar8xxx_phy_dbg_write(struct ar8xxx_priv
*priv
, int phy_addr
,
317 u16 dbg_addr
, u16 dbg_data
)
319 struct mii_bus
*bus
= priv
->mii_bus
;
321 mutex_lock(&bus
->mdio_lock
);
322 bus
->write(bus
, phy_addr
, MII_ATH_DBG_ADDR
, dbg_addr
);
323 bus
->write(bus
, phy_addr
, MII_ATH_DBG_DATA
, dbg_data
);
324 mutex_unlock(&bus
->mdio_lock
);
328 ar8xxx_phy_mmd_prep(struct mii_bus
*bus
, int phy_addr
, u16 addr
, u16 reg
)
330 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
);
331 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, reg
);
332 bus
->write(bus
, phy_addr
, MII_ATH_MMD_ADDR
, addr
| 0x4000);
336 ar8xxx_phy_mmd_write(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
, u16 data
)
338 struct mii_bus
*bus
= priv
->mii_bus
;
340 mutex_lock(&bus
->mdio_lock
);
341 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
342 bus
->write(bus
, phy_addr
, MII_ATH_MMD_DATA
, data
);
343 mutex_unlock(&bus
->mdio_lock
);
347 ar8xxx_phy_mmd_read(struct ar8xxx_priv
*priv
, int phy_addr
, u16 addr
, u16 reg
)
349 struct mii_bus
*bus
= priv
->mii_bus
;
352 mutex_lock(&bus
->mdio_lock
);
353 ar8xxx_phy_mmd_prep(bus
, phy_addr
, addr
, reg
);
354 data
= bus
->read(bus
, phy_addr
, MII_ATH_MMD_DATA
);
355 mutex_unlock(&bus
->mdio_lock
);
361 ar8xxx_reg_wait(struct ar8xxx_priv
*priv
, u32 reg
, u32 mask
, u32 val
,
366 for (i
= 0; i
< timeout
; i
++) {
369 t
= ar8xxx_read(priv
, reg
);
370 if ((t
& mask
) == val
)
373 usleep_range(1000, 2000);
381 ar8xxx_mib_op(struct ar8xxx_priv
*priv
, u32 op
)
383 unsigned mib_func
= priv
->chip
->mib_func
;
386 lockdep_assert_held(&priv
->mib_lock
);
388 /* Capture the hardware statistics for all ports */
389 ar8xxx_rmw(priv
, mib_func
, AR8216_MIB_FUNC
, (op
<< AR8216_MIB_FUNC_S
));
391 /* Wait for the capturing to complete. */
392 ret
= ar8xxx_reg_wait(priv
, mib_func
, AR8216_MIB_BUSY
, 0, 10);
403 ar8xxx_mib_capture(struct ar8xxx_priv
*priv
)
405 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_CAPTURE
);
409 ar8xxx_mib_flush(struct ar8xxx_priv
*priv
)
411 return ar8xxx_mib_op(priv
, AR8216_MIB_FUNC_FLUSH
);
415 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv
*priv
, int port
, bool flush
)
421 WARN_ON(port
>= priv
->dev
.ports
);
423 lockdep_assert_held(&priv
->mib_lock
);
425 base
= priv
->chip
->reg_port_stats_start
+
426 priv
->chip
->reg_port_stats_length
* port
;
428 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
429 for (i
= 0; i
< priv
->chip
->num_mibs
; i
++) {
430 const struct ar8xxx_mib_desc
*mib
;
433 mib
= &priv
->chip
->mib_decs
[i
];
434 t
= ar8xxx_read(priv
, base
+ mib
->offset
);
435 if (mib
->size
== 2) {
438 hi
= ar8xxx_read(priv
, base
+ mib
->offset
+ 4);
451 ar8216_read_port_link(struct ar8xxx_priv
*priv
, int port
,
452 struct switch_port_link
*link
)
457 memset(link
, '\0', sizeof(*link
));
459 status
= priv
->chip
->read_port_status(priv
, port
);
461 link
->aneg
= !!(status
& AR8216_PORT_STATUS_LINK_AUTO
);
463 link
->link
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
467 if (priv
->get_port_link
) {
470 err
= priv
->get_port_link(port
);
479 link
->duplex
= !!(status
& AR8216_PORT_STATUS_DUPLEX
);
480 link
->tx_flow
= !!(status
& AR8216_PORT_STATUS_TXFLOW
);
481 link
->rx_flow
= !!(status
& AR8216_PORT_STATUS_RXFLOW
);
483 if (link
->aneg
&& link
->duplex
&& priv
->chip
->read_port_eee_status
)
484 link
->eee
= priv
->chip
->read_port_eee_status(priv
, port
);
486 speed
= (status
& AR8216_PORT_STATUS_SPEED
) >>
487 AR8216_PORT_STATUS_SPEED_S
;
490 case AR8216_PORT_SPEED_10M
:
491 link
->speed
= SWITCH_PORT_SPEED_10
;
493 case AR8216_PORT_SPEED_100M
:
494 link
->speed
= SWITCH_PORT_SPEED_100
;
496 case AR8216_PORT_SPEED_1000M
:
497 link
->speed
= SWITCH_PORT_SPEED_1000
;
500 link
->speed
= SWITCH_PORT_SPEED_UNKNOWN
;
505 static struct sk_buff
*
506 ar8216_mangle_tx(struct net_device
*dev
, struct sk_buff
*skb
)
508 struct ar8xxx_priv
*priv
= dev
->phy_ptr
;
517 if (unlikely(skb_headroom(skb
) < 2)) {
518 if (pskb_expand_head(skb
, 2, 0, GFP_ATOMIC
) < 0)
522 buf
= skb_push(skb
, 2);
530 dev_kfree_skb_any(skb
);
535 ar8216_mangle_rx(struct net_device
*dev
, struct sk_buff
*skb
)
537 struct ar8xxx_priv
*priv
;
545 /* don't strip the header if vlan mode is disabled */
549 /* strip header, get vlan id */
553 /* check for vlan header presence */
554 if ((buf
[12 + 2] != 0x81) || (buf
[13 + 2] != 0x00))
559 /* no need to fix up packets coming from a tagged source */
560 if (priv
->vlan_tagged
& (1 << port
))
563 /* lookup port vid from local table, the switch passes an invalid vlan id */
564 vlan
= priv
->vlan_id
[priv
->pvid
[port
]];
567 buf
[14 + 2] |= vlan
>> 8;
568 buf
[15 + 2] = vlan
& 0xff;
572 ar8216_wait_bit(struct ar8xxx_priv
*priv
, int reg
, u32 mask
, u32 val
)
578 t
= ar8xxx_read(priv
, reg
);
579 if ((t
& mask
) == val
)
589 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
590 (unsigned int) reg
, t
, mask
, val
);
595 ar8216_vtu_op(struct ar8xxx_priv
*priv
, u32 op
, u32 val
)
597 if (ar8216_wait_bit(priv
, AR8216_REG_VTU
, AR8216_VTU_ACTIVE
, 0))
599 if ((op
& AR8216_VTU_OP
) == AR8216_VTU_OP_LOAD
) {
600 val
&= AR8216_VTUDATA_MEMBER
;
601 val
|= AR8216_VTUDATA_VALID
;
602 ar8xxx_write(priv
, AR8216_REG_VTU_DATA
, val
);
604 op
|= AR8216_VTU_ACTIVE
;
605 ar8xxx_write(priv
, AR8216_REG_VTU
, op
);
609 ar8216_vtu_flush(struct ar8xxx_priv
*priv
)
611 ar8216_vtu_op(priv
, AR8216_VTU_OP_FLUSH
, 0);
615 ar8216_vtu_load_vlan(struct ar8xxx_priv
*priv
, u32 vid
, u32 port_mask
)
619 op
= AR8216_VTU_OP_LOAD
| (vid
<< AR8216_VTU_VID_S
);
620 ar8216_vtu_op(priv
, op
, port_mask
);
624 ar8216_atu_flush(struct ar8xxx_priv
*priv
)
628 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
630 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_OP_FLUSH
|
637 ar8216_atu_flush_port(struct ar8xxx_priv
*priv
, int port
)
642 ret
= ar8216_wait_bit(priv
, AR8216_REG_ATU_FUNC0
, AR8216_ATU_ACTIVE
, 0);
644 t
= (port
<< AR8216_ATU_PORT_NUM_S
) | AR8216_ATU_OP_FLUSH_PORT
;
645 t
|= AR8216_ATU_ACTIVE
;
646 ar8xxx_write(priv
, AR8216_REG_ATU_FUNC0
, t
);
653 ar8216_read_port_status(struct ar8xxx_priv
*priv
, int port
)
655 return ar8xxx_read(priv
, AR8216_REG_PORT_STATUS(port
));
659 __ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
,
667 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
668 if (priv
->vlan_tagged
& (1 << port
))
669 egress
= AR8216_OUT_ADD_VLAN
;
671 egress
= AR8216_OUT_STRIP_VLAN
;
672 ingress
= AR8216_IN_SECURE
;
675 egress
= AR8216_OUT_KEEP
;
676 ingress
= AR8216_IN_PORT_ONLY
;
679 header
= ath_hdr_en
? AR8216_PORT_CTRL_HEADER
: 0;
681 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
682 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
683 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
684 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
685 AR8216_PORT_CTRL_LEARN
| header
|
686 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
687 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
689 ar8xxx_rmw(priv
, AR8216_REG_PORT_VLAN(port
),
690 AR8216_PORT_VLAN_DEST_PORTS
| AR8216_PORT_VLAN_MODE
|
691 AR8216_PORT_VLAN_DEFAULT_ID
,
692 (members
<< AR8216_PORT_VLAN_DEST_PORTS_S
) |
693 (ingress
<< AR8216_PORT_VLAN_MODE_S
) |
694 (pvid
<< AR8216_PORT_VLAN_DEFAULT_ID_S
));
698 ar8216_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
700 return __ar8216_setup_port(priv
, port
, members
,
701 chip_is_ar8216(priv
) && priv
->vlan
&&
702 port
== AR8216_PORT_CPU
);
706 ar8216_hw_init(struct ar8xxx_priv
*priv
)
708 if (priv
->initialized
)
711 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
712 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
714 ar8xxx_phy_init(priv
);
716 priv
->initialized
= true;
721 ar8216_init_globals(struct ar8xxx_priv
*priv
)
723 /* standard atheros magic */
724 ar8xxx_write(priv
, 0x38, 0xc000050e);
726 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
727 AR8216_GCTRL_MTU
, 1518 + 8 + 2);
731 __ar8216_init_port(struct ar8xxx_priv
*priv
, int port
,
732 bool cpu_ge
, bool flow_en
)
734 /* Enable port learning and tx */
735 ar8xxx_write(priv
, AR8216_REG_PORT_CTRL(port
),
736 AR8216_PORT_CTRL_LEARN
|
737 (4 << AR8216_PORT_CTRL_STATE_S
));
739 ar8xxx_write(priv
, AR8216_REG_PORT_VLAN(port
), 0);
741 if (port
== AR8216_PORT_CPU
) {
742 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
743 AR8216_PORT_STATUS_LINK_UP
|
744 (cpu_ge
? AR8216_PORT_SPEED_1000M
: AR8216_PORT_SPEED_100M
) |
745 AR8216_PORT_STATUS_TXMAC
|
746 AR8216_PORT_STATUS_RXMAC
|
747 (flow_en
? AR8216_PORT_STATUS_RXFLOW
: 0) |
748 (flow_en
? AR8216_PORT_STATUS_TXFLOW
: 0) |
749 AR8216_PORT_STATUS_DUPLEX
);
751 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(port
),
752 AR8216_PORT_STATUS_LINK_AUTO
);
757 ar8216_init_port(struct ar8xxx_priv
*priv
, int port
)
759 __ar8216_init_port(priv
, port
, ar8xxx_has_gige(priv
),
760 chip_is_ar8316(priv
));
764 ar8216_wait_atu_ready(struct ar8xxx_priv
*priv
, u16 r2
, u16 r1
)
768 while (ar8xxx_mii_read32(priv
, r2
, r1
) & AR8216_ATU_ACTIVE
&& --timeout
) {
774 pr_err("ar8216: timeout waiting for atu to become ready\n");
777 static void ar8216_get_arl_entry(struct ar8xxx_priv
*priv
,
778 struct arl_entry
*a
, u32
*status
, enum arl_op op
)
780 struct mii_bus
*bus
= priv
->mii_bus
;
782 u16 r1_func0
, r1_func1
, r1_func2
;
783 u32 t
, val0
, val1
, val2
;
785 split_addr(AR8216_REG_ATU_FUNC0
, &r1_func0
, &r2
, &page
);
788 r1_func1
= (AR8216_REG_ATU_FUNC1
>> 1) & 0x1e;
789 r1_func2
= (AR8216_REG_ATU_FUNC2
>> 1) & 0x1e;
792 case AR8XXX_ARL_INITIALIZE
:
793 /* all ATU registers are on the same page
794 * therefore set page only once
796 bus
->write(bus
, 0x18, 0, page
);
797 wait_for_page_switch();
799 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
801 ar8xxx_mii_write32(priv
, r2
, r1_func0
, AR8216_ATU_OP_GET_NEXT
);
802 ar8xxx_mii_write32(priv
, r2
, r1_func1
, 0);
803 ar8xxx_mii_write32(priv
, r2
, r1_func2
, 0);
805 case AR8XXX_ARL_GET_NEXT
:
806 t
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
807 t
|= AR8216_ATU_ACTIVE
;
808 ar8xxx_mii_write32(priv
, r2
, r1_func0
, t
);
809 ar8216_wait_atu_ready(priv
, r2
, r1_func0
);
811 val0
= ar8xxx_mii_read32(priv
, r2
, r1_func0
);
812 val1
= ar8xxx_mii_read32(priv
, r2
, r1_func1
);
813 val2
= ar8xxx_mii_read32(priv
, r2
, r1_func2
);
815 *status
= (val2
& AR8216_ATU_STATUS
) >> AR8216_ATU_STATUS_S
;
819 a
->portmap
= (val2
& AR8216_ATU_PORTS
) >> AR8216_ATU_PORTS_S
;
820 a
->mac
[0] = (val0
& AR8216_ATU_ADDR5
) >> AR8216_ATU_ADDR5_S
;
821 a
->mac
[1] = (val0
& AR8216_ATU_ADDR4
) >> AR8216_ATU_ADDR4_S
;
822 a
->mac
[2] = (val1
& AR8216_ATU_ADDR3
) >> AR8216_ATU_ADDR3_S
;
823 a
->mac
[3] = (val1
& AR8216_ATU_ADDR2
) >> AR8216_ATU_ADDR2_S
;
824 a
->mac
[4] = (val1
& AR8216_ATU_ADDR1
) >> AR8216_ATU_ADDR1_S
;
825 a
->mac
[5] = (val1
& AR8216_ATU_ADDR0
) >> AR8216_ATU_ADDR0_S
;
831 ar8216_phy_read(struct ar8xxx_priv
*priv
, int addr
, int regnum
)
836 if (addr
>= AR8216_NUM_PORTS
)
838 t
= (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
839 (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
840 AR8216_MDIO_CTRL_MASTER_EN
|
841 AR8216_MDIO_CTRL_BUSY
|
842 AR8216_MDIO_CTRL_CMD_READ
;
844 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
845 err
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
846 AR8216_MDIO_CTRL_BUSY
, 0, 5);
848 val
= ar8xxx_read(priv
, AR8216_REG_MDIO_CTRL
);
850 return val
& AR8216_MDIO_CTRL_DATA_M
;
854 ar8216_phy_write(struct ar8xxx_priv
*priv
, int addr
, int regnum
, u16 val
)
859 if (addr
>= AR8216_NUM_PORTS
)
862 t
= (addr
<< AR8216_MDIO_CTRL_PHY_ADDR_S
) |
863 (regnum
<< AR8216_MDIO_CTRL_REG_ADDR_S
) |
864 AR8216_MDIO_CTRL_MASTER_EN
|
865 AR8216_MDIO_CTRL_BUSY
|
866 AR8216_MDIO_CTRL_CMD_WRITE
|
869 ar8xxx_write(priv
, AR8216_REG_MDIO_CTRL
, t
);
870 ret
= ar8xxx_reg_wait(priv
, AR8216_REG_MDIO_CTRL
,
871 AR8216_MDIO_CTRL_BUSY
, 0, 5);
877 ar8229_hw_init(struct ar8xxx_priv
*priv
)
881 if (priv
->initialized
)
884 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
885 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
887 phy_if_mode
= of_get_phy_mode(priv
->pdev
->of_node
);
889 if (phy_if_mode
== PHY_INTERFACE_MODE_GMII
) {
890 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
891 AR8229_OPER_MODE0_MAC_GMII_EN
);
892 } else if (phy_if_mode
== PHY_INTERFACE_MODE_MII
) {
893 ar8xxx_write(priv
, AR8229_REG_OPER_MODE0
,
894 AR8229_OPER_MODE0_PHY_MII_EN
);
896 pr_err("ar8229: unsupported mii mode\n");
900 if (priv
->port4_phy
) {
901 ar8xxx_write(priv
, AR8229_REG_OPER_MODE1
,
902 AR8229_REG_OPER_MODE1_PHY4_MII_EN
);
903 /* disable port5 to prevent mii conflict */
904 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
907 ar8xxx_phy_init(priv
);
909 priv
->initialized
= true;
914 ar8229_init_globals(struct ar8xxx_priv
*priv
)
917 /* Enable CPU port, and disable mirror port */
918 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
919 AR8216_GLOBAL_CPUPORT_EN
|
920 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
922 /* Setup TAG priority mapping */
923 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
925 /* Enable aging, MAC replacing */
926 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
927 0x2b /* 5 min age time */ |
928 AR8216_ATU_CTRL_AGE_EN
|
929 AR8216_ATU_CTRL_LEARN_CHANGE
);
931 /* Enable ARP frame acknowledge */
932 ar8xxx_reg_set(priv
, AR8229_REG_QM_CTRL
,
933 AR8229_QM_CTRL_ARP_EN
);
935 /* Enable Broadcast/Multicast frames transmitted to the CPU */
936 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
937 AR8229_FLOOD_MASK_BC_DP(0) |
938 AR8229_FLOOD_MASK_MC_DP(0));
941 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
942 AR8236_GCTRL_MTU
, AR8236_GCTRL_MTU
);
944 /* Enable MIB counters */
945 ar8xxx_reg_set(priv
, AR8216_REG_MIB_FUNC
,
948 /* setup Service TAG */
949 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
953 ar8229_init_port(struct ar8xxx_priv
*priv
, int port
)
955 __ar8216_init_port(priv
, port
, true, true);
960 ar7240sw_hw_init(struct ar8xxx_priv
*priv
)
962 if (priv
->initialized
)
965 ar8xxx_write(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
);
966 ar8xxx_reg_wait(priv
, AR8216_REG_CTRL
, AR8216_CTRL_RESET
, 0, 1000);
969 /* disable port5 to prevent mii conflict */
970 ar8xxx_write(priv
, AR8216_REG_PORT_STATUS(5), 0);
972 ar8xxx_phy_init(priv
);
974 priv
->initialized
= true;
979 ar7240sw_init_globals(struct ar8xxx_priv
*priv
)
982 /* Enable CPU port, and disable mirror port */
983 ar8xxx_write(priv
, AR8216_REG_GLOBAL_CPUPORT
,
984 AR8216_GLOBAL_CPUPORT_EN
|
985 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
987 /* Setup TAG priority mapping */
988 ar8xxx_write(priv
, AR8216_REG_TAG_PRIORITY
, 0xfa50);
990 /* Enable ARP frame acknowledge, aging, MAC replacing */
991 ar8xxx_write(priv
, AR8216_REG_ATU_CTRL
,
992 AR8216_ATU_CTRL_RESERVED
|
993 0x2b /* 5 min age time */ |
994 AR8216_ATU_CTRL_AGE_EN
|
995 AR8216_ATU_CTRL_ARP_EN
|
996 AR8216_ATU_CTRL_LEARN_CHANGE
);
998 /* Enable Broadcast frames transmitted to the CPU */
999 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
1000 AR8236_FM_CPU_BROADCAST_EN
);
1003 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1007 /* setup Service TAG */
1008 ar8xxx_rmw(priv
, AR8216_REG_SERVICE_TAG
, AR8216_SERVICE_TAG_M
, 0);
1012 ar7240sw_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1014 return __ar8216_setup_port(priv
, port
, members
, false);
1018 ar8236_setup_port(struct ar8xxx_priv
*priv
, int port
, u32 members
)
1020 u32 egress
, ingress
;
1024 pvid
= priv
->vlan_id
[priv
->pvid
[port
]];
1025 if (priv
->vlan_tagged
& (1 << port
))
1026 egress
= AR8216_OUT_ADD_VLAN
;
1028 egress
= AR8216_OUT_STRIP_VLAN
;
1029 ingress
= AR8216_IN_SECURE
;
1032 egress
= AR8216_OUT_KEEP
;
1033 ingress
= AR8216_IN_PORT_ONLY
;
1036 ar8xxx_rmw(priv
, AR8216_REG_PORT_CTRL(port
),
1037 AR8216_PORT_CTRL_LEARN
| AR8216_PORT_CTRL_VLAN_MODE
|
1038 AR8216_PORT_CTRL_SINGLE_VLAN
| AR8216_PORT_CTRL_STATE
|
1039 AR8216_PORT_CTRL_HEADER
| AR8216_PORT_CTRL_LEARN_LOCK
,
1040 AR8216_PORT_CTRL_LEARN
|
1041 (egress
<< AR8216_PORT_CTRL_VLAN_MODE_S
) |
1042 (AR8216_PORT_STATE_FORWARD
<< AR8216_PORT_CTRL_STATE_S
));
1044 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN(port
),
1045 AR8236_PORT_VLAN_DEFAULT_ID
,
1046 (pvid
<< AR8236_PORT_VLAN_DEFAULT_ID_S
));
1048 ar8xxx_rmw(priv
, AR8236_REG_PORT_VLAN2(port
),
1049 AR8236_PORT_VLAN2_VLAN_MODE
|
1050 AR8236_PORT_VLAN2_MEMBER
,
1051 (ingress
<< AR8236_PORT_VLAN2_VLAN_MODE_S
) |
1052 (members
<< AR8236_PORT_VLAN2_MEMBER_S
));
1056 ar8236_init_globals(struct ar8xxx_priv
*priv
)
1058 /* enable jumbo frames */
1059 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1060 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1062 /* enable cpu port to receive arp frames */
1063 ar8xxx_reg_set(priv
, AR8216_REG_ATU_CTRL
,
1064 AR8236_ATU_CTRL_RES
);
1066 /* enable cpu port to receive multicast and broadcast frames */
1067 ar8xxx_reg_set(priv
, AR8216_REG_FLOOD_MASK
,
1068 AR8236_FM_CPU_BROADCAST_EN
| AR8236_FM_CPU_BCAST_FWD_EN
);
1070 /* Enable MIB counters */
1071 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1072 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1077 ar8316_hw_init(struct ar8xxx_priv
*priv
)
1081 val
= ar8xxx_read(priv
, AR8316_REG_POSTRIP
);
1083 if (priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1084 if (priv
->port4_phy
) {
1085 /* value taken from Ubiquiti RouterStation Pro */
1086 newval
= 0x81461bea;
1087 pr_info("ar8316: Using port 4 as PHY\n");
1089 newval
= 0x01261be2;
1090 pr_info("ar8316: Using port 4 as switch port\n");
1092 } else if (priv
->phy
->interface
== PHY_INTERFACE_MODE_GMII
) {
1093 /* value taken from AVM Fritz!Box 7390 sources */
1094 newval
= 0x010e5b71;
1096 /* no known value for phy interface */
1097 pr_err("ar8316: unsupported mii mode: %d.\n",
1098 priv
->phy
->interface
);
1105 ar8xxx_write(priv
, AR8316_REG_POSTRIP
, newval
);
1107 if (priv
->port4_phy
&&
1108 priv
->phy
->interface
== PHY_INTERFACE_MODE_RGMII
) {
1109 /* work around for phy4 rgmii mode */
1110 ar8xxx_phy_dbg_write(priv
, 4, 0x12, 0x480c);
1112 ar8xxx_phy_dbg_write(priv
, 4, 0x0, 0x824e);
1114 ar8xxx_phy_dbg_write(priv
, 4, 0x5, 0x3d47);
1118 ar8xxx_phy_init(priv
);
1121 priv
->initialized
= true;
1126 ar8316_init_globals(struct ar8xxx_priv
*priv
)
1128 /* standard atheros magic */
1129 ar8xxx_write(priv
, 0x38, 0xc000050e);
1131 /* enable cpu port to receive multicast and broadcast frames */
1132 ar8xxx_write(priv
, AR8216_REG_FLOOD_MASK
, 0x003f003f);
1134 /* enable jumbo frames */
1135 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CTRL
,
1136 AR8316_GCTRL_MTU
, 9018 + 8 + 2);
1138 /* Enable MIB counters */
1139 ar8xxx_rmw(priv
, AR8216_REG_MIB_FUNC
, AR8216_MIB_FUNC
| AR8236_MIB_EN
,
1140 (AR8216_MIB_FUNC_NO_OP
<< AR8216_MIB_FUNC_S
) |
1145 ar8xxx_sw_set_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1146 struct switch_val
*val
)
1148 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1149 priv
->vlan
= !!val
->value
.i
;
1154 ar8xxx_sw_get_vlan(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1155 struct switch_val
*val
)
1157 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1158 val
->value
.i
= priv
->vlan
;
1164 ar8xxx_sw_set_pvid(struct switch_dev
*dev
, int port
, int vlan
)
1166 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1168 /* make sure no invalid PVIDs get set */
1170 if (vlan
< 0 || vlan
>= dev
->vlans
||
1171 port
< 0 || port
>= AR8X16_MAX_PORTS
)
1174 priv
->pvid
[port
] = vlan
;
1179 ar8xxx_sw_get_pvid(struct switch_dev
*dev
, int port
, int *vlan
)
1181 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1183 if (port
< 0 || port
>= AR8X16_MAX_PORTS
)
1186 *vlan
= priv
->pvid
[port
];
1191 ar8xxx_sw_set_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1192 struct switch_val
*val
)
1194 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1196 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1199 priv
->vlan_id
[val
->port_vlan
] = val
->value
.i
;
1204 ar8xxx_sw_get_vid(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1205 struct switch_val
*val
)
1207 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1208 val
->value
.i
= priv
->vlan_id
[val
->port_vlan
];
1213 ar8xxx_sw_get_port_link(struct switch_dev
*dev
, int port
,
1214 struct switch_port_link
*link
)
1216 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1218 ar8216_read_port_link(priv
, port
, link
);
1223 ar8xxx_sw_get_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1225 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1229 if (val
->port_vlan
>= AR8X16_MAX_VLANS
)
1232 ports
= priv
->vlan_table
[val
->port_vlan
];
1234 for (i
= 0; i
< dev
->ports
; i
++) {
1235 struct switch_port
*p
;
1237 if (!(ports
& (1 << i
)))
1240 p
= &val
->value
.ports
[val
->len
++];
1242 if (priv
->vlan_tagged
& (1 << i
))
1243 p
->flags
= (1 << SWITCH_PORT_FLAG_TAGGED
);
1251 ar8xxx_sw_set_ports(struct switch_dev
*dev
, struct switch_val
*val
)
1253 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1254 u8
*vt
= &priv
->vlan_table
[val
->port_vlan
];
1258 for (i
= 0; i
< val
->len
; i
++) {
1259 struct switch_port
*p
= &val
->value
.ports
[i
];
1261 if (p
->flags
& (1 << SWITCH_PORT_FLAG_TAGGED
)) {
1262 priv
->vlan_tagged
|= (1 << p
->id
);
1264 priv
->vlan_tagged
&= ~(1 << p
->id
);
1265 priv
->pvid
[p
->id
] = val
->port_vlan
;
1267 /* make sure that an untagged port does not
1268 * appear in other vlans */
1269 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1270 if (j
== val
->port_vlan
)
1272 priv
->vlan_table
[j
] &= ~(1 << p
->id
);
1282 ar8216_set_mirror_regs(struct ar8xxx_priv
*priv
)
1286 /* reset all mirror registers */
1287 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1288 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1289 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1290 for (port
= 0; port
< AR8216_NUM_PORTS
; port
++) {
1291 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1292 AR8216_PORT_CTRL_MIRROR_RX
);
1294 ar8xxx_reg_clear(priv
, AR8216_REG_PORT_CTRL(port
),
1295 AR8216_PORT_CTRL_MIRROR_TX
);
1298 /* now enable mirroring if necessary */
1299 if (priv
->source_port
>= AR8216_NUM_PORTS
||
1300 priv
->monitor_port
>= AR8216_NUM_PORTS
||
1301 priv
->source_port
== priv
->monitor_port
) {
1305 ar8xxx_rmw(priv
, AR8216_REG_GLOBAL_CPUPORT
,
1306 AR8216_GLOBAL_CPUPORT_MIRROR_PORT
,
1307 (priv
->monitor_port
<< AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S
));
1309 if (priv
->mirror_rx
)
1310 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1311 AR8216_PORT_CTRL_MIRROR_RX
);
1313 if (priv
->mirror_tx
)
1314 ar8xxx_reg_set(priv
, AR8216_REG_PORT_CTRL(priv
->source_port
),
1315 AR8216_PORT_CTRL_MIRROR_TX
);
1319 ar8xxx_age_time_val(int age_time
)
1321 return (age_time
+ AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
/ 2) /
1322 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS
;
1326 ar8xxx_set_age_time(struct ar8xxx_priv
*priv
, int reg
)
1328 u32 age_time
= ar8xxx_age_time_val(priv
->arl_age_time
);
1329 ar8xxx_rmw(priv
, reg
, AR8216_ATU_CTRL_AGE_TIME
, age_time
<< AR8216_ATU_CTRL_AGE_TIME_S
);
1333 ar8xxx_sw_hw_apply(struct switch_dev
*dev
)
1335 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1336 const struct ar8xxx_chip
*chip
= priv
->chip
;
1337 u8 portmask
[AR8X16_MAX_PORTS
];
1340 mutex_lock(&priv
->reg_mutex
);
1341 /* flush all vlan translation unit entries */
1342 priv
->chip
->vtu_flush(priv
);
1344 memset(portmask
, 0, sizeof(portmask
));
1346 /* calculate the port destination masks and load vlans
1347 * into the vlan translation unit */
1348 for (j
= 0; j
< AR8X16_MAX_VLANS
; j
++) {
1349 u8 vp
= priv
->vlan_table
[j
];
1354 for (i
= 0; i
< dev
->ports
; i
++) {
1357 portmask
[i
] |= vp
& ~mask
;
1360 chip
->vtu_load_vlan(priv
, priv
->vlan_id
[j
],
1361 priv
->vlan_table
[j
]);
1365 * isolate all ports, but connect them to the cpu port */
1366 for (i
= 0; i
< dev
->ports
; i
++) {
1367 if (i
== AR8216_PORT_CPU
)
1370 portmask
[i
] = 1 << AR8216_PORT_CPU
;
1371 portmask
[AR8216_PORT_CPU
] |= (1 << i
);
1375 /* update the port destination mask registers and tag settings */
1376 for (i
= 0; i
< dev
->ports
; i
++) {
1377 chip
->setup_port(priv
, i
, portmask
[i
]);
1380 chip
->set_mirror_regs(priv
);
1383 if (chip
->reg_arl_ctrl
)
1384 ar8xxx_set_age_time(priv
, chip
->reg_arl_ctrl
);
1386 mutex_unlock(&priv
->reg_mutex
);
1391 ar8xxx_sw_reset_switch(struct switch_dev
*dev
)
1393 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1394 const struct ar8xxx_chip
*chip
= priv
->chip
;
1397 mutex_lock(&priv
->reg_mutex
);
1398 memset(&priv
->vlan
, 0, sizeof(struct ar8xxx_priv
) -
1399 offsetof(struct ar8xxx_priv
, vlan
));
1401 for (i
= 0; i
< AR8X16_MAX_VLANS
; i
++)
1402 priv
->vlan_id
[i
] = i
;
1404 /* Configure all ports */
1405 for (i
= 0; i
< dev
->ports
; i
++)
1406 chip
->init_port(priv
, i
);
1408 priv
->mirror_rx
= false;
1409 priv
->mirror_tx
= false;
1410 priv
->source_port
= 0;
1411 priv
->monitor_port
= 0;
1412 priv
->arl_age_time
= AR8XXX_DEFAULT_ARL_AGE_TIME
;
1414 chip
->init_globals(priv
);
1415 chip
->atu_flush(priv
);
1417 mutex_unlock(&priv
->reg_mutex
);
1419 return chip
->sw_hw_apply(dev
);
1423 ar8xxx_sw_set_reset_mibs(struct switch_dev
*dev
,
1424 const struct switch_attr
*attr
,
1425 struct switch_val
*val
)
1427 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1431 if (!ar8xxx_has_mib_counters(priv
))
1434 mutex_lock(&priv
->mib_lock
);
1436 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
1437 sizeof(*priv
->mib_stats
);
1438 memset(priv
->mib_stats
, '\0', len
);
1439 ret
= ar8xxx_mib_flush(priv
);
1446 mutex_unlock(&priv
->mib_lock
);
1451 ar8xxx_sw_set_mib_poll_interval(struct switch_dev
*dev
,
1452 const struct switch_attr
*attr
,
1453 struct switch_val
*val
)
1455 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1457 if (!ar8xxx_has_mib_counters(priv
))
1460 ar8xxx_mib_stop(priv
);
1461 priv
->mib_poll_interval
= val
->value
.i
;
1462 ar8xxx_mib_start(priv
);
1468 ar8xxx_sw_get_mib_poll_interval(struct switch_dev
*dev
,
1469 const struct switch_attr
*attr
,
1470 struct switch_val
*val
)
1472 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1474 if (!ar8xxx_has_mib_counters(priv
))
1476 val
->value
.i
= priv
->mib_poll_interval
;
1481 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev
*dev
,
1482 const struct switch_attr
*attr
,
1483 struct switch_val
*val
)
1485 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1487 mutex_lock(&priv
->reg_mutex
);
1488 priv
->mirror_rx
= !!val
->value
.i
;
1489 priv
->chip
->set_mirror_regs(priv
);
1490 mutex_unlock(&priv
->reg_mutex
);
1496 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev
*dev
,
1497 const struct switch_attr
*attr
,
1498 struct switch_val
*val
)
1500 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1501 val
->value
.i
= priv
->mirror_rx
;
1506 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev
*dev
,
1507 const struct switch_attr
*attr
,
1508 struct switch_val
*val
)
1510 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1512 mutex_lock(&priv
->reg_mutex
);
1513 priv
->mirror_tx
= !!val
->value
.i
;
1514 priv
->chip
->set_mirror_regs(priv
);
1515 mutex_unlock(&priv
->reg_mutex
);
1521 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev
*dev
,
1522 const struct switch_attr
*attr
,
1523 struct switch_val
*val
)
1525 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1526 val
->value
.i
= priv
->mirror_tx
;
1531 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev
*dev
,
1532 const struct switch_attr
*attr
,
1533 struct switch_val
*val
)
1535 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1537 mutex_lock(&priv
->reg_mutex
);
1538 priv
->monitor_port
= val
->value
.i
;
1539 priv
->chip
->set_mirror_regs(priv
);
1540 mutex_unlock(&priv
->reg_mutex
);
1546 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev
*dev
,
1547 const struct switch_attr
*attr
,
1548 struct switch_val
*val
)
1550 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1551 val
->value
.i
= priv
->monitor_port
;
1556 ar8xxx_sw_set_mirror_source_port(struct switch_dev
*dev
,
1557 const struct switch_attr
*attr
,
1558 struct switch_val
*val
)
1560 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1562 mutex_lock(&priv
->reg_mutex
);
1563 priv
->source_port
= val
->value
.i
;
1564 priv
->chip
->set_mirror_regs(priv
);
1565 mutex_unlock(&priv
->reg_mutex
);
1571 ar8xxx_sw_get_mirror_source_port(struct switch_dev
*dev
,
1572 const struct switch_attr
*attr
,
1573 struct switch_val
*val
)
1575 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1576 val
->value
.i
= priv
->source_port
;
1581 ar8xxx_sw_set_port_reset_mib(struct switch_dev
*dev
,
1582 const struct switch_attr
*attr
,
1583 struct switch_val
*val
)
1585 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1589 if (!ar8xxx_has_mib_counters(priv
))
1592 port
= val
->port_vlan
;
1593 if (port
>= dev
->ports
)
1596 mutex_lock(&priv
->mib_lock
);
1597 ret
= ar8xxx_mib_capture(priv
);
1601 ar8xxx_mib_fetch_port_stat(priv
, port
, true);
1606 mutex_unlock(&priv
->mib_lock
);
1611 ar8xxx_byte_to_str(char *buf
, int len
, u64 byte
)
1616 if (byte
>= 0x40000000) { /* 1 GiB */
1617 b
= byte
* 10 / 0x40000000;
1619 } else if (byte
>= 0x100000) { /* 1 MiB */
1620 b
= byte
* 10 / 0x100000;
1622 } else if (byte
>= 0x400) { /* 1 KiB */
1623 b
= byte
* 10 / 0x400;
1629 if (strcmp(unit
, "Byte"))
1630 snprintf(buf
, len
, "%lu.%lu %s", b
/ 10, b
% 10, unit
);
1632 snprintf(buf
, len
, "%lu %s", b
, unit
);
1636 ar8xxx_sw_get_port_mib(struct switch_dev
*dev
,
1637 const struct switch_attr
*attr
,
1638 struct switch_val
*val
)
1640 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1641 const struct ar8xxx_chip
*chip
= priv
->chip
;
1642 u64
*mib_stats
, mib_data
;
1645 char *buf
= priv
->buf
;
1647 const char *mib_name
;
1649 bool mib_stats_empty
= true;
1651 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
1654 port
= val
->port_vlan
;
1655 if (port
>= dev
->ports
)
1658 mutex_lock(&priv
->mib_lock
);
1659 ret
= ar8xxx_mib_capture(priv
);
1663 ar8xxx_mib_fetch_port_stat(priv
, port
, false);
1665 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1668 mib_stats
= &priv
->mib_stats
[port
* chip
->num_mibs
];
1669 for (i
= 0; i
< chip
->num_mibs
; i
++) {
1670 mib_name
= chip
->mib_decs
[i
].name
;
1671 mib_data
= mib_stats
[i
];
1672 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1673 "%-12s: %llu\n", mib_name
, mib_data
);
1674 if ((!strcmp(mib_name
, "TxByte") ||
1675 !strcmp(mib_name
, "RxGoodByte")) &&
1677 ar8xxx_byte_to_str(buf1
, sizeof(buf1
), mib_data
);
1678 --len
; /* discard newline at the end of buf */
1679 len
+= snprintf(buf
+ len
, sizeof(priv
->buf
) - len
,
1682 if (mib_stats_empty
&& mib_data
)
1683 mib_stats_empty
= false;
1686 if (mib_stats_empty
)
1687 len
= snprintf(buf
, sizeof(priv
->buf
), "No MIB data");
1695 mutex_unlock(&priv
->mib_lock
);
1700 ar8xxx_sw_set_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1701 struct switch_val
*val
)
1703 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1704 int age_time
= val
->value
.i
;
1710 age_time_val
= ar8xxx_age_time_val(age_time
);
1711 if (age_time_val
== 0 || age_time_val
> 0xffff)
1714 priv
->arl_age_time
= age_time
;
1719 ar8xxx_sw_get_arl_age_time(struct switch_dev
*dev
, const struct switch_attr
*attr
,
1720 struct switch_val
*val
)
1722 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1723 val
->value
.i
= priv
->arl_age_time
;
1728 ar8xxx_sw_get_arl_table(struct switch_dev
*dev
,
1729 const struct switch_attr
*attr
,
1730 struct switch_val
*val
)
1732 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1733 struct mii_bus
*bus
= priv
->mii_bus
;
1734 const struct ar8xxx_chip
*chip
= priv
->chip
;
1735 char *buf
= priv
->arl_buf
;
1736 int i
, j
, k
, len
= 0;
1737 struct arl_entry
*a
, *a1
;
1740 if (!chip
->get_arl_entry
)
1743 mutex_lock(&priv
->reg_mutex
);
1744 mutex_lock(&bus
->mdio_lock
);
1746 chip
->get_arl_entry(priv
, NULL
, NULL
, AR8XXX_ARL_INITIALIZE
);
1748 for(i
= 0; i
< AR8XXX_NUM_ARL_RECORDS
; ++i
) {
1749 a
= &priv
->arl_table
[i
];
1751 chip
->get_arl_entry(priv
, a
, &status
, AR8XXX_ARL_GET_NEXT
);
1757 * ARL table can include multiple valid entries
1758 * per MAC, just with differing status codes
1760 for (j
= 0; j
< i
; ++j
) {
1761 a1
= &priv
->arl_table
[j
];
1762 if (!memcmp(a
->mac
, a1
->mac
, sizeof(a
->mac
))) {
1763 /* ignore ports already seen in former entry */
1764 a
->portmap
&= ~a1
->portmap
;
1771 mutex_unlock(&bus
->mdio_lock
);
1773 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1774 "address resolution table\n");
1776 if (i
== AR8XXX_NUM_ARL_RECORDS
)
1777 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1778 "Too many entries found, displaying the first %d only!\n",
1779 AR8XXX_NUM_ARL_RECORDS
);
1781 for (j
= 0; j
< priv
->dev
.ports
; ++j
) {
1782 for (k
= 0; k
< i
; ++k
) {
1783 a
= &priv
->arl_table
[k
];
1784 if (!(a
->portmap
& BIT(j
)))
1786 len
+= snprintf(buf
+ len
, sizeof(priv
->arl_buf
) - len
,
1787 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1789 a
->mac
[5], a
->mac
[4], a
->mac
[3],
1790 a
->mac
[2], a
->mac
[1], a
->mac
[0]);
1797 mutex_unlock(&priv
->reg_mutex
);
1803 ar8xxx_sw_set_flush_arl_table(struct switch_dev
*dev
,
1804 const struct switch_attr
*attr
,
1805 struct switch_val
*val
)
1807 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1810 mutex_lock(&priv
->reg_mutex
);
1811 ret
= priv
->chip
->atu_flush(priv
);
1812 mutex_unlock(&priv
->reg_mutex
);
1818 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev
*dev
,
1819 const struct switch_attr
*attr
,
1820 struct switch_val
*val
)
1822 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1825 port
= val
->port_vlan
;
1826 if (port
>= dev
->ports
)
1829 mutex_lock(&priv
->reg_mutex
);
1830 ret
= priv
->chip
->atu_flush_port(priv
, port
);
1831 mutex_unlock(&priv
->reg_mutex
);
1837 ar8xxx_sw_get_port_stats(struct switch_dev
*dev
, int port
,
1838 struct switch_port_stats
*stats
)
1840 struct ar8xxx_priv
*priv
= swdev_to_ar8xxx(dev
);
1843 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
1846 if (!(priv
->chip
->mib_rxb_id
|| priv
->chip
->mib_txb_id
))
1849 if (port
>= dev
->ports
)
1852 mutex_lock(&priv
->mib_lock
);
1854 mib_stats
= &priv
->mib_stats
[port
* priv
->chip
->num_mibs
];
1856 stats
->tx_bytes
= mib_stats
[priv
->chip
->mib_txb_id
];
1857 stats
->rx_bytes
= mib_stats
[priv
->chip
->mib_rxb_id
];
1859 mutex_unlock(&priv
->mib_lock
);
1864 ar8xxx_phy_read(struct mii_bus
*bus
, int phy_addr
, int reg_addr
)
1866 struct ar8xxx_priv
*priv
= bus
->priv
;
1867 return priv
->chip
->phy_read(priv
, phy_addr
, reg_addr
);
1871 ar8xxx_phy_write(struct mii_bus
*bus
, int phy_addr
, int reg_addr
,
1874 struct ar8xxx_priv
*priv
= bus
->priv
;
1875 return priv
->chip
->phy_write(priv
, phy_addr
, reg_addr
, reg_val
);
1878 static const struct switch_attr ar8xxx_sw_attr_globals
[] = {
1880 .type
= SWITCH_TYPE_INT
,
1881 .name
= "enable_vlan",
1882 .description
= "Enable VLAN mode",
1883 .set
= ar8xxx_sw_set_vlan
,
1884 .get
= ar8xxx_sw_get_vlan
,
1888 .type
= SWITCH_TYPE_NOVAL
,
1889 .name
= "reset_mibs",
1890 .description
= "Reset all MIB counters",
1891 .set
= ar8xxx_sw_set_reset_mibs
,
1894 .type
= SWITCH_TYPE_INT
,
1895 .name
= "ar8xxx_mib_poll_interval",
1896 .description
= "MIB polling interval in msecs (0 to disable)",
1897 .set
= ar8xxx_sw_set_mib_poll_interval
,
1898 .get
= ar8xxx_sw_get_mib_poll_interval
1901 .type
= SWITCH_TYPE_INT
,
1902 .name
= "enable_mirror_rx",
1903 .description
= "Enable mirroring of RX packets",
1904 .set
= ar8xxx_sw_set_mirror_rx_enable
,
1905 .get
= ar8xxx_sw_get_mirror_rx_enable
,
1909 .type
= SWITCH_TYPE_INT
,
1910 .name
= "enable_mirror_tx",
1911 .description
= "Enable mirroring of TX packets",
1912 .set
= ar8xxx_sw_set_mirror_tx_enable
,
1913 .get
= ar8xxx_sw_get_mirror_tx_enable
,
1917 .type
= SWITCH_TYPE_INT
,
1918 .name
= "mirror_monitor_port",
1919 .description
= "Mirror monitor port",
1920 .set
= ar8xxx_sw_set_mirror_monitor_port
,
1921 .get
= ar8xxx_sw_get_mirror_monitor_port
,
1922 .max
= AR8216_NUM_PORTS
- 1
1925 .type
= SWITCH_TYPE_INT
,
1926 .name
= "mirror_source_port",
1927 .description
= "Mirror source port",
1928 .set
= ar8xxx_sw_set_mirror_source_port
,
1929 .get
= ar8xxx_sw_get_mirror_source_port
,
1930 .max
= AR8216_NUM_PORTS
- 1
1933 .type
= SWITCH_TYPE_STRING
,
1934 .name
= "arl_table",
1935 .description
= "Get ARL table",
1937 .get
= ar8xxx_sw_get_arl_table
,
1940 .type
= SWITCH_TYPE_NOVAL
,
1941 .name
= "flush_arl_table",
1942 .description
= "Flush ARL table",
1943 .set
= ar8xxx_sw_set_flush_arl_table
,
1947 const struct switch_attr ar8xxx_sw_attr_port
[] = {
1949 .type
= SWITCH_TYPE_NOVAL
,
1950 .name
= "reset_mib",
1951 .description
= "Reset single port MIB counters",
1952 .set
= ar8xxx_sw_set_port_reset_mib
,
1955 .type
= SWITCH_TYPE_STRING
,
1957 .description
= "Get port's MIB counters",
1959 .get
= ar8xxx_sw_get_port_mib
,
1962 .type
= SWITCH_TYPE_NOVAL
,
1963 .name
= "flush_arl_table",
1964 .description
= "Flush port's ARL table entries",
1965 .set
= ar8xxx_sw_set_flush_port_arl_table
,
1969 const struct switch_attr ar8xxx_sw_attr_vlan
[1] = {
1971 .type
= SWITCH_TYPE_INT
,
1973 .description
= "VLAN ID (0-4094)",
1974 .set
= ar8xxx_sw_set_vid
,
1975 .get
= ar8xxx_sw_get_vid
,
1980 static const struct switch_dev_ops ar8xxx_sw_ops
= {
1982 .attr
= ar8xxx_sw_attr_globals
,
1983 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_globals
),
1986 .attr
= ar8xxx_sw_attr_port
,
1987 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_port
),
1990 .attr
= ar8xxx_sw_attr_vlan
,
1991 .n_attr
= ARRAY_SIZE(ar8xxx_sw_attr_vlan
),
1993 .get_port_pvid
= ar8xxx_sw_get_pvid
,
1994 .set_port_pvid
= ar8xxx_sw_set_pvid
,
1995 .get_vlan_ports
= ar8xxx_sw_get_ports
,
1996 .set_vlan_ports
= ar8xxx_sw_set_ports
,
1997 .apply_config
= ar8xxx_sw_hw_apply
,
1998 .reset_switch
= ar8xxx_sw_reset_switch
,
1999 .get_port_link
= ar8xxx_sw_get_port_link
,
2000 .get_port_stats
= ar8xxx_sw_get_port_stats
,
2003 static const struct ar8xxx_chip ar7240sw_chip
= {
2004 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2006 .reg_port_stats_start
= 0x20000,
2007 .reg_port_stats_length
= 0x100,
2008 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2010 .name
= "Atheros AR724X/AR933X built-in",
2011 .ports
= AR7240SW_NUM_PORTS
,
2012 .vlans
= AR8216_NUM_VLANS
,
2013 .swops
= &ar8xxx_sw_ops
,
2015 .hw_init
= ar7240sw_hw_init
,
2016 .init_globals
= ar7240sw_init_globals
,
2017 .init_port
= ar8229_init_port
,
2018 .phy_read
= ar8216_phy_read
,
2019 .phy_write
= ar8216_phy_write
,
2020 .setup_port
= ar7240sw_setup_port
,
2021 .read_port_status
= ar8216_read_port_status
,
2022 .atu_flush
= ar8216_atu_flush
,
2023 .atu_flush_port
= ar8216_atu_flush_port
,
2024 .vtu_flush
= ar8216_vtu_flush
,
2025 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2026 .set_mirror_regs
= ar8216_set_mirror_regs
,
2027 .get_arl_entry
= ar8216_get_arl_entry
,
2028 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2030 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2031 .mib_decs
= ar8236_mibs
,
2032 .mib_func
= AR8216_REG_MIB_FUNC
,
2033 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2034 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2037 static const struct ar8xxx_chip ar8216_chip
= {
2038 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2040 .reg_port_stats_start
= 0x19000,
2041 .reg_port_stats_length
= 0xa0,
2042 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2044 .name
= "Atheros AR8216",
2045 .ports
= AR8216_NUM_PORTS
,
2046 .vlans
= AR8216_NUM_VLANS
,
2047 .swops
= &ar8xxx_sw_ops
,
2049 .hw_init
= ar8216_hw_init
,
2050 .init_globals
= ar8216_init_globals
,
2051 .init_port
= ar8216_init_port
,
2052 .setup_port
= ar8216_setup_port
,
2053 .read_port_status
= ar8216_read_port_status
,
2054 .atu_flush
= ar8216_atu_flush
,
2055 .atu_flush_port
= ar8216_atu_flush_port
,
2056 .vtu_flush
= ar8216_vtu_flush
,
2057 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2058 .set_mirror_regs
= ar8216_set_mirror_regs
,
2059 .get_arl_entry
= ar8216_get_arl_entry
,
2060 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2062 .num_mibs
= ARRAY_SIZE(ar8216_mibs
),
2063 .mib_decs
= ar8216_mibs
,
2064 .mib_func
= AR8216_REG_MIB_FUNC
,
2065 .mib_rxb_id
= AR8216_MIB_RXB_ID
,
2066 .mib_txb_id
= AR8216_MIB_TXB_ID
,
2069 static const struct ar8xxx_chip ar8229_chip
= {
2070 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2072 .reg_port_stats_start
= 0x20000,
2073 .reg_port_stats_length
= 0x100,
2074 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2076 .name
= "Atheros AR8229",
2077 .ports
= AR8216_NUM_PORTS
,
2078 .vlans
= AR8216_NUM_VLANS
,
2079 .swops
= &ar8xxx_sw_ops
,
2081 .hw_init
= ar8229_hw_init
,
2082 .init_globals
= ar8229_init_globals
,
2083 .init_port
= ar8229_init_port
,
2084 .phy_read
= ar8216_phy_read
,
2085 .phy_write
= ar8216_phy_write
,
2086 .setup_port
= ar8236_setup_port
,
2087 .read_port_status
= ar8216_read_port_status
,
2088 .atu_flush
= ar8216_atu_flush
,
2089 .atu_flush_port
= ar8216_atu_flush_port
,
2090 .vtu_flush
= ar8216_vtu_flush
,
2091 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2092 .set_mirror_regs
= ar8216_set_mirror_regs
,
2093 .get_arl_entry
= ar8216_get_arl_entry
,
2094 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2096 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2097 .mib_decs
= ar8236_mibs
,
2098 .mib_func
= AR8216_REG_MIB_FUNC
,
2099 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2100 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2103 static const struct ar8xxx_chip ar8236_chip
= {
2104 .caps
= AR8XXX_CAP_MIB_COUNTERS
,
2106 .reg_port_stats_start
= 0x20000,
2107 .reg_port_stats_length
= 0x100,
2108 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2110 .name
= "Atheros AR8236",
2111 .ports
= AR8216_NUM_PORTS
,
2112 .vlans
= AR8216_NUM_VLANS
,
2113 .swops
= &ar8xxx_sw_ops
,
2115 .hw_init
= ar8216_hw_init
,
2116 .init_globals
= ar8236_init_globals
,
2117 .init_port
= ar8216_init_port
,
2118 .setup_port
= ar8236_setup_port
,
2119 .read_port_status
= ar8216_read_port_status
,
2120 .atu_flush
= ar8216_atu_flush
,
2121 .atu_flush_port
= ar8216_atu_flush_port
,
2122 .vtu_flush
= ar8216_vtu_flush
,
2123 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2124 .set_mirror_regs
= ar8216_set_mirror_regs
,
2125 .get_arl_entry
= ar8216_get_arl_entry
,
2126 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2128 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2129 .mib_decs
= ar8236_mibs
,
2130 .mib_func
= AR8216_REG_MIB_FUNC
,
2131 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2132 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2135 static const struct ar8xxx_chip ar8316_chip
= {
2136 .caps
= AR8XXX_CAP_GIGE
| AR8XXX_CAP_MIB_COUNTERS
,
2138 .reg_port_stats_start
= 0x20000,
2139 .reg_port_stats_length
= 0x100,
2140 .reg_arl_ctrl
= AR8216_REG_ATU_CTRL
,
2142 .name
= "Atheros AR8316",
2143 .ports
= AR8216_NUM_PORTS
,
2144 .vlans
= AR8X16_MAX_VLANS
,
2145 .swops
= &ar8xxx_sw_ops
,
2147 .hw_init
= ar8316_hw_init
,
2148 .init_globals
= ar8316_init_globals
,
2149 .init_port
= ar8216_init_port
,
2150 .setup_port
= ar8216_setup_port
,
2151 .read_port_status
= ar8216_read_port_status
,
2152 .atu_flush
= ar8216_atu_flush
,
2153 .atu_flush_port
= ar8216_atu_flush_port
,
2154 .vtu_flush
= ar8216_vtu_flush
,
2155 .vtu_load_vlan
= ar8216_vtu_load_vlan
,
2156 .set_mirror_regs
= ar8216_set_mirror_regs
,
2157 .get_arl_entry
= ar8216_get_arl_entry
,
2158 .sw_hw_apply
= ar8xxx_sw_hw_apply
,
2160 .num_mibs
= ARRAY_SIZE(ar8236_mibs
),
2161 .mib_decs
= ar8236_mibs
,
2162 .mib_func
= AR8216_REG_MIB_FUNC
,
2163 .mib_rxb_id
= AR8236_MIB_RXB_ID
,
2164 .mib_txb_id
= AR8236_MIB_TXB_ID
,
2168 ar8xxx_read_id(struct ar8xxx_priv
*priv
)
2174 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2178 id
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2179 for (i
= 0; i
< AR8X16_PROBE_RETRIES
; i
++) {
2182 val
= ar8xxx_read(priv
, AR8216_REG_CTRL
);
2186 t
= val
& (AR8216_CTRL_REVISION
| AR8216_CTRL_VERSION
);
2191 priv
->chip_ver
= (id
& AR8216_CTRL_VERSION
) >> AR8216_CTRL_VERSION_S
;
2192 priv
->chip_rev
= (id
& AR8216_CTRL_REVISION
);
2197 ar8xxx_id_chip(struct ar8xxx_priv
*priv
)
2201 ret
= ar8xxx_read_id(priv
);
2205 switch (priv
->chip_ver
) {
2206 case AR8XXX_VER_AR8216
:
2207 priv
->chip
= &ar8216_chip
;
2209 case AR8XXX_VER_AR8236
:
2210 priv
->chip
= &ar8236_chip
;
2212 case AR8XXX_VER_AR8316
:
2213 priv
->chip
= &ar8316_chip
;
2215 case AR8XXX_VER_AR8327
:
2216 priv
->chip
= &ar8327_chip
;
2218 case AR8XXX_VER_AR8337
:
2219 priv
->chip
= &ar8337_chip
;
2222 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2223 priv
->chip_ver
, priv
->chip_rev
);
2232 ar8xxx_mib_work_func(struct work_struct
*work
)
2234 struct ar8xxx_priv
*priv
;
2237 priv
= container_of(work
, struct ar8xxx_priv
, mib_work
.work
);
2239 mutex_lock(&priv
->mib_lock
);
2241 err
= ar8xxx_mib_capture(priv
);
2245 for (i
= 0; i
< priv
->dev
.ports
; i
++)
2246 ar8xxx_mib_fetch_port_stat(priv
, i
, false);
2249 mutex_unlock(&priv
->mib_lock
);
2250 schedule_delayed_work(&priv
->mib_work
,
2251 msecs_to_jiffies(priv
->mib_poll_interval
));
2255 ar8xxx_mib_init(struct ar8xxx_priv
*priv
)
2259 if (!ar8xxx_has_mib_counters(priv
))
2262 BUG_ON(!priv
->chip
->mib_decs
|| !priv
->chip
->num_mibs
);
2264 len
= priv
->dev
.ports
* priv
->chip
->num_mibs
*
2265 sizeof(*priv
->mib_stats
);
2266 priv
->mib_stats
= kzalloc(len
, GFP_KERNEL
);
2268 if (!priv
->mib_stats
)
2275 ar8xxx_mib_start(struct ar8xxx_priv
*priv
)
2277 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
2280 schedule_delayed_work(&priv
->mib_work
,
2281 msecs_to_jiffies(priv
->mib_poll_interval
));
2285 ar8xxx_mib_stop(struct ar8xxx_priv
*priv
)
2287 if (!ar8xxx_has_mib_counters(priv
) || !priv
->mib_poll_interval
)
2290 cancel_delayed_work_sync(&priv
->mib_work
);
2293 static struct ar8xxx_priv
*
2296 struct ar8xxx_priv
*priv
;
2298 priv
= kzalloc(sizeof(struct ar8xxx_priv
), GFP_KERNEL
);
2302 mutex_init(&priv
->reg_mutex
);
2303 mutex_init(&priv
->mib_lock
);
2304 INIT_DELAYED_WORK(&priv
->mib_work
, ar8xxx_mib_work_func
);
2310 ar8xxx_free(struct ar8xxx_priv
*priv
)
2312 if (priv
->chip
&& priv
->chip
->cleanup
)
2313 priv
->chip
->cleanup(priv
);
2315 kfree(priv
->chip_data
);
2316 kfree(priv
->mib_stats
);
2321 ar8xxx_probe_switch(struct ar8xxx_priv
*priv
)
2323 const struct ar8xxx_chip
*chip
;
2324 struct switch_dev
*swdev
;
2330 swdev
->cpu_port
= AR8216_PORT_CPU
;
2331 swdev
->name
= chip
->name
;
2332 swdev
->vlans
= chip
->vlans
;
2333 swdev
->ports
= chip
->ports
;
2334 swdev
->ops
= chip
->swops
;
2336 ret
= ar8xxx_mib_init(priv
);
2344 ar8xxx_start(struct ar8xxx_priv
*priv
)
2350 ret
= priv
->chip
->hw_init(priv
);
2354 ret
= ar8xxx_sw_reset_switch(&priv
->dev
);
2360 ar8xxx_mib_start(priv
);
2366 ar8xxx_phy_config_init(struct phy_device
*phydev
)
2368 struct ar8xxx_priv
*priv
= phydev
->priv
;
2369 struct net_device
*dev
= phydev
->attached_dev
;
2375 if (priv
->chip
->config_at_probe
)
2376 return ar8xxx_phy_check_aneg(phydev
);
2380 if (phydev
->mdio
.addr
!= 0) {
2381 if (chip_is_ar8316(priv
)) {
2382 /* switch device has been initialized, reinit */
2383 priv
->dev
.ports
= (AR8216_NUM_PORTS
- 1);
2384 priv
->initialized
= false;
2385 priv
->port4_phy
= true;
2386 ar8316_hw_init(priv
);
2393 ret
= ar8xxx_start(priv
);
2397 /* VID fixup only needed on ar8216 */
2398 if (chip_is_ar8216(priv
)) {
2399 dev
->phy_ptr
= priv
;
2400 dev
->priv_flags
|= IFF_NO_IP_ALIGN
;
2401 dev
->eth_mangle_rx
= ar8216_mangle_rx
;
2402 dev
->eth_mangle_tx
= ar8216_mangle_tx
;
2409 ar8xxx_check_link_states(struct ar8xxx_priv
*priv
)
2411 bool link_new
, changed
= false;
2415 mutex_lock(&priv
->reg_mutex
);
2417 for (i
= 0; i
< priv
->dev
.ports
; i
++) {
2418 status
= priv
->chip
->read_port_status(priv
, i
);
2419 link_new
= !!(status
& AR8216_PORT_STATUS_LINK_UP
);
2420 if (link_new
== priv
->link_up
[i
])
2423 priv
->link_up
[i
] = link_new
;
2425 /* flush ARL entries for this port if it went down*/
2427 priv
->chip
->atu_flush_port(priv
, i
);
2428 dev_info(&priv
->phy
->mdio
.dev
, "Port %d is %s\n",
2429 i
, link_new
? "up" : "down");
2432 mutex_unlock(&priv
->reg_mutex
);
2438 ar8xxx_phy_read_status(struct phy_device
*phydev
)
2440 struct ar8xxx_priv
*priv
= phydev
->priv
;
2441 struct switch_port_link link
;
2443 /* check for switch port link changes */
2444 if (phydev
->state
== PHY_CHANGELINK
)
2445 ar8xxx_check_link_states(priv
);
2447 if (phydev
->mdio
.addr
!= 0)
2448 return genphy_read_status(phydev
);
2450 ar8216_read_port_link(priv
, phydev
->mdio
.addr
, &link
);
2451 phydev
->link
= !!link
.link
;
2455 switch (link
.speed
) {
2456 case SWITCH_PORT_SPEED_10
:
2457 phydev
->speed
= SPEED_10
;
2459 case SWITCH_PORT_SPEED_100
:
2460 phydev
->speed
= SPEED_100
;
2462 case SWITCH_PORT_SPEED_1000
:
2463 phydev
->speed
= SPEED_1000
;
2468 phydev
->duplex
= link
.duplex
? DUPLEX_FULL
: DUPLEX_HALF
;
2470 phydev
->state
= PHY_RUNNING
;
2471 netif_carrier_on(phydev
->attached_dev
);
2472 if (phydev
->adjust_link
)
2473 phydev
->adjust_link(phydev
->attached_dev
);
2479 ar8xxx_phy_config_aneg(struct phy_device
*phydev
)
2481 if (phydev
->mdio
.addr
== 0)
2484 return genphy_config_aneg(phydev
);
2487 static const u32 ar8xxx_phy_ids
[] = {
2489 0x004dd034, /* AR8327 */
2490 0x004dd036, /* AR8337 */
2493 0x004dd043, /* AR8236 */
2497 ar8xxx_phy_match(u32 phy_id
)
2501 for (i
= 0; i
< ARRAY_SIZE(ar8xxx_phy_ids
); i
++)
2502 if (phy_id
== ar8xxx_phy_ids
[i
])
2509 ar8xxx_is_possible(struct mii_bus
*bus
)
2511 unsigned int i
, found_phys
= 0;
2513 for (i
= 0; i
< 5; i
++) {
2516 phy_id
= mdiobus_read(bus
, i
, MII_PHYSID1
) << 16;
2517 phy_id
|= mdiobus_read(bus
, i
, MII_PHYSID2
);
2518 if (ar8xxx_phy_match(phy_id
)) {
2520 } else if (phy_id
) {
2521 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2522 dev_name(&bus
->dev
), i
, phy_id
);
2525 return !!found_phys
;
2529 ar8xxx_phy_probe(struct phy_device
*phydev
)
2531 struct ar8xxx_priv
*priv
;
2532 struct switch_dev
*swdev
;
2535 /* skip PHYs at unused adresses */
2536 if (phydev
->mdio
.addr
!= 0 && phydev
->mdio
.addr
!= 3 && phydev
->mdio
.addr
!= 4)
2539 if (!ar8xxx_is_possible(phydev
->mdio
.bus
))
2542 mutex_lock(&ar8xxx_dev_list_lock
);
2543 list_for_each_entry(priv
, &ar8xxx_dev_list
, list
)
2544 if (priv
->mii_bus
== phydev
->mdio
.bus
)
2547 priv
= ar8xxx_create();
2553 priv
->mii_bus
= phydev
->mdio
.bus
;
2554 priv
->pdev
= &phydev
->mdio
.dev
;
2556 ret
= of_property_read_u32(priv
->pdev
->of_node
, "qca,mib-poll-interval",
2557 &priv
->mib_poll_interval
);
2559 priv
->mib_poll_interval
= 0;
2561 ret
= ar8xxx_id_chip(priv
);
2565 ret
= ar8xxx_probe_switch(priv
);
2570 swdev
->alias
= dev_name(&priv
->mii_bus
->dev
);
2571 ret
= register_switch(swdev
, NULL
);
2575 pr_info("%s: %s rev. %u switch registered on %s\n",
2576 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2577 dev_name(&priv
->mii_bus
->dev
));
2579 list_add(&priv
->list
, &ar8xxx_dev_list
);
2584 if (phydev
->mdio
.addr
== 0) {
2585 if (ar8xxx_has_gige(priv
)) {
2586 phydev
->supported
= SUPPORTED_1000baseT_Full
;
2587 phydev
->advertising
= ADVERTISED_1000baseT_Full
;
2589 phydev
->supported
= SUPPORTED_100baseT_Full
;
2590 phydev
->advertising
= ADVERTISED_100baseT_Full
;
2593 if (priv
->chip
->config_at_probe
) {
2596 ret
= ar8xxx_start(priv
);
2598 goto err_unregister_switch
;
2601 if (ar8xxx_has_gige(priv
)) {
2602 phydev
->supported
|= SUPPORTED_1000baseT_Full
;
2603 phydev
->advertising
|= ADVERTISED_1000baseT_Full
;
2605 if (priv
->chip
->phy_rgmii_set
)
2606 priv
->chip
->phy_rgmii_set(priv
, phydev
);
2609 phydev
->priv
= priv
;
2611 mutex_unlock(&ar8xxx_dev_list_lock
);
2615 err_unregister_switch
:
2616 if (--priv
->use_count
)
2619 unregister_switch(&priv
->dev
);
2624 mutex_unlock(&ar8xxx_dev_list_lock
);
2629 ar8xxx_phy_detach(struct phy_device
*phydev
)
2631 struct net_device
*dev
= phydev
->attached_dev
;
2636 dev
->phy_ptr
= NULL
;
2637 dev
->priv_flags
&= ~IFF_NO_IP_ALIGN
;
2638 dev
->eth_mangle_rx
= NULL
;
2639 dev
->eth_mangle_tx
= NULL
;
2643 ar8xxx_phy_remove(struct phy_device
*phydev
)
2645 struct ar8xxx_priv
*priv
= phydev
->priv
;
2650 phydev
->priv
= NULL
;
2652 mutex_lock(&ar8xxx_dev_list_lock
);
2654 if (--priv
->use_count
> 0) {
2655 mutex_unlock(&ar8xxx_dev_list_lock
);
2659 list_del(&priv
->list
);
2660 mutex_unlock(&ar8xxx_dev_list_lock
);
2662 unregister_switch(&priv
->dev
);
2663 ar8xxx_mib_stop(priv
);
2668 ar8xxx_phy_soft_reset(struct phy_device
*phydev
)
2670 /* we don't need an extra reset */
2674 static struct phy_driver ar8xxx_phy_driver
[] = {
2676 .phy_id
= 0x004d0000,
2677 .name
= "Atheros AR8216/AR8236/AR8316",
2678 .phy_id_mask
= 0xffff0000,
2679 .features
= PHY_BASIC_FEATURES
,
2680 .probe
= ar8xxx_phy_probe
,
2681 .remove
= ar8xxx_phy_remove
,
2682 .detach
= ar8xxx_phy_detach
,
2683 .config_init
= ar8xxx_phy_config_init
,
2684 .config_aneg
= ar8xxx_phy_config_aneg
,
2685 .read_status
= ar8xxx_phy_read_status
,
2686 .soft_reset
= ar8xxx_phy_soft_reset
,
2690 static const struct of_device_id ar8xxx_mdiodev_of_match
[] = {
2692 .compatible
= "qca,ar7240sw",
2693 .data
= &ar7240sw_chip
,
2695 .compatible
= "qca,ar8229",
2696 .data
= &ar8229_chip
,
2698 .compatible
= "qca,ar8236",
2699 .data
= &ar8236_chip
,
2701 .compatible
= "qca,ar8327",
2702 .data
= &ar8327_chip
,
2708 ar8xxx_mdiodev_probe(struct mdio_device
*mdiodev
)
2710 const struct of_device_id
*match
;
2711 struct ar8xxx_priv
*priv
;
2712 struct switch_dev
*swdev
;
2713 struct device_node
*mdio_node
;
2716 match
= of_match_device(ar8xxx_mdiodev_of_match
, &mdiodev
->dev
);
2720 priv
= ar8xxx_create();
2724 priv
->mii_bus
= mdiodev
->bus
;
2725 priv
->pdev
= &mdiodev
->dev
;
2726 priv
->chip
= (const struct ar8xxx_chip
*) match
->data
;
2728 ret
= of_property_read_u32(priv
->pdev
->of_node
, "qca,mib-poll-interval",
2729 &priv
->mib_poll_interval
);
2731 priv
->mib_poll_interval
= 0;
2733 ret
= ar8xxx_read_id(priv
);
2737 ret
= ar8xxx_probe_switch(priv
);
2741 if (priv
->chip
->phy_read
&& priv
->chip
->phy_write
) {
2742 priv
->sw_mii_bus
= devm_mdiobus_alloc(&mdiodev
->dev
);
2743 priv
->sw_mii_bus
->name
= "ar8xxx-mdio";
2744 priv
->sw_mii_bus
->read
= ar8xxx_phy_read
;
2745 priv
->sw_mii_bus
->write
= ar8xxx_phy_write
;
2746 priv
->sw_mii_bus
->priv
= priv
;
2747 priv
->sw_mii_bus
->parent
= &mdiodev
->dev
;
2748 snprintf(priv
->sw_mii_bus
->id
, MII_BUS_ID_SIZE
, "%s",
2749 dev_name(&mdiodev
->dev
));
2750 mdio_node
= of_get_child_by_name(priv
->pdev
->of_node
, "mdio-bus");
2751 ret
= of_mdiobus_register(priv
->sw_mii_bus
, mdio_node
);
2757 swdev
->alias
= dev_name(&mdiodev
->dev
);
2759 if (of_property_read_bool(priv
->pdev
->of_node
, "qca,phy4-mii-enable")) {
2760 priv
->port4_phy
= true;
2764 ret
= register_switch(swdev
, NULL
);
2768 pr_info("%s: %s rev. %u switch registered on %s\n",
2769 swdev
->devname
, swdev
->name
, priv
->chip_rev
,
2770 dev_name(&priv
->mii_bus
->dev
));
2772 mutex_lock(&ar8xxx_dev_list_lock
);
2773 list_add(&priv
->list
, &ar8xxx_dev_list
);
2774 mutex_unlock(&ar8xxx_dev_list_lock
);
2778 ret
= ar8xxx_start(priv
);
2780 goto err_unregister_switch
;
2782 dev_set_drvdata(&mdiodev
->dev
, priv
);
2786 err_unregister_switch
:
2787 if (--priv
->use_count
)
2790 unregister_switch(&priv
->dev
);
2798 ar8xxx_mdiodev_remove(struct mdio_device
*mdiodev
)
2800 struct ar8xxx_priv
*priv
= dev_get_drvdata(&mdiodev
->dev
);
2805 mutex_lock(&ar8xxx_dev_list_lock
);
2807 if (--priv
->use_count
> 0) {
2808 mutex_unlock(&ar8xxx_dev_list_lock
);
2812 list_del(&priv
->list
);
2813 mutex_unlock(&ar8xxx_dev_list_lock
);
2815 unregister_switch(&priv
->dev
);
2816 ar8xxx_mib_stop(priv
);
2817 if(priv
->sw_mii_bus
)
2818 mdiobus_unregister(priv
->sw_mii_bus
);
2822 static struct mdio_driver ar8xxx_mdio_driver
= {
2823 .probe
= ar8xxx_mdiodev_probe
,
2824 .remove
= ar8xxx_mdiodev_remove
,
2826 .name
= "ar8xxx-switch",
2827 .of_match_table
= ar8xxx_mdiodev_of_match
,
2831 static int __init
ar8216_init(void)
2835 ret
= phy_drivers_register(ar8xxx_phy_driver
,
2836 ARRAY_SIZE(ar8xxx_phy_driver
),
2841 ret
= mdio_driver_register(&ar8xxx_mdio_driver
);
2843 phy_drivers_unregister(ar8xxx_phy_driver
,
2844 ARRAY_SIZE(ar8xxx_phy_driver
));
2848 module_init(ar8216_init
);
2850 static void __exit
ar8216_exit(void)
2852 mdio_driver_unregister(&ar8xxx_mdio_driver
);
2853 phy_drivers_unregister(ar8xxx_phy_driver
,
2854 ARRAY_SIZE(ar8xxx_phy_driver
));
2856 module_exit(ar8216_exit
);
2858 MODULE_LICENSE("GPL");