#define DANUBE_PMU_PWDCR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x001C))
#define DANUBE_PMU_PWDSR ((u32*)(DANUBE_PMU_BASE_ADDR + 0x0020))
-#define DANUBE_PMU_PWDCR_DMA 0x20
-#define DANUBE_PMU_PWDCR_LED 0x800
-#define DANUBE_PMU_PWDCR_GPT 0x1000
-#define DANUBE_PMU_PWDCR_PPE 0x2000
-#define DANUBE_PMU_PWDCR_FPI 0x4000
-
/*------------ ICU */