Fix VLYNQ device enable for DG834Gv1
authorFelix Fietkau <nbd@openwrt.org>
Tue, 4 Dec 2007 12:49:54 +0000 (12:49 +0000)
committerFelix Fietkau <nbd@openwrt.org>
Tue, 4 Dec 2007 12:49:54 +0000 (12:49 +0000)
commit5dc134c5420579de99dcdbde07882caaac53ec71
treeb51ab642611ad20f6f7976e0d0b87e5ad4f3c30d
parentedc74f8cc3f810b03a39b5f98bd0c3908d5c9303
Fix VLYNQ device enable for DG834Gv1

This patch allows VLYNQ devices on the DG834Gv1 to be successfully
enabled.

Currently the "__vlynq_enable_device" function attempts to set the VLYNQ
device clock divisor to values from 1 through 8 until a link is
successfully established. On the DG834Gv1 (but not the DG834Gv2),
setting the VLYNQ device clock divisor to 1 (full rate) results in all
further VLYNQ operations failing (including software reset), so the
device is never enabled. This patches changes the function to only
attempt divisors 2 through 8, and hence the device is successfully
enabled.

Signed-off-by: Nick Forbes <nick.forbes@huntsworth.com>
---------

SVN-Revision: 9656
target/linux/ar7/files/drivers/vlynq/vlynq.c