--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 4 Sep 2020 18:36:06 +0200
+Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for coherent DMA
+
+It improves performance by eliminating the need for a cache flush on rx and tx
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -357,7 +357,7 @@
+ };
+
+ cci_control2: slave-if@5000 {
+- compatible = "arm,cci-400-ctrl-if";
++ compatible = "arm,cci-400-ctrl-if", "syscon";
+ interface-type = "ace";
+ reg = <0x5000 0x1000>;
+ };
+@@ -965,6 +965,8 @@
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
+ mediatek,ethsys = <ðsys>;
+ mediatek,sgmiisys = <&sgmiisys>;
++ mediatek,cci-control = <&cci_control2>;
++ dma-coherent;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -9,6 +9,7 @@
+ #include <linux/of_device.h>
+ #include <linux/of_mdio.h>
+ #include <linux/of_net.h>
++#include <linux/of_address.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/regmap.h>
+ #include <linux/clk.h>
+@@ -2472,6 +2473,12 @@ static int mtk_hw_init(struct mtk_eth *e
+ if (ret)
+ goto err_disable_pm;
+
++ if (of_dma_is_coherent(eth->dev->of_node)) {
++ u32 mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA;
++
++ regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, mask, mask);
++ }
++
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628)) {
+ ret = device_reset(eth->dev);
+ if (ret) {
+@@ -3074,6 +3081,16 @@ static int mtk_probe(struct platform_dev
+ }
+ }
+
++ if (of_dma_is_coherent(pdev->dev.of_node)) {
++ struct regmap *cci;
++
++ cci = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
++ "mediatek,cci-control");
++ /* enable CPU/bus coherency */
++ if (!IS_ERR(cci))
++ regmap_write(cci, 0, 3);
++ }
++
+ if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
+ eth->sgmii = devm_kzalloc(eth->dev, sizeof(*eth->sgmii),
+ GFP_KERNEL);
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -425,6 +425,11 @@
+ #define RSTCTRL_FE BIT(6)
+ #define RSTCTRL_PPE BIT(31)
+
++/* ethernet dma channel agent map */
++#define ETHSYS_DMA_AG_MAP 0x408
++#define ETHSYS_DMA_AG_MAP_PDMA BIT(0)
++#define ETHSYS_DMA_AG_MAP_QDMA BIT(1)
++
+ /* SGMII subsystem config registers */
+ /* Register to auto-negotiation restart */
+ #define SGMSYS_PCS_CONTROL_1 0x0
--- /dev/null
+From: Felix Fietkau <nbd@nbd.name>
+Date: Fri, 4 Sep 2020 18:42:42 +0200
+Subject: [PATCH] pci: pcie-mediatek: add support for coherent DMA
+
+It improves performance by eliminating the need for a cache flush for DMA on
+attached devices
+
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
++++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+@@ -801,6 +801,8 @@
+ reg = <0 0x1a143000 0 0x1000>;
+ reg-names = "port0";
+ mediatek,pcie-cfg = <&pciecfg>;
++ mediatek,hifsys = <&hifsys>;
++ mediatek,cci-control = <&cci_control2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
+@@ -818,6 +820,7 @@
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
+ status = "disabled";
++ dma-coherent;
+
+ slot0: pcie@0,0 {
+ reg = <0x0000 0 0 0 0>;
+@@ -844,6 +847,8 @@
+ reg = <0 0x1a145000 0 0x1000>;
+ reg-names = "port1";
+ mediatek,pcie-cfg = <&pciecfg>;
++ mediatek,hifsys = <&hifsys>;
++ mediatek,cci-control = <&cci_control2>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
+@@ -862,6 +867,7 @@
+ bus-range = <0x00 0xff>;
+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
+ status = "disabled";
++ dma-coherent;
+
+ slot1: pcie@1,0 {
+ reg = <0x0800 0 0 0 0>;
+@@ -921,6 +927,11 @@
+ };
+ };
+
++ hifsys: syscon@1af00000 {
++ compatible = "mediatek,mt7622-hifsys", "syscon";
++ reg = <0 0x1af00000 0 0x70>;
++ };
++
+ ethsys: syscon@1b000000 {
+ compatible = "mediatek,mt7622-ethsys",
+ "syscon";
+--- a/drivers/pci/controller/pcie-mediatek.c
++++ b/drivers/pci/controller/pcie-mediatek.c
+@@ -20,6 +20,7 @@
+ #include <linux/of_address.h>
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
++#include <linux/of_address.h>
+ #include <linux/pci.h>
+ #include <linux/phy/phy.h>
+ #include <linux/platform_device.h>
+@@ -139,6 +140,11 @@
+ #define PCIE_LINK_STATUS_V2 0x804
+ #define PCIE_PORT_LINKUP_V2 BIT(10)
+
++/* DMA channel mapping */
++#define HIFSYS_DMA_AG_MAP 0x008
++#define HIFSYS_DMA_AG_MAP_PCIE0 BIT(0)
++#define HIFSYS_DMA_AG_MAP_PCIE1 BIT(1)
++
+ struct mtk_pcie_port;
+
+ /**
+@@ -1068,6 +1074,27 @@ static int mtk_pcie_setup(struct mtk_pci
+ }
+ }
+
++ if (of_dma_is_coherent(node)) {
++ struct regmap *con;
++ u32 mask;
++
++ con = syscon_regmap_lookup_by_phandle(node,
++ "mediatek,cci-control");
++ /* enable CPU/bus coherency */
++ if (!IS_ERR(con))
++ regmap_write(con, 0, 3);
++
++ con = syscon_regmap_lookup_by_phandle(node,
++ "mediatek,hifsys");
++ if (IS_ERR(con)) {
++ dev_err(dev, "missing hifsys node\n");
++ return PTR_ERR(con);
++ }
++
++ mask = HIFSYS_DMA_AG_MAP_PCIE0 | HIFSYS_DMA_AG_MAP_PCIE1;
++ regmap_update_bits(con, HIFSYS_DMA_AG_MAP, mask, mask);
++ }
++
+ for_each_available_child_of_node(node, child) {
+ int slot;
+
projects / openwrt / staging / dedeckeh.git / commitdiff