target/linux/adm5120/files/include/asm-mips/mach-adm5120/adm5120_intc.h

   1 /*
   2  *  $Id$
   3  *
   4  *  ADM5120 interrupt controller definitions
   5  *
   6  *  This header file defines the hardware registers of the ADM5120 SoC
   7  *  built-in interrupt controller.
   8  *
   9  *  Copyright (C) 2007 OpenWrt.org
  10  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
  11  *
  12  *  This program is free software; you can redistribute it and/or
  13  *  modify it under the terms of the GNU General Public License
  14  *  as published by the Free Software Foundation; either version 2
  15  *  of the License, or (at your option) any later version.
  16  *
  17  *  This program is distributed in the hope that it will be useful,
  18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  *  GNU General Public License for more details.
  21  *
  22  *  You should have received a copy of the GNU General Public License
  23  *  along with this program; if not, write to the
  24  *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  25  *  Boston, MA  02110-1301, USA.
  26  */
  27
  28 #ifndef _ADM5120_INTC_H_
  29 #define _ADM5120_INTC_H_
  30
  31 /*
  32  * INTC register offsets
  33  */
  34 #define INTC_REG_IRQ_STATUS             0x00 /* Interrupt status after masking */
  35 #define INTC_REG_IRQ_RAW_STATUS         0x04 /* Interrupt status before masking */
  36 #define INTC_REG_IRQ_ENABLE             0x08 /* Used to enable the interrupt sources */
  37 #define INTC_REG_IRQ_ENABLE_CLEAR       0x0C /* Used to disable the interrupt sources */
  38 #define INTC_REG_IRQ_DISABLE            INTC_REG_IRQ_ENABLE_CLEAR
  39 #define INTC_REG_INT_MODE               0x14 /* The interrupt mode of the sources */
  40 #define INTC_REG_FIQ_STATUS             0x18 /* FIQ status */
  41 #define INTC_REG_IRQ_TEST_SOURCE        0x1C
  42 #define INTC_REG_IRQ_SOURCE_SELECT      0x20
  43 #define INTC_REG_INT_LEVEL              0x24
  44
  45 /*
  46  * INTC IRQ numbers
  47  */
  48 #define INTC_IRQ_TIMER  0       /* built in timer */
  49 #define INTC_IRQ_UART0  1       /* built-in UART0 */
  50 #define INTC_IRQ_UART1  2       /* built-in UART1 */
  51 #define INTC_IRQ_USBC   3       /* USB Host Controller */
  52 #define INTC_IRQ_GPIO2  4       /* GPIO line 2 */
  53 #define INTC_IRQ_GPIO4  5       /* GPIO line 4 */
  54 #define INTC_IRQ_PCI0   6       /* PCI slot 2 */
  55 #define INTC_IRQ_PCI1   7       /* PCI slot 3 */
  56 #define INTC_IRQ_PCI2   8       /* PCI slot 4 */
  57 #define INTC_IRQ_SWITCH 9       /* built-in ethernet switch */
  58 #define INTC_IRQ_LAST   INTC_IRQ_SWITCH
  59 #define INTC_IRQ_COUNT  10
  60
  61 /*
  62  * INTC register bits
  63  */
  64 #define INTC_INT_TIMER  ( 1 << INTC_IRQ_TIMER )
  65 #define INTC_INT_UART0  ( 1 << INTC_IRQ_UART0 )
  66 #define INTC_INT_UART1  ( 1 << INTC_IRQ_UART1 )
  67 #define INTC_INT_USBC   ( 1 << INTC_IRQ_USBC )
  68 #define INTC_INT_INTX0  ( 1 << INTC_IRQ_INTX0 )
  69 #define INTC_INT_INTX1  ( 1 << INTC_IRQ_INTX1 )
  70 #define INTC_INT_PCI0   ( 1 << INTC_IRQ_PCI0 )
  71 #define INTC_INT_PCI1   ( 1 << INTC_IRQ_PCI1 )
  72 #define INTC_INT_PCI2   ( 1 << INTC_IRQ_PCI2 )
  73 #define INTC_INT_SWITCH ( 1 << INTC_IRQ_SWITCH )
  74 #define INTC_INT_ALL    (( 1 << INTC_IRQ_COUNT)-1)
  75
  76 #endif /* _ADM5120_INTC_H_ */