target/linux/atheros/files-2.6.28/arch/mips/atheros/ar5312/irq.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003 Atheros Communications, Inc.,  All Rights Reserved.
   7  * Copyright (C) 2006 FON Technology, SL.
   8  * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
   9  * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
  10  */
  11
  12 /*
  13  * Platform devices for Atheros SoCs
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <linux/types.h>
  19 #include <linux/string.h>
  20 #include <linux/kernel.h>
  21 #include <linux/reboot.h>
  22 #include <asm/bootinfo.h>
  23 #include <asm/time.h>
  24 #include <asm/irq.h>
  25 #include <asm/io.h>
  26
  27 #include <ar531x.h>
  28 #include <gpio.h>
  29
  30 /*
  31  * Called when an interrupt is received, this function
  32  * determines exactly which interrupt it was, and it
  33  * invokes the appropriate handler.
  34  *
  35  * Implicitly, we also define interrupt priority by
  36  * choosing which to dispatch first.
  37  */
  38 asmlinkage void ar5312_irq_dispatch(void)
  39 {
  40         int pending = read_c0_status() & read_c0_cause();
  41
  42         if (pending & CAUSEF_IP2)
  43                 do_IRQ(AR5312_IRQ_WLAN0_INTRS);
  44         else if (pending & CAUSEF_IP3)
  45                 do_IRQ(AR5312_IRQ_ENET0_INTRS);
  46         else if (pending & CAUSEF_IP4)
  47                 do_IRQ(AR5312_IRQ_ENET1_INTRS);
  48         else if (pending & CAUSEF_IP5)
  49                 do_IRQ(AR5312_IRQ_WLAN1_INTRS);
  50         else if (pending & CAUSEF_IP6) {
  51                 unsigned int ar531x_misc_intrs = sysRegRead(AR531X_ISR) & sysRegRead(AR531X_IMR);
  52
  53                 if (ar531x_misc_intrs & AR531X_ISR_TIMER) {
  54                         do_IRQ(AR531X_MISC_IRQ_TIMER);
  55                         (void)sysRegRead(AR531X_TIMER);
  56                 } else if (ar531x_misc_intrs & AR531X_ISR_AHBPROC)
  57                         do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
  58                 else if ((ar531x_misc_intrs & AR531X_ISR_UART0))
  59                         do_IRQ(AR531X_MISC_IRQ_UART0);
  60                 else if (ar531x_misc_intrs & AR531X_ISR_WD)
  61                         do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
  62                 else
  63                         do_IRQ(AR531X_MISC_IRQ_NONE);
  64         } else if (pending & CAUSEF_IP7) {
  65                 do_IRQ(AR531X_IRQ_CPU_CLOCK);
  66         }
  67 }
  68
  69
  70 /* Enable the specified AR531X_MISC_IRQ interrupt */
  71 static void
  72 ar5312_misc_intr_enable(unsigned int irq)
  73 {
  74         unsigned int imr;
  75
  76         imr = sysRegRead(AR531X_IMR);
  77         imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
  78         sysRegWrite(AR531X_IMR, imr);
  79         sysRegRead(AR531X_IMR); /* flush write buffer */
  80 }
  81
  82 /* Disable the specified AR531X_MISC_IRQ interrupt */
  83 static void
  84 ar5312_misc_intr_disable(unsigned int irq)
  85 {
  86         unsigned int imr;
  87
  88         imr = sysRegRead(AR531X_IMR);
  89         imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
  90         sysRegWrite(AR531X_IMR, imr);
  91         sysRegRead(AR531X_IMR); /* flush write buffer */
  92 }
  93
  94 /* Turn on the specified AR531X_MISC_IRQ interrupt */
  95 static unsigned int
  96 ar5312_misc_intr_startup(unsigned int irq)
  97 {
  98         ar5312_misc_intr_enable(irq);
  99         return 0;
 100 }
 101
 102 /* Turn off the specified AR531X_MISC_IRQ interrupt */
 103 static void
 104 ar5312_misc_intr_shutdown(unsigned int irq)
 105 {
 106         ar5312_misc_intr_disable(irq);
 107 }
 108
 109 static void
 110 ar5312_misc_intr_ack(unsigned int irq)
 111 {
 112         ar5312_misc_intr_disable(irq);
 113 }
 114
 115 static void
 116 ar5312_misc_intr_end(unsigned int irq)
 117 {
 118         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 119                 ar5312_misc_intr_enable(irq);
 120 }
 121
 122 static struct irq_chip ar5312_misc_intr_controller = {
 123         .typename       = "AR5312 misc",
 124         .startup        = ar5312_misc_intr_startup,
 125         .shutdown       = ar5312_misc_intr_shutdown,
 126         .enable         = ar5312_misc_intr_enable,
 127         .disable        = ar5312_misc_intr_disable,
 128         .ack            = ar5312_misc_intr_ack,
 129         .end            = ar5312_misc_intr_end,
 130 };
 131
 132 static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
 133 {
 134         u32 proc1 = sysRegRead(AR531X_PROC1);
 135         u32 procAddr = sysRegRead(AR531X_PROCADDR); /* clears error state */
 136         u32 dma1 = sysRegRead(AR531X_DMA1);
 137         u32 dmaAddr = sysRegRead(AR531X_DMAADDR);   /* clears error state */
 138
 139         printk("AHB interrupt: PROCADDR=0x%8.8x  PROC1=0x%8.8x  DMAADDR=0x%8.8x  DMA1=0x%8.8x\n",
 140                         procAddr, proc1, dmaAddr, dma1);
 141
 142         machine_restart("AHB error"); /* Catastrophic failure */
 143         return IRQ_HANDLED;
 144 }
 145
 146
 147 static struct irqaction ar5312_ahb_proc_interrupt  = {
 148         .handler        = ar5312_ahb_proc_handler,
 149         .flags          = IRQF_DISABLED,
 150         .name           = "ar5312_ahb_proc_interrupt",
 151 };
 152
 153
 154 static struct irqaction cascade  = {
 155         .handler        = no_action,
 156         .flags          = IRQF_DISABLED,
 157         .name           = "cascade",
 158 };
 159
 160 void __init ar5312_misc_intr_init(int irq_base)
 161 {
 162         int i;
 163
 164         for (i = irq_base; i < irq_base + AR531X_MISC_IRQ_COUNT; i++) {
 165                 irq_desc[i].status = IRQ_DISABLED;
 166                 irq_desc[i].action = NULL;
 167                 irq_desc[i].depth = 1;
 168                 irq_desc[i].chip = &ar5312_misc_intr_controller;
 169         }
 170         setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
 171         setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
 172 }
 173
 174