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atheros: clean up the 2.6.28 port in preparation for pushing it upstream
[openwrt/staging/florian.git] / target / linux / atheros / patches-2.6.28 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -60,6 +60,19 @@ config BCM47XX
4 help
5 Support for BCM47XX based boards
6
7 +config ATHEROS
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select GENERIC_GPIO
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -597,6 +610,7 @@ config WR_PPMC
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/basler/excite/Kconfig"
30 source "arch/mips/emma/Kconfig"
31 --- a/arch/mips/Makefile
32 +++ b/arch/mips/Makefile
33 @@ -278,6 +278,13 @@ libs-$(CONFIG_MIPS_XXS1500) += arch/mips
34 load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000
35
36 #
37 +# Atheros AR5312/AR2312 WiSoC
38 +#
39 +core-$(CONFIG_ATHEROS) += arch/mips/ar231x/
40 +cflags-$(CONFIG_ATHEROS) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
41 +load-$(CONFIG_ATHEROS) += 0xffffffff80041000
42 +
43 +#
44 # Cobalt Server
45 #
46 core-$(CONFIG_MIPS_COBALT) += arch/mips/cobalt/
47 --- /dev/null
48 +++ b/arch/mips/ar231x/Kconfig
49 @@ -0,0 +1,27 @@
50 +config ATHEROS_AR5312
51 + bool "Atheros 5312/2312+ support"
52 + depends on ATHEROS
53 + default y
54 +
55 +config ATHEROS_AR2315
56 + bool "Atheros 2315+ support"
57 + depends on ATHEROS
58 + select DMA_NONCOHERENT
59 + select CEVT_R4K
60 + select CSRC_R4K
61 + select IRQ_CPU
62 + select SYS_HAS_CPU_MIPS32_R1
63 + select SYS_SUPPORTS_32BIT_KERNEL
64 + select SYS_SUPPORTS_BIG_ENDIAN
65 + select GENERIC_GPIO
66 + default y
67 +
68 +config ATHEROS_AR2315_PCI
69 + bool "PCI support"
70 + depends on ATHEROS_AR2315
71 + select HW_HAS_PCI
72 + select PCI
73 + select USB_ARCH_HAS_HCD
74 + select USB_ARCH_HAS_OHCI
75 + select USB_ARCH_HAS_EHCI
76 + default y
77 --- /dev/null
78 +++ b/arch/mips/ar231x/Makefile
79 @@ -0,0 +1,14 @@
80 +#
81 +# This file is subject to the terms and conditions of the GNU General Public
82 +# License. See the file "COPYING" in the main directory of this archive
83 +# for more details.
84 +#
85 +# Copyright (C) 2006 FON Technology, SL.
86 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
87 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
88 +#
89 +
90 +obj-y += board.o prom.o devices.o
91 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
92 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
93 +obj-$(CONFIG_ATHEROS_AR2315_PCI) += pci.o
94 --- /dev/null
95 +++ b/arch/mips/ar231x/board.c
96 @@ -0,0 +1,247 @@
97 +/*
98 + * This file is subject to the terms and conditions of the GNU General Public
99 + * License. See the file "COPYING" in the main directory of this archive
100 + * for more details.
101 + *
102 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
103 + * Copyright (C) 2006 FON Technology, SL.
104 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
105 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
106 + */
107 +
108 +#include <linux/autoconf.h>
109 +#include <linux/init.h>
110 +#include <linux/module.h>
111 +#include <linux/types.h>
112 +#include <linux/string.h>
113 +#include <linux/platform_device.h>
114 +#include <linux/kernel.h>
115 +#include <linux/random.h>
116 +#include <linux/etherdevice.h>
117 +#include <asm/irq_cpu.h>
118 +#include <asm/reboot.h>
119 +#include <asm/io.h>
120 +
121 +#include <ar231x_platform.h>
122 +#include "devices.h"
123 +#include "ar5312.h"
124 +#include "ar2315.h"
125 +
126 +void (*ar231x_irq_dispatch)(void);
127 +
128 +static inline bool
129 +check_radio_magic(u8 *addr)
130 +{
131 + addr += 0x7a; /* offset for flash magic */
132 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5)) {
133 + return 1;
134 + }
135 + return 0;
136 +}
137 +
138 +static inline bool
139 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
140 +{
141 + /* config magic found */
142 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
143 + return 1;
144 +
145 + if (!broken)
146 + return 0;
147 +
148 + if (check_radio_magic(addr + 0xf8))
149 + ar231x_board.radio = addr + 0xf8;
150 + if ((addr < flash_limit + 0x10000) &&
151 + check_radio_magic(addr + 0x10000))
152 + ar231x_board.radio = addr + 0x10000;
153 +
154 + if (ar231x_board.radio) {
155 + /* broken board data detected, use radio data to find the offset,
156 + * user will fix this */
157 + return 1;
158 + }
159 + return 0;
160 +}
161 +
162 +static u8 *
163 +find_board_config(u8 *flash_limit, bool broken)
164 +{
165 + u8 *addr;
166 + int found = 0;
167 +
168 + for (addr = flash_limit - 0x1000;
169 + addr >= flash_limit - 0x30000;
170 + addr -= 0x1000) {
171 +
172 + if (check_board_data(flash_limit, addr, broken)) {
173 + found = 1;
174 + break;
175 + }
176 + }
177 +
178 + if (!found)
179 + addr = NULL;
180 +
181 + return addr;
182 +}
183 +
184 +static u8 *
185 +find_radio_config(u8 *flash_limit, u8 *board_config)
186 +{
187 + int found;
188 + u8 *radio_config;
189 +
190 + /*
191 + * Now find the start of Radio Configuration data, using heuristics:
192 + * Search forward from Board Configuration data by 0x1000 bytes
193 + * at a time until we find non-0xffffffff.
194 + */
195 + found = 0;
196 + for (radio_config = board_config + 0x1000;
197 + (radio_config < flash_limit);
198 + radio_config += 0x1000) {
199 + if ((*(u32 *)radio_config != 0xffffffff) &&
200 + check_radio_magic(radio_config)) {
201 + found = 1;
202 + break;
203 + }
204 + }
205 +
206 + /* AR2316 relocates radio config to new location */
207 + if (!found) {
208 + for (radio_config = board_config + 0xf8;
209 + (radio_config < flash_limit - 0x1000 + 0xf8);
210 + radio_config += 0x1000) {
211 + if ((*(u32 *)radio_config != 0xffffffff) &&
212 + check_radio_magic(radio_config)) {
213 + found = 1;
214 + break;
215 + }
216 + }
217 + }
218 +
219 + if (!found) {
220 + printk("Could not find Radio Configuration data\n");
221 + radio_config = 0;
222 + }
223 +
224 + return (u8 *) radio_config;
225 +}
226 +
227 +int __init
228 +ar231x_find_config(u8 *flash_limit)
229 +{
230 + struct ar231x_boarddata *config;
231 + unsigned int rcfg_size;
232 + int broken_boarddata = 0;
233 + u8 *bcfg, *rcfg;
234 + u8 *board_data;
235 + u8 *radio_data;
236 + u32 offset;
237 +
238 + ar231x_board.config = NULL;
239 + ar231x_board.radio = NULL;
240 + /* Copy the board and radio data to RAM, because accessing the mapped
241 + * memory of the flash directly after booting is not safe */
242 +
243 + /* Try to find valid board and radio data */
244 + bcfg = find_board_config(flash_limit, false);
245 +
246 + /* If that fails, try to at least find valid radio data */
247 + if (!bcfg) {
248 + bcfg = find_board_config(flash_limit, true);
249 + broken_boarddata = 1;
250 + }
251 +
252 + if (!bcfg) {
253 + printk(KERN_WARNING "WARNING: No board configuration data found!\n");
254 + return -ENODEV;
255 + }
256 +
257 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
258 + ar231x_board.config = (struct ar231x_boarddata *) board_data;
259 + memcpy(board_data, bcfg, 0x100);
260 + if (broken_boarddata) {
261 + printk(KERN_WARNING "WARNING: broken board data detected\n");
262 + config = ar231x_board.config;
263 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
264 + printk(KERN_INFO "Fixing up empty mac addresses\n");
265 + random_ether_addr(config->enet0_mac);
266 + random_ether_addr(config->enet1_mac);
267 + }
268 + }
269 +
270 +
271 + /* Radio config starts 0x100 bytes after board config, regardless
272 + * of what the physical layout on the flash chip looks like */
273 +
274 + if (ar231x_board.radio)
275 + rcfg = (u8 *) ar231x_board.radio;
276 + else
277 + rcfg = find_radio_config(flash_limit, bcfg);
278 +
279 + if (!rcfg)
280 + return -ENODEV;
281 +
282 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
283 + ar231x_board.radio = radio_data;
284 + offset = radio_data - board_data;
285 + printk(KERN_INFO "Radio config found at offset 0x%x(0x%x)\n", rcfg - bcfg, offset);
286 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
287 + memcpy(radio_data, rcfg, rcfg_size);
288 +
289 + return 0;
290 +}
291 +
292 +static void
293 +ar231x_halt(void)
294 +{
295 + local_irq_disable();
296 + while (1);
297 +}
298 +
299 +void __init
300 +plat_mem_setup(void)
301 +{
302 + _machine_halt = ar231x_halt;
303 + pm_power_off = ar231x_halt;
304 +
305 + ar5312_plat_setup();
306 + ar2315_plat_setup();
307 +
308 + /* Disable data watchpoints */
309 + write_c0_watchlo0(0);
310 +}
311 +
312 +
313 +asmlinkage void
314 +plat_irq_dispatch(void)
315 +{
316 + ar231x_irq_dispatch();
317 +}
318 +
319 +void __init
320 +plat_time_init(void)
321 +{
322 + ar5312_time_init();
323 + ar2315_time_init();
324 +}
325 +
326 +unsigned int __cpuinit
327 +get_c0_compare_irq(void)
328 +{
329 + return CP0_LEGACY_COMPARE_IRQ;
330 +}
331 +
332 +void __init
333 +arch_init_irq(void)
334 +{
335 + clear_c0_status(ST0_IM);
336 + mips_cpu_irq_init();
337 +
338 + /* Initialize interrupt controllers */
339 + ar5312_irq_init();
340 + ar2315_irq_init();
341 +}
342 +
343 +
344 --- /dev/null
345 +++ b/arch/mips/ar231x/prom.c
346 @@ -0,0 +1,37 @@
347 +/*
348 + * This file is subject to the terms and conditions of the GNU General Public
349 + * License. See the file "COPYING" in the main directory of this archive
350 + * for more details.
351 + *
352 + * Copyright MontaVista Software Inc
353 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
354 + * Copyright (C) 2006 FON Technology, SL.
355 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
356 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
357 + */
358 +
359 +/*
360 + * Prom setup file for ar531x
361 + */
362 +
363 +#include <linux/init.h>
364 +#include <linux/autoconf.h>
365 +#include <linux/kernel.h>
366 +#include <linux/string.h>
367 +#include <linux/mm.h>
368 +#include <linux/bootmem.h>
369 +
370 +#include <asm/bootinfo.h>
371 +#include <asm/addrspace.h>
372 +#include "ar5312.h"
373 +#include "ar2315.h"
374 +
375 +void __init prom_init(void)
376 +{
377 + ar5312_prom_init();
378 + ar2315_prom_init();
379 +}
380 +
381 +void __init prom_free_prom_memory(void)
382 +{
383 +}
384 --- /dev/null
385 +++ b/arch/mips/ar231x/reset.c
386 @@ -0,0 +1,162 @@
387 +#include <linux/module.h>
388 +#include <linux/timer.h>
389 +#include <linux/interrupt.h>
390 +#include <linux/kobject.h>
391 +#include <linux/workqueue.h>
392 +#include <linux/skbuff.h>
393 +#include <linux/netlink.h>
394 +#include <net/sock.h>
395 +#include <asm/uaccess.h>
396 +#include <ar231x.h>
397 +
398 +#define AR531X_RESET_GPIO_IRQ (AR531X_GPIO_IRQ(bcfg->resetConfigGpio))
399 +
400 +struct event_t {
401 + struct work_struct wq;
402 + int set;
403 + unsigned long jiffies;
404 +};
405 +
406 +static struct ar231x_boarddata *bcfg;
407 +static struct timer_list rst_button_timer;
408 +
409 +extern struct sock *uevent_sock;
410 +extern u64 uevent_next_seqnum(void);
411 +static unsigned long seen;
412 +
413 +static inline void add_msg(struct sk_buff *skb, char *msg)
414 +{
415 + char *scratch;
416 + scratch = skb_put(skb, strlen(msg) + 1);
417 + sprintf(scratch, msg);
418 +}
419 +
420 +static void hotplug_button(struct work_struct *wq)
421 +{
422 + struct sk_buff *skb;
423 + struct event_t *event;
424 + size_t len;
425 + char *scratch, *s;
426 + char buf[128];
427 +
428 + event = container_of(wq, struct event_t, wq);
429 + if (!uevent_sock)
430 + goto done;
431 +
432 + /* allocate message with the maximum possible size */
433 + s = event->set ? "pressed" : "released";
434 + len = strlen(s) + 2;
435 + skb = alloc_skb(len + 2048, GFP_KERNEL);
436 + if (!skb)
437 + goto done;
438 +
439 + /* add header */
440 + scratch = skb_put(skb, len);
441 + sprintf(scratch, "%s@",s);
442 +
443 + /* copy keys to our continuous event payload buffer */
444 + add_msg(skb, "HOME=/");
445 + add_msg(skb, "PATH=/sbin:/bin:/usr/sbin:/usr/bin");
446 + add_msg(skb, "SUBSYSTEM=button");
447 + add_msg(skb, "BUTTON=reset");
448 + add_msg(skb, (event->set ? "ACTION=pressed" : "ACTION=released"));
449 + sprintf(buf, "SEEN=%ld", (event->jiffies - seen)/HZ);
450 + add_msg(skb, buf);
451 + snprintf(buf, 128, "SEQNUM=%llu", uevent_next_seqnum());
452 + add_msg(skb, buf);
453 +
454 + NETLINK_CB(skb).dst_group = 1;
455 + netlink_broadcast(uevent_sock, skb, 0, 1, GFP_KERNEL);
456 +
457 +done:
458 + kfree(event);
459 +}
460 +
461 +static int no_release_workaround = 1;
462 +
463 +static void
464 +reset_button_poll(unsigned long unused)
465 +{
466 + struct event_t *event;
467 + int gpio = ~0;
468 +
469 + if(!no_release_workaround)
470 + return;
471 +
472 + DO_AR2315(gpio = sysRegRead(AR2315_GPIO_DI);)
473 + gpio &= 1 << (AR531X_RESET_GPIO_IRQ - AR531X_GPIO_IRQ_BASE);
474 + if(gpio)
475 + {
476 + rst_button_timer.expires = jiffies + (HZ / 4);
477 + add_timer(&rst_button_timer);
478 + } else {
479 + event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
480 + if (!event)
481 + {
482 + printk("Could not alloc hotplug event\n");
483 + return;
484 + }
485 + event->set = 0;
486 + event->jiffies = jiffies;
487 + INIT_WORK(&event->wq, (void *)(void *)hotplug_button);
488 + schedule_work(&event->wq);
489 + }
490 +}
491 +
492 +static irqreturn_t button_handler(int irq, void *dev_id)
493 +{
494 + static int pressed = 0;
495 + struct event_t *event;
496 + u32 gpio = ~0;
497 +
498 + event = (struct event_t *) kzalloc(sizeof(struct event_t), GFP_ATOMIC);
499 + if (!event)
500 + return IRQ_NONE;
501 +
502 + pressed = !pressed;
503 +
504 + DO_AR2315(gpio = sysRegRead(AR2315_GPIO_DI);)
505 + gpio &= 1 << (irq - AR531X_GPIO_IRQ_BASE);
506 +
507 + event->set = gpio;
508 + if(!event->set)
509 + no_release_workaround = 0;
510 +
511 + event->jiffies = jiffies;
512 +
513 + INIT_WORK(&event->wq, (void *)(void *)hotplug_button);
514 + schedule_work(&event->wq);
515 +
516 + seen = jiffies;
517 + if(event->set && no_release_workaround)
518 + mod_timer(&rst_button_timer, jiffies + (HZ / 4));
519 +
520 + return IRQ_HANDLED;
521 +}
522 +
523 +void ar231x_disable_reset_button(void)
524 +{
525 + disable_irq(AR531X_RESET_GPIO_IRQ);
526 +}
527 +
528 +EXPORT_SYMBOL(ar231x_disable_reset_button);
529 +
530 +int __init ar231x_init_reset(void)
531 +{
532 + bcfg = (struct ar231x_boarddata *) board_config;
533 +
534 + seen = jiffies;
535 +
536 + init_timer(&rst_button_timer);
537 + rst_button_timer.function = reset_button_poll;
538 + rst_button_timer.expires = jiffies + HZ / 50;
539 + add_timer(&rst_button_timer);
540 +
541 + request_irq(AR531X_RESET_GPIO_IRQ, &button_handler, IRQF_SAMPLE_RANDOM, "ar231x_reset", NULL);
542 +
543 + return 0;
544 +}
545 +
546 +
547 +
548 +module_init(ar231x_init_reset);
549 --- /dev/null
550 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
551 @@ -0,0 +1,83 @@
552 +#ifndef __AR531X_PLATFORM_H
553 +#define __AR531X_PLATFORM_H
554 +
555 +/*
556 + * This is board-specific data that is stored in a "fixed" location in flash.
557 + * It is shared across operating systems, so it should not be changed lightly.
558 + * The main reason we need it is in order to extract the ethernet MAC
559 + * address(es).
560 + */
561 +struct ar231x_boarddata {
562 + u32 magic; /* board data is valid */
563 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
564 + u16 cksum; /* checksum (starting with BD_REV 2) */
565 + u16 rev; /* revision of this struct */
566 +#define BD_REV 4
567 + char boardName[64]; /* Name of board */
568 + u16 major; /* Board major number */
569 + u16 minor; /* Board minor number */
570 + u32 flags; /* Board configuration */
571 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
572 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
573 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
574 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
575 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
576 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
577 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
578 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
579 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
580 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
581 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ memCap for testing */
582 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
583 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
584 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
585 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
586 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
587 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
588 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
589 + u16 resetConfigGpio; /* Reset factory GPIO pin */
590 + u16 sysLedGpio; /* System LED GPIO pin */
591 +
592 + u32 cpuFreq; /* CPU core frequency in Hz */
593 + u32 sysFreq; /* System frequency in Hz */
594 + u32 cntFreq; /* Calculated C0_COUNT frequency */
595 +
596 + u8 wlan0_mac[6];
597 + u8 enet0_mac[6];
598 + u8 enet1_mac[6];
599 +
600 + u16 pciId; /* Pseudo PCIID for common code */
601 + u16 memCap; /* cap bank1 in MB */
602 +
603 + /* version 3 */
604 + u8 wlan1_mac[6]; /* (ar5212) */
605 +};
606 +
607 +#define BOARD_CONFIG_BUFSZ 0x1000
608 +
609 +/*
610 + * Platform device information for the Wireless MAC
611 + */
612 +struct ar231x_board_config {
613 + u16 devid;
614 +
615 + /* board config data */
616 + struct ar231x_boarddata *config;
617 +
618 + /* radio calibration data */
619 + const char *radio;
620 +};
621 +
622 +/*
623 + * Platform device information for the Ethernet MAC
624 + */
625 +struct ar231x_eth {
626 + u32 reset_base;
627 + u32 reset_mac;
628 + u32 reset_phy;
629 + u32 phy_base;
630 + struct ar231x_board_config *config;
631 + char *macaddr;
632 +};
633 +
634 +#endif /* __AR531X_PLATFORM_H */
635 --- /dev/null
636 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
637 @@ -0,0 +1,84 @@
638 +/*
639 + * Atheros SoC specific CPU feature overrides
640 + *
641 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
642 + *
643 + * This file was derived from: include/asm-mips/cpu-features.h
644 + * Copyright (C) 2003, 2004 Ralf Baechle
645 + * Copyright (C) 2004 Maciej W. Rozycki
646 + *
647 + * This program is free software; you can redistribute it and/or modify it
648 + * under the terms of the GNU General Public License version 2 as published
649 + * by the Free Software Foundation.
650 + *
651 + */
652 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
653 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
654 +
655 +/*
656 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
657 + */
658 +#define cpu_has_tlb 1
659 +#define cpu_has_4kex 1
660 +#define cpu_has_3k_cache 0
661 +#define cpu_has_4k_cache 1
662 +#define cpu_has_tx39_cache 0
663 +#define cpu_has_sb1_cache 0
664 +#define cpu_has_fpu 0
665 +#define cpu_has_32fpr 0
666 +#define cpu_has_counter 1
667 +/* #define cpu_has_watch ? */
668 +/* #define cpu_has_divec ? */
669 +/* #define cpu_has_vce ? */
670 +/* #define cpu_has_cache_cdex_p ? */
671 +/* #define cpu_has_cache_cdex_s ? */
672 +/* #define cpu_has_prefetch ? */
673 +/* #define cpu_has_mcheck ? */
674 +#define cpu_has_ejtag 1
675 +
676 +#if !defined(CONFIG_ATHEROS_AR5312)
677 +# define cpu_has_llsc 1
678 +#else
679 +/*
680 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
681 + * ll/sc instructions.
682 + */
683 +# define cpu_has_llsc 0
684 +#endif
685 +
686 +#define cpu_has_mips16 0
687 +#define cpu_has_mdmx 0
688 +#define cpu_has_mips3d 0
689 +#define cpu_has_smartmips 0
690 +
691 +/* #define cpu_has_vtag_icache ? */
692 +/* #define cpu_has_dc_aliases ? */
693 +/* #define cpu_has_ic_fills_f_dc ? */
694 +/* #define cpu_has_pindexed_dcache ? */
695 +
696 +/* #define cpu_icache_snoops_remote_store ? */
697 +
698 +#define cpu_has_mips32r1 1
699 +
700 +#if !defined(CONFIG_ATHEROS_AR5312)
701 +# define cpu_has_mips32r2 1
702 +#endif
703 +
704 +#define cpu_has_mips64r1 0
705 +#define cpu_has_mips64r2 0
706 +
707 +#define cpu_has_dsp 0
708 +#define cpu_has_mipsmt 0
709 +
710 +/* #define cpu_has_nofpuex ? */
711 +#define cpu_has_64bits 0
712 +#define cpu_has_64bit_zero_reg 0
713 +#define cpu_has_64bit_gp_regs 0
714 +#define cpu_has_64bit_addresses 0
715 +
716 +/* #define cpu_has_inclusive_pcaches ? */
717 +
718 +/* #define cpu_dcache_line_size() ? */
719 +/* #define cpu_icache_line_size() ? */
720 +
721 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
722 --- /dev/null
723 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
724 @@ -0,0 +1,41 @@
725 +/*
726 + * This file is subject to the terms and conditions of the GNU General Public
727 + * License. See the file "COPYING" in the main directory of this archive
728 + * for more details.
729 + *
730 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
731 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
732 + *
733 + */
734 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
735 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
736 +
737 +#define PCI_DMA_OFFSET 0x20000000
738 +
739 +struct device;
740 +
741 +static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
742 +{
743 + return virt_to_phys(addr) + (dev != NULL ? PCI_DMA_OFFSET : 0);
744 +}
745 +
746 +static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
747 +{
748 + return page_to_phys(page) + (dev != NULL ? PCI_DMA_OFFSET : 0);
749 +}
750 +
751 +static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
752 +{
753 + return (dma_addr > PCI_DMA_OFFSET ? dma_addr - PCI_DMA_OFFSET : dma_addr);
754 +}
755 +
756 +static void plat_unmap_dma_mem(dma_addr_t dma_addr)
757 +{
758 +}
759 +
760 +static inline int plat_device_is_coherent(struct device *dev)
761 +{
762 + return 0;
763 +}
764 +
765 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
766 --- /dev/null
767 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
768 @@ -0,0 +1,79 @@
769 +#ifndef _ATHEROS_GPIO_H_
770 +#define _ATHEROS_GPIO_H_
771 +
772 +#include <ar231x.h>
773 +
774 +struct ar231x_gpiodev {
775 + u32 valid_mask;
776 + u32 (*get_output)(void);
777 + u32 (*set_output)(u32 mask, u32 val);
778 + u32 (*get)(void);
779 + u32 (*set)(u32 mask, u32 val);
780 +};
781 +
782 +extern const struct ar231x_gpiodev *ar231x_gpiodev;
783 +
784 +/*
785 + * Wrappers for the generic GPIO layer
786 + */
787 +
788 +static inline int gpio_direction_input(unsigned gpio) {
789 + u32 mask = 1 << gpio;
790 +
791 + if (!(ar231x_gpiodev->valid_mask & mask))
792 + return -ENXIO;
793 +
794 + ar231x_gpiodev->set_output(mask, 0);
795 + return 0;
796 +}
797 +
798 +static inline void gpio_set_value(unsigned gpio, int value) {
799 + u32 mask = 1 << gpio;
800 +
801 + if (!(ar231x_gpiodev->valid_mask & mask))
802 + return;
803 +
804 + ar231x_gpiodev->set(mask, (!!value) * mask);
805 +}
806 +
807 +static inline int gpio_direction_output(unsigned gpio, int value) {
808 + u32 mask = 1 << gpio;
809 +
810 + if (!(ar231x_gpiodev->valid_mask & mask))
811 + return -ENXIO;
812 +
813 + ar231x_gpiodev->set_output(mask, mask);
814 + ar231x_gpiodev->set(mask, (!!value) * mask);
815 + return 0;
816 +}
817 +
818 +/* Reads the gpio pin. Unchecked function */
819 +static inline int gpio_get_value(unsigned gpio) {
820 + u32 mask = 1 << gpio;
821 +
822 + if (!(ar231x_gpiodev->valid_mask & mask))
823 + return 0;
824 +
825 + return !!(ar231x_gpiodev->get() & mask);
826 +}
827 +
828 +static inline int gpio_request(unsigned gpio, const char *label) {
829 + return 0;
830 +}
831 +
832 +static inline void gpio_free(unsigned gpio) {
833 +}
834 +
835 +/* Returns IRQ to attach for gpio. Unchecked function */
836 +static inline int gpio_to_irq(unsigned gpio) {
837 + return AR531X_GPIO_IRQ(gpio);
838 +}
839 +
840 +/* Returns gpio for IRQ attached. Unchecked function */
841 +static inline int irq_to_gpio(unsigned irq) {
842 + return (irq - (AR531X_GPIO_IRQ(0)));
843 +}
844 +
845 +#include <asm-generic/gpio.h> /* cansleep wrappers */
846 +
847 +#endif
848 --- /dev/null
849 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
850 @@ -0,0 +1,6 @@
851 +#ifndef __AR531X_RESET_H
852 +#define __AR531X_RESET_H
853 +
854 +void ar531x_disable_reset_button(void);
855 +
856 +#endif /* __AR531X_RESET_H */
857 --- /dev/null
858 +++ b/arch/mips/include/asm/mach-ar231x/war.h
859 @@ -0,0 +1,25 @@
860 +/*
861 + * This file is subject to the terms and conditions of the GNU General Public
862 + * License. See the file "COPYING" in the main directory of this archive
863 + * for more details.
864 + *
865 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
866 + */
867 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
868 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
869 +
870 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
871 +#define R4600_V1_HIT_CACHEOP_WAR 0
872 +#define R4600_V2_HIT_CACHEOP_WAR 0
873 +#define R5432_CP0_INTERRUPT_WAR 0
874 +#define BCM1250_M3_WAR 0
875 +#define SIBYTE_1956_WAR 0
876 +#define MIPS4K_ICACHE_REFILL_WAR 0
877 +#define MIPS_CACHE_SYNC_WAR 0
878 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
879 +#define RM9000_CDEX_SMP_WAR 0
880 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
881 +#define R10000_LLSC_WAR 0
882 +#define MIPS34K_MISSED_ITLB_WAR 0
883 +
884 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
885 --- /dev/null
886 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
887 @@ -0,0 +1,580 @@
888 +/*
889 + * Register definitions for AR2315+
890 + *
891 + * This file is subject to the terms and conditions of the GNU General Public
892 + * License. See the file "COPYING" in the main directory of this archive
893 + * for more details.
894 + *
895 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
896 + * Copyright (C) 2006 FON Technology, SL.
897 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
898 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
899 + */
900 +
901 +#ifndef __AR2315_REG_H
902 +#define __AR2315_REG_H
903 +
904 +/*
905 + * IRQs
906 + */
907 +#define AR2315_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
908 +#define AR2315_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
909 +#define AR2315_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
910 +#define AR2315_IRQ_LCBUS_PCI MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
911 +#define AR2315_IRQ_WLAN0_POLL MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
912 +
913 +/*
914 + * Address map
915 + */
916 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
917 +#define AR2315_WLAN0 0xB0000000 /* Wireless MMR */
918 +#define AR2315_PCI 0xB0100000 /* PCI MMR */
919 +#define AR2315_SDRAMCTL 0xB0300000 /* SDRAM MMR */
920 +#define AR2315_LOCAL 0xB0400000 /* LOCAL BUS MMR */
921 +#define AR2315_ENET0 0xB0500000 /* ETHERNET MMR */
922 +#define AR2315_DSLBASE 0xB1000000 /* RESET CONTROL MMR */
923 +#define AR2315_UART0 0xB1100003 /* UART MMR */
924 +#define AR2315_SPI 0xB1300000 /* SPI FLASH MMR */
925 +#define AR2315_PCIEXT 0x80000000 /* pci external */
926 +
927 +/*
928 + * Reset Register
929 + */
930 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
931 +
932 +#define AR2315_RESET_COLD_AHB 0x00000001
933 +#define AR2315_RESET_COLD_APB 0x00000002
934 +#define AR2315_RESET_COLD_CPU 0x00000004
935 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
936 +#define AR2315_RESET_SYSTEM (RESET_COLD_CPU | RESET_COLD_APB | RESET_COLD_AHB) /* full system */
937 +#define AR2317_RESET_SYSTEM 0x00000010
938 +
939 +
940 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
941 +
942 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001 /* warm reset WLAN0 MAC */
943 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002 /* warm reset WLAN0 BaseBand */
944 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004 /* warm reset MPEG-TS */
945 +#define AR2315_RESET_PCIDMA 0x00000008 /* warm reset PCI ahb/dma */
946 +#define AR2315_RESET_MEMCTL 0x00000010 /* warm reset memory controller */
947 +#define AR2315_RESET_LOCAL 0x00000020 /* warm reset local bus */
948 +#define AR2315_RESET_I2C_RSVD 0x00000040 /* warm reset I2C bus */
949 +#define AR2315_RESET_SPI 0x00000080 /* warm reset SPI interface */
950 +#define AR2315_RESET_UART0 0x00000100 /* warm reset UART0 */
951 +#define AR2315_RESET_IR_RSVD 0x00000200 /* warm reset IR interface */
952 +#define AR2315_RESET_EPHY0 0x00000400 /* cold reset ENET0 phy */
953 +#define AR2315_RESET_ENET0 0x00000800 /* cold reset ENET0 mac */
954 +
955 +/*
956 + * AHB master arbitration control
957 + */
958 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
959 +
960 +#define AR2315_ARB_CPU 0x00000001 /* CPU, default */
961 +#define AR2315_ARB_WLAN 0x00000002 /* WLAN */
962 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004 /* MPEG-TS */
963 +#define AR2315_ARB_LOCAL 0x00000008 /* LOCAL */
964 +#define AR2315_ARB_PCI 0x00000010 /* PCI */
965 +#define AR2315_ARB_ETHERNET 0x00000020 /* Ethernet */
966 +#define AR2315_ARB_RETRY 0x00000100 /* retry policy, debug only */
967 +
968 +/*
969 + * Config Register
970 + */
971 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
972 +
973 +#define AR2315_CONFIG_AHB 0x00000001 /* EC - AHB bridge endianess */
974 +#define AR2315_CONFIG_WLAN 0x00000002 /* WLAN byteswap */
975 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004 /* MPEG-TS byteswap */
976 +#define AR2315_CONFIG_PCI 0x00000008 /* PCI byteswap */
977 +#define AR2315_CONFIG_MEMCTL 0x00000010 /* Memory controller endianess */
978 +#define AR2315_CONFIG_LOCAL 0x00000020 /* Local bus byteswap */
979 +#define AR2315_CONFIG_ETHERNET 0x00000040 /* Ethernet byteswap */
980 +
981 +#define AR2315_CONFIG_MERGE 0x00000200 /* CPU write buffer merge */
982 +#define AR2315_CONFIG_CPU 0x00000400 /* CPU big endian */
983 +#define AR2315_CONFIG_PCIAHB 0x00000800
984 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
985 +#define AR2315_CONFIG_SPI 0x00008000 /* SPI byteswap */
986 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
987 +#define AR2315_CONFIG_CPU_PCI 0x00020000
988 +#define AR2315_CONFIG_CPU_MMR 0x00040000
989 +#define AR2315_CONFIG_BIG 0x00000400
990 +
991 +
992 +/*
993 + * NMI control
994 + */
995 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
996 +
997 +#define AR2315_NMI_EN 1
998 +
999 +/*
1000 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
1001 + */
1002 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
1003 +
1004 +#define AR2315_REV_MAJ 0x00f0
1005 +#define AR2315_REV_MAJ_S 4
1006 +#define AR2315_REV_MIN 0x000f
1007 +#define AR2315_REV_MIN_S 0
1008 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
1009 +
1010 +/*
1011 + * Interface Enable
1012 + */
1013 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
1014 +
1015 +#define AR2315_IF_MASK 0x00000007
1016 +#define AR2315_IF_DISABLED 0
1017 +#define AR2315_IF_PCI 1
1018 +#define AR2315_IF_TS_LOCAL 2
1019 +#define AR2315_IF_ALL 3 /* only for emulation with separate pins */
1020 +#define AR2315_IF_LOCAL_HOST 0x00000008
1021 +#define AR2315_IF_PCI_HOST 0x00000010
1022 +#define AR2315_IF_PCI_INTR 0x00000020
1023 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
1024 +#define AR2315_IF_PCI_CLK_INPUT 0
1025 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
1026 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
1027 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
1028 +#define AR2315_IF_PCI_CLK_SHIFT 16
1029 +
1030 +/*
1031 + * APB Interrupt control
1032 + */
1033 +
1034 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
1035 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
1036 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
1037 +
1038 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
1039 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
1040 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
1041 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
1042 +#define AR2315_ISR_APB 0x0010 /* APB error */
1043 +#define AR2315_ISR_TIMER 0x0020 /* timer */
1044 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
1045 +#define AR2315_ISR_WD 0x0080 /* watchdog */
1046 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
1047 +
1048 +#define AR2315_GISR_MISC 0x0001
1049 +#define AR2315_GISR_WLAN0 0x0002
1050 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
1051 +#define AR2315_GISR_LOCALPCI 0x0008
1052 +#define AR2315_GISR_WMACPOLL 0x0010
1053 +#define AR2315_GISR_TIMER 0x0020
1054 +#define AR2315_GISR_ETHERNET 0x0040
1055 +
1056 +/*
1057 + * Interrupt routing from IO to the processor IP bits
1058 + * Define our inter mask and level
1059 + */
1060 +#define AR2315_INTR_MISCIO SR_IBIT3
1061 +#define AR2315_INTR_WLAN0 SR_IBIT4
1062 +#define AR2315_INTR_ENET0 SR_IBIT5
1063 +#define AR2315_INTR_LOCALPCI SR_IBIT6
1064 +#define AR2315_INTR_WMACPOLL SR_IBIT7
1065 +#define AR2315_INTR_COMPARE SR_IBIT8
1066 +
1067 +/*
1068 + * Timers
1069 + */
1070 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
1071 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
1072 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
1073 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
1074 +
1075 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
1076 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
1077 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
1078 +
1079 +/*
1080 + * CPU Performance Counters
1081 + */
1082 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
1083 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
1084 +
1085 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
1086 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
1087 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
1088 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
1089 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
1090 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
1091 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
1092 +
1093 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
1094 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
1095 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
1096 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
1097 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
1098 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
1099 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
1100 +
1101 +/*
1102 + * AHB Error Reporting.
1103 + */
1104 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
1105 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
1106 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
1107 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
1108 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
1109 +
1110 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
1111 + /* write 1 to clear all bits in ERR0 */
1112 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
1113 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
1114 +
1115 +#define AR2315_PROCERR_HMAST 0x0000000f
1116 +#define AR2315_PROCERR_HMAST_DFLT 0
1117 +#define AR2315_PROCERR_HMAST_WMAC 1
1118 +#define AR2315_PROCERR_HMAST_ENET 2
1119 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
1120 +#define AR2315_PROCERR_HMAST_LOCAL 4
1121 +#define AR2315_PROCERR_HMAST_CPU 5
1122 +#define AR2315_PROCERR_HMAST_PCITGT 6
1123 +
1124 +#define AR2315_PROCERR_HMAST_S 0
1125 +#define AR2315_PROCERR_HWRITE 0x00000010
1126 +#define AR2315_PROCERR_HSIZE 0x00000060
1127 +#define AR2315_PROCERR_HSIZE_S 5
1128 +#define AR2315_PROCERR_HTRANS 0x00000180
1129 +#define AR2315_PROCERR_HTRANS_S 7
1130 +#define AR2315_PROCERR_HBURST 0x00000e00
1131 +#define AR2315_PROCERR_HBURST_S 9
1132 +
1133 +/*
1134 + * Clock Control
1135 + */
1136 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
1137 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1138 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1139 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1140 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1141 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1142 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1143 +
1144 +/* PLLc Control fields */
1145 +#define PLLC_REF_DIV_M 0x00000003
1146 +#define PLLC_REF_DIV_S 0
1147 +#define PLLC_FDBACK_DIV_M 0x0000007C
1148 +#define PLLC_FDBACK_DIV_S 2
1149 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1150 +#define PLLC_ADD_FDBACK_DIV_S 7
1151 +#define PLLC_CLKC_DIV_M 0x0001c000
1152 +#define PLLC_CLKC_DIV_S 14
1153 +#define PLLC_CLKM_DIV_M 0x00700000
1154 +#define PLLC_CLKM_DIV_S 20
1155 +
1156 +/* CPU CLK Control fields */
1157 +#define CPUCLK_CLK_SEL_M 0x00000003
1158 +#define CPUCLK_CLK_SEL_S 0
1159 +#define CPUCLK_CLK_DIV_M 0x0000000c
1160 +#define CPUCLK_CLK_DIV_S 2
1161 +
1162 +/* AMBA CLK Control fields */
1163 +#define AMBACLK_CLK_SEL_M 0x00000003
1164 +#define AMBACLK_CLK_SEL_S 0
1165 +#define AMBACLK_CLK_DIV_M 0x0000000c
1166 +#define AMBACLK_CLK_DIV_S 2
1167 +
1168 +/*
1169 + * GPIO
1170 + */
1171 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1172 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1173 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1174 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1175 +
1176 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1177 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1178 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1179 +
1180 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1181 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1182 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1183 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1184 +
1185 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for AR5313_GPIO_INT_* macros */
1186 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1187 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1188 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1189 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1190 +
1191 +#define AR2315_RESET_GPIO 5
1192 +#define AR2315_NUM_GPIO 22
1193 +
1194 +/*
1195 + * PCI Clock Control
1196 + */
1197 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1198 +
1199 +#define AR2315_PCICLK_INPUT_M 0x3
1200 +#define AR2315_PCICLK_INPUT_S 0
1201 +
1202 +#define AR2315_PCICLK_PLLC_CLKM 0
1203 +#define AR2315_PCICLK_PLLC_CLKM1 1
1204 +#define AR2315_PCICLK_PLLC_CLKC 2
1205 +#define AR2315_PCICLK_REF_CLK 3
1206 +
1207 +#define AR2315_PCICLK_DIV_M 0xc
1208 +#define AR2315_PCICLK_DIV_S 2
1209 +
1210 +#define AR2315_PCICLK_IN_FREQ 0
1211 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1212 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1213 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1214 +
1215 +/*
1216 + * Observation Control Register
1217 + */
1218 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1219 +#define OCR_GPIO0_IRIN 0x0040
1220 +#define OCR_GPIO1_IROUT 0x0080
1221 +#define OCR_GPIO3_RXCLR 0x0200
1222 +
1223 +/*
1224 + * General Clock Control
1225 + */
1226 +
1227 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1228 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1229 +#define MISCCLK_PROCREFCLK 0x00000002
1230 +
1231 +/*
1232 + * SDRAM Controller
1233 + * - No read or write buffers are included.
1234 + */
1235 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1236 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1237 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1238 +
1239 +#define SDRAM_DATA_WIDTH_M 0x00006000
1240 +#define SDRAM_DATA_WIDTH_S 13
1241 +
1242 +#define SDRAM_COL_WIDTH_M 0x00001E00
1243 +#define SDRAM_COL_WIDTH_S 9
1244 +
1245 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1246 +#define SDRAM_ROW_WIDTH_S 5
1247 +
1248 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1249 +#define SDRAM_BANKADDR_BITS_S 3
1250 +
1251 +/*
1252 + * SPI Flash Interface Registers
1253 + */
1254 +
1255 +#define AR2315_SPI_CTL (AR2315_SPI + 0x00)
1256 +#define AR2315_SPI_OPCODE (AR2315_SPI + 0x04)
1257 +#define AR2315_SPI_DATA (AR2315_SPI + 0x08)
1258 +
1259 +#define SPI_CTL_START 0x00000100
1260 +#define SPI_CTL_BUSY 0x00010000
1261 +#define SPI_CTL_TXCNT_MASK 0x0000000f
1262 +#define SPI_CTL_RXCNT_MASK 0x000000f0
1263 +#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
1264 +#define SPI_CTL_SIZE_MASK 0x00060000
1265 +
1266 +#define SPI_CTL_CLK_SEL_MASK 0x03000000
1267 +#define SPI_OPCODE_MASK 0x000000ff
1268 +
1269 +/*
1270 + * PCI Bus Interface Registers
1271 + */
1272 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1273 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1274 +
1275 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1276 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1277 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1278 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1279 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1280 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1281 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1282 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1283 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1284 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1285 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1286 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1287 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache disable */
1288 +
1289 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1290 +
1291 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1292 +
1293 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1294 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1295 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1296 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1297 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1298 +
1299 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1300 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1301 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1302 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1303 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1304 +
1305 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1306 +
1307 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1308 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1309 +
1310 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1311 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1312 +
1313 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1314 +
1315 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1316 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1317 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1318 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1319 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1320 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1321 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1322 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1323 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1324 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1325 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1326 +#define AR2315_PCI_EXT_INT 0x02000000
1327 +#define AR2315_PCI_ABORT_INT 0x04000000
1328 +
1329 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1330 +
1331 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1332 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1333 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1334 +
1335 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1336 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1337 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1338 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1339 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1340 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1341 +
1342 +
1343 +/*
1344 + * Local Bus Interface Registers
1345 + */
1346 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1347 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1348 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1349 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1350 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1351 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1352 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1353 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1354 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1355 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1356 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1357 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1358 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1359 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1360 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1361 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1362 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1363 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1364 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1365 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1366 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1367 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1368 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1369 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1370 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1371 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1372 +
1373 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1374 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1375 +
1376 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1377 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1378 +
1379 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1380 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1381 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1382 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1383 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1384 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1385 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1386 +#define AR2315_LBM_TIMEOUT_SHFT 7
1387 +#define AR2315_LBM_PORTMUX 0x07000000
1388 +
1389 +
1390 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1391 +
1392 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1393 +#define AR2315_LB_TXEN_0 0x01
1394 +#define AR2315_LB_TXEN_1 0x02
1395 +#define AR2315_LB_TXEN_2 0x04
1396 +#define AR2315_LB_TXEN_3 0x08
1397 +
1398 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1399 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1400 +
1401 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1402 +#define AR2315_LB_RXEN 0x01
1403 +
1404 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1405 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1406 +
1407 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1408 +#define AR2315_INT_TX_DESC 0x0001
1409 +#define AR2315_INT_TX_OK 0x0002
1410 +#define AR2315_INT_TX_ERR 0x0004
1411 +#define AR2315_INT_TX_EOF 0x0008
1412 +#define AR2315_INT_RX_DESC 0x0010
1413 +#define AR2315_INT_RX_OK 0x0020
1414 +#define AR2315_INT_RX_ERR 0x0040
1415 +#define AR2315_INT_RX_EOF 0x0080
1416 +#define AR2315_INT_TX_TRUNC 0x0100
1417 +#define AR2315_INT_TX_STARVE 0x0200
1418 +#define AR2315_INT_LB_TIMEOUT 0x0400
1419 +#define AR2315_INT_LB_ERR 0x0800
1420 +#define AR2315_INT_MBOX_WR 0x1000
1421 +#define AR2315_INT_MBOX_RD 0x2000
1422 +
1423 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1424 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1425 +
1426 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1427 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1428 +
1429 +/*
1430 + * IR Interface Registers
1431 + */
1432 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1433 +
1434 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1435 +
1436 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1437 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1438 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1439 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor mask */
1440 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1441 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk divisor mask */
1442 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1443 +
1444 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1445 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1446 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1447 +
1448 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1449 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert input polarity */
1450 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert output polarity */
1451 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1452 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0 /* */
1453 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100 /* */
1454 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00 /* */
1455 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000 /* */
1456 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000 /* */
1457 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000 /* */
1458 +
1459 +#define HOST_PCI_DEV_ID 3
1460 +#define HOST_PCI_MBAR0 0x10000000
1461 +#define HOST_PCI_MBAR1 0x20000000
1462 +#define HOST_PCI_MBAR2 0x30000000
1463 +
1464 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1465 +#define PCI_DEVICE_MEM_SPACE 0x800000
1466 +
1467 +#endif /* __AR2315_REG_H */
1468 --- /dev/null
1469 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1470 @@ -0,0 +1,236 @@
1471 +/*
1472 + * This file is subject to the terms and conditions of the GNU General Public
1473 + * License. See the file "COPYING" in the main directory of this archive
1474 + * for more details.
1475 + *
1476 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1477 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1478 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1479 + */
1480 +
1481 +#ifndef AR5312_H
1482 +#define AR5312_H
1483 +
1484 +#include <asm/addrspace.h>
1485 +
1486 +/*
1487 + * IRQs
1488 + */
1489 +
1490 +#define AR5312_IRQ_WLAN0_INTRS MIPS_CPU_IRQ_BASE+2 /* C0_CAUSE: 0x0400 */
1491 +#define AR5312_IRQ_ENET0_INTRS MIPS_CPU_IRQ_BASE+3 /* C0_CAUSE: 0x0800 */
1492 +#define AR5312_IRQ_ENET1_INTRS MIPS_CPU_IRQ_BASE+4 /* C0_CAUSE: 0x1000 */
1493 +#define AR5312_IRQ_WLAN1_INTRS MIPS_CPU_IRQ_BASE+5 /* C0_CAUSE: 0x2000 */
1494 +#define AR5312_IRQ_MISC_INTRS MIPS_CPU_IRQ_BASE+6 /* C0_CAUSE: 0x4000 */
1495 +
1496 +
1497 +/* Address Map */
1498 +#define AR531X_WLAN0 0x18000000
1499 +#define AR531X_WLAN1 0x18500000
1500 +#define AR531X_ENET0 0x18100000
1501 +#define AR531X_ENET1 0x18200000
1502 +#define AR531X_SDRAMCTL 0x18300000
1503 +#define AR531X_FLASHCTL 0x18400000
1504 +#define AR531X_APBBASE 0x1c000000
1505 +#define AR531X_FLASH 0x1e000000
1506 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1507 +
1508 +/*
1509 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1510 + * should be considered available. The AR5312 supports 2 enet MACS,
1511 + * even though many reference boards only actually use 1 of them
1512 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1513 + * The AR2312 supports 1 enet MAC.
1514 + */
1515 +#define AR531X_NUM_ENET_MAC 2
1516 +
1517 +/*
1518 + * Need these defines to determine true number of ethernet MACs
1519 + */
1520 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1521 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1522 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1523 +#define AR531X_RADIO_MASK_OFF 0xc8
1524 +#define AR531X_RADIO0_MASK 0x0003
1525 +#define AR531X_RADIO1_MASK 0x000c
1526 +#define AR531X_RADIO1_S 2
1527 +
1528 +/*
1529 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1530 + * should be considered available.
1531 + */
1532 +#define AR531X_NUM_WMAC 2
1533 +
1534 +/* Reset/Timer Block Address Map */
1535 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1536 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1537 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1538 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1539 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1540 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1541 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1542 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1543 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1544 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1545 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1546 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1547 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1548 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1549 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1550 +
1551 +/* AR531X_WD_CTRL register bit field definitions */
1552 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1553 +#define AR531X_WD_CTRL_NMI 0x0001
1554 +#define AR531X_WD_CTRL_RESET 0x0002
1555 +
1556 +/* AR531X_ISR register bit field definitions */
1557 +#define AR531X_ISR_NONE 0x0000
1558 +#define AR531X_ISR_TIMER 0x0001
1559 +#define AR531X_ISR_AHBPROC 0x0002
1560 +#define AR531X_ISR_AHBDMA 0x0004
1561 +#define AR531X_ISR_GPIO 0x0008
1562 +#define AR531X_ISR_UART0 0x0010
1563 +#define AR531X_ISR_UART0DMA 0x0020
1564 +#define AR531X_ISR_WD 0x0040
1565 +#define AR531X_ISR_LOCAL 0x0080
1566 +
1567 +/* AR531X_RESET register bit field definitions */
1568 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1569 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1570 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1571 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1572 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1573 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1574 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1575 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1576 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1577 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1578 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1579 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1580 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1581 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1582 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1583 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1584 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1585 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1586 +
1587 +#define AR531X_RESET_WMAC0_BITS \
1588 + AR531X_RESET_WLAN0 |\
1589 + AR531X_RESET_WARM_WLAN0_MAC |\
1590 + AR531X_RESET_WARM_WLAN0_BB
1591 +
1592 +#define AR531X_RESERT_WMAC1_BITS \
1593 + AR531X_RESET_WLAN1 |\
1594 + AR531X_RESET_WARM_WLAN1_MAC |\
1595 + AR531X_RESET_WARM_WLAN1_BB
1596 +
1597 +/* AR5312_CLOCKCTL1 register bit field definitions */
1598 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1599 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1600 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1601 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1602 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1603 +
1604 +/* Valid for AR5312 and AR2312 */
1605 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1606 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1607 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1608 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1609 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1610 +
1611 +/* Valid for AR2313 */
1612 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1613 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1614 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1615 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1616 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1617 +
1618 +
1619 +/* AR531X_ENABLE register bit field definitions */
1620 +#define AR531X_ENABLE_WLAN0 0x0001
1621 +#define AR531X_ENABLE_ENET0 0x0002
1622 +#define AR531X_ENABLE_ENET1 0x0004
1623 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1624 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1625 +#define AR531X_ENABLE_WLAN1 \
1626 + (AR531X_ENABLE_UART_AND_WLAN1_PIO | AR531X_ENABLE_WLAN1_DMA)
1627 +
1628 +/* AR531X_REV register bit field definitions */
1629 +#define AR531X_REV_WMAC_MAJ 0xf000
1630 +#define AR531X_REV_WMAC_MAJ_S 12
1631 +#define AR531X_REV_WMAC_MIN 0x0f00
1632 +#define AR531X_REV_WMAC_MIN_S 8
1633 +#define AR531X_REV_MAJ 0x00f0
1634 +#define AR531X_REV_MAJ_S 4
1635 +#define AR531X_REV_MIN 0x000f
1636 +#define AR531X_REV_MIN_S 0
1637 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1638 +
1639 +/* Major revision numbers, bits 7..4 of Revision ID register */
1640 +#define AR531X_REV_MAJ_AR5312 0x4
1641 +#define AR531X_REV_MAJ_AR2313 0x5
1642 +
1643 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1644 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1645 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1646 +
1647 +/* AR531X_FLASHCTL register bit field definitions */
1648 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1649 +#define FLASHCTL_IDCY_S 0
1650 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1651 +#define FLASHCTL_WST1_S 5
1652 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1653 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1654 +#define FLASHCTL_WST2_S 11
1655 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1656 +#define FLASHCTL_AC_S 16
1657 +#define FLASHCTL_AC_128K 0x00000000
1658 +#define FLASHCTL_AC_256K 0x00010000
1659 +#define FLASHCTL_AC_512K 0x00020000
1660 +#define FLASHCTL_AC_1M 0x00030000
1661 +#define FLASHCTL_AC_2M 0x00040000
1662 +#define FLASHCTL_AC_4M 0x00050000
1663 +#define FLASHCTL_AC_8M 0x00060000
1664 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1665 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1666 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1667 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1668 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1669 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1670 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1671 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1672 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1673 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1674 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1675 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1676 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1677 +
1678 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1679 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1680 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1681 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1682 +
1683 +/* ARM SDRAM Controller -- just enough to determine memory size */
1684 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1685 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1686 +#define MEM_CFG1_AC0_S 8
1687 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1688 +#define MEM_CFG1_AC1_S 12
1689 +
1690 +/* GPIO Address Map */
1691 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1692 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1693 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1694 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1695 +
1696 +/* GPIO Control Register bit field definitions */
1697 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1698 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1699 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1700 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt */
1701 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1702 +#define AR531X_NUM_GPIO 8
1703 +
1704 +
1705 +#endif
1706 +
1707 --- /dev/null
1708 +++ b/arch/mips/ar231x/ar5312.c
1709 @@ -0,0 +1,563 @@
1710 +/*
1711 + * This file is subject to the terms and conditions of the GNU General Public
1712 + * License. See the file "COPYING" in the main directory of this archive
1713 + * for more details.
1714 + *
1715 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1716 + * Copyright (C) 2006 FON Technology, SL.
1717 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1718 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1719 + */
1720 +
1721 +/*
1722 + * Platform devices for Atheros SoCs
1723 + */
1724 +
1725 +#include <linux/autoconf.h>
1726 +#include <linux/init.h>
1727 +#include <linux/module.h>
1728 +#include <linux/types.h>
1729 +#include <linux/string.h>
1730 +#include <linux/mtd/physmap.h>
1731 +#include <linux/platform_device.h>
1732 +#include <linux/kernel.h>
1733 +#include <linux/reboot.h>
1734 +#include <linux/leds.h>
1735 +#include <asm/bootinfo.h>
1736 +#include <asm/reboot.h>
1737 +#include <asm/time.h>
1738 +#include <asm/irq.h>
1739 +#include <asm/io.h>
1740 +#include <gpio.h>
1741 +
1742 +#include <ar231x_platform.h>
1743 +#include <ar5312_regs.h>
1744 +#include <ar231x.h>
1745 +#include "devices.h"
1746 +#include "ar5312.h"
1747 +
1748 +#define IS_5312() (current_cpu_data.cputype != CPU_4KEC)
1749 +
1750 +static void
1751 +ar5312_misc_irq_dispatch(void)
1752 +{
1753 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) & ar231x_read_reg(AR531X_IMR);
1754 +
1755 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1756 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1757 + (void)ar231x_read_reg(AR531X_TIMER);
1758 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1759 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1760 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1761 + do_IRQ(AR531X_MISC_IRQ_UART0);
1762 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1763 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1764 + else
1765 + do_IRQ(AR531X_MISC_IRQ_NONE);
1766 +}
1767 +
1768 +void
1769 +ar5312_irq_dispatch(void)
1770 +{
1771 + int pending = read_c0_status() & read_c0_cause();
1772 +
1773 + if (pending & CAUSEF_IP2)
1774 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1775 + else if (pending & CAUSEF_IP3)
1776 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1777 + else if (pending & CAUSEF_IP4)
1778 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1779 + else if (pending & CAUSEF_IP5)
1780 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1781 + else if (pending & CAUSEF_IP6)
1782 + ar5312_misc_irq_dispatch();
1783 + else if (pending & CAUSEF_IP7)
1784 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1785 +}
1786 +
1787 +
1788 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1789 +static void
1790 +ar5312_misc_intr_enable(unsigned int irq)
1791 +{
1792 + unsigned int imr;
1793 +
1794 + imr = ar231x_read_reg(AR531X_IMR);
1795 + imr |= (1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1796 + ar231x_write_reg(AR531X_IMR, imr);
1797 +}
1798 +
1799 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1800 +static void
1801 +ar5312_misc_intr_disable(unsigned int irq)
1802 +{
1803 + unsigned int imr;
1804 +
1805 + imr = ar231x_read_reg(AR531X_IMR);
1806 + imr &= ~(1 << (irq - AR531X_MISC_IRQ_BASE - 1));
1807 + ar231x_write_reg(AR531X_IMR, imr);
1808 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1809 +}
1810 +
1811 +static unsigned int
1812 +ar5312_misc_intr_startup(unsigned int irq)
1813 +{
1814 + ar5312_misc_intr_enable(irq);
1815 + return 0;
1816 +}
1817 +
1818 +static void
1819 +ar5312_misc_intr_end(unsigned int irq)
1820 +{
1821 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
1822 + ar5312_misc_intr_enable(irq);
1823 +}
1824 +
1825 +static struct irq_chip ar5312_misc_intr_controller = {
1826 + .name = "AR5312-MISC",
1827 + .startup = ar5312_misc_intr_startup,
1828 + .shutdown = ar5312_misc_intr_disable,
1829 + .enable = ar5312_misc_intr_enable,
1830 + .disable = ar5312_misc_intr_disable,
1831 + .ack = ar5312_misc_intr_disable,
1832 + .end = ar5312_misc_intr_end,
1833 +};
1834 +
1835 +
1836 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1837 +{
1838 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1839 + u32 procAddr = ar231x_read_reg(AR531X_PROCADDR); /* clears error state */
1840 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1841 + u32 dmaAddr = ar231x_read_reg(AR531X_DMAADDR); /* clears error state */
1842 +
1843 + printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1844 + procAddr, proc1, dmaAddr, dma1);
1845 +
1846 + machine_restart("AHB error"); /* Catastrophic failure */
1847 + return IRQ_HANDLED;
1848 +}
1849 +
1850 +
1851 +static struct irqaction ar5312_ahb_proc_interrupt = {
1852 + .handler = ar5312_ahb_proc_handler,
1853 + .flags = IRQF_DISABLED,
1854 + .name = "ar5312_ahb_proc_interrupt",
1855 +};
1856 +
1857 +
1858 +static struct irqaction cascade = {
1859 + .handler = no_action,
1860 + .flags = IRQF_DISABLED,
1861 + .name = "cascade",
1862 +};
1863 +
1864 +void __init ar5312_irq_init(void)
1865 +{
1866 + int i;
1867 +
1868 + if (!IS_5312())
1869 + return;
1870 +
1871 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1872 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1873 + int irq = AR531X_MISC_IRQ_BASE + i;
1874 + irq_desc[irq].status = IRQ_DISABLED;
1875 + irq_desc[irq].action = NULL;
1876 + irq_desc[irq].depth = 1;
1877 + irq_desc[irq].chip = &ar5312_misc_intr_controller;
1878 + }
1879 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1880 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1881 +}
1882 +
1883 +const struct ar231x_gpiodev ar5312_gpiodev;
1884 +
1885 +static u32
1886 +ar5312_gpio_get_output(void)
1887 +{
1888 + u32 reg;
1889 + reg = ~(ar231x_read_reg(AR531X_GPIO_CR));
1890 + reg &= ar5312_gpiodev.valid_mask;
1891 + return reg;
1892 +}
1893 +
1894 +static u32
1895 +ar5312_gpio_set_output(u32 mask, u32 val)
1896 +{
1897 + u32 reg;
1898 +
1899 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1900 + reg |= mask;
1901 + reg &= ~val;
1902 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1903 + return reg;
1904 +}
1905 +
1906 +static u32
1907 +ar5312_gpio_get(void)
1908 +{
1909 + u32 reg;
1910 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1911 + reg &= ar5312_gpiodev.valid_mask;
1912 + return reg;
1913 +}
1914 +
1915 +static u32
1916 +ar5312_gpio_set(u32 mask, u32 value)
1917 +{
1918 + u32 reg;
1919 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1920 + reg &= ~mask;
1921 + reg |= value;
1922 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1923 + return reg;
1924 +}
1925 +
1926 +const struct ar231x_gpiodev ar5312_gpiodev = {
1927 + .valid_mask = (1 << 8) - 1,
1928 + .get_output = ar5312_gpio_get_output,
1929 + .set_output = ar5312_gpio_set_output,
1930 + .get = ar5312_gpio_get,
1931 + .set = ar5312_gpio_set,
1932 +};
1933 +
1934 +static struct physmap_flash_data ar5312_flash_data = {
1935 + .width = 2,
1936 +};
1937 +
1938 +static struct resource ar5312_flash_resource = {
1939 + .start = AR531X_FLASH,
1940 + .end = AR531X_FLASH + 0x800000 - 1,
1941 + .flags = IORESOURCE_MEM,
1942 +};
1943 +
1944 +static struct ar231x_eth ar5312_eth0_data = {
1945 + .reset_base = AR531X_RESET,
1946 + .reset_mac = AR531X_RESET_ENET0,
1947 + .reset_phy = AR531X_RESET_EPHY0,
1948 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1949 + .config = &ar231x_board,
1950 +};
1951 +
1952 +static struct ar231x_eth ar5312_eth1_data = {
1953 + .reset_base = AR531X_RESET,
1954 + .reset_mac = AR531X_RESET_ENET1,
1955 + .reset_phy = AR531X_RESET_EPHY1,
1956 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1957 + .config = &ar231x_board,
1958 +};
1959 +
1960 +static struct platform_device ar5312_physmap_flash = {
1961 + .name = "physmap-flash",
1962 + .id = 0,
1963 + .dev.platform_data = &ar5312_flash_data,
1964 + .resource = &ar5312_flash_resource,
1965 + .num_resources = 1,
1966 +};
1967 +
1968 +#ifdef CONFIG_LEDS_GPIO
1969 +static struct gpio_led ar5312_leds[] = {
1970 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1971 +};
1972 +
1973 +static const struct gpio_led_platform_data ar5312_led_data = {
1974 + .num_leds = ARRAY_SIZE(ar5312_leds),
1975 + .leds = (void *) ar5312_leds,
1976 +};
1977 +
1978 +static struct platform_device ar5312_gpio_leds = {
1979 + .name = "leds-gpio",
1980 + .id = -1,
1981 + .dev.platform_data = (void *) &ar5312_led_data,
1982 + .num_resources = 1,
1983 +};
1984 +#endif
1985 +
1986 +/*
1987 + * NB: This mapping size is larger than the actual flash size,
1988 + * but this shouldn't be a problem here, because the flash
1989 + * will simply be mapped multiple times.
1990 + */
1991 +static char __init *ar5312_flash_limit(void)
1992 +{
1993 + u32 ctl;
1994 + /*
1995 + * Configure flash bank 0.
1996 + * Assume 8M window size. Flash will be aliased if it's smaller
1997 + */
1998 + ctl = FLASHCTL_E |
1999 + FLASHCTL_AC_8M |
2000 + FLASHCTL_RBLE |
2001 + (0x01 << FLASHCTL_IDCY_S) |
2002 + (0x07 << FLASHCTL_WST1_S) |
2003 + (0x07 << FLASHCTL_WST2_S) |
2004 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
2005 +
2006 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
2007 +
2008 + /* Disable other flash banks */
2009 + ar231x_write_reg(AR531X_FLASHCTL1,
2010 + ar231x_read_reg(AR531X_FLASHCTL1) & ~(FLASHCTL_E | FLASHCTL_AC));
2011 +
2012 + ar231x_write_reg(AR531X_FLASHCTL2,
2013 + ar231x_read_reg(AR531X_FLASHCTL2) & ~(FLASHCTL_E | FLASHCTL_AC));
2014 +
2015 + return (char *) KSEG1ADDR(AR531X_FLASH + 0x800000);
2016 +}
2017 +
2018 +int __init ar5312_init_devices(void)
2019 +{
2020 + struct ar231x_boarddata *config;
2021 + u32 fctl = 0;
2022 + const u8 *radio;
2023 + u8 *c;
2024 +
2025 + if (!IS_5312())
2026 + return 0;
2027 +
2028 + /* Locate board/radio config data */
2029 + ar231x_find_config(ar5312_flash_limit());
2030 + config = ar231x_board.config;
2031 +
2032 +
2033 + /*
2034 + * Chip IDs and hardware detection for some Atheros
2035 + * models are really broken!
2036 + *
2037 + * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
2038 + * as indication for AR2312, which is otherwise
2039 + * indistinguishable from the real AR5312.
2040 + */
2041 + if (ar231x_board.radio) {
2042 + radio = ar231x_board.radio + AR531X_RADIO_MASK_OFF;
2043 + if ((*((const u32 *) radio) & AR531X_RADIO0_MASK) == 0)
2044 + config->flags |= BD_ISCASPER;
2045 + } else
2046 + radio = NULL;
2047 +
2048 + /* AR2313 has CPU minor rev. 10 */
2049 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
2050 + ar231x_devtype = DEV_TYPE_AR2313;
2051 +
2052 + /* AR2312 shares the same Silicon ID as AR5312 */
2053 + else if (config->flags & BD_ISCASPER)
2054 + ar231x_devtype = DEV_TYPE_AR2312;
2055 +
2056 + /* Everything else is probably AR5312 or compatible */
2057 + else
2058 + ar231x_devtype = DEV_TYPE_AR5312;
2059 +
2060 + /* fixup flash width */
2061 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
2062 + switch (fctl) {
2063 + case FLASHCTL_MWx16:
2064 + ar5312_flash_data.width = 2;
2065 + break;
2066 + case FLASHCTL_MWx8:
2067 + default:
2068 + ar5312_flash_data.width = 1;
2069 + break;
2070 + }
2071 +
2072 + platform_device_register(&ar5312_physmap_flash);
2073 +
2074 +#ifdef CONFIG_LEDS_GPIO
2075 + ar5312_leds[0].gpio = config->sysLedGpio;
2076 + platform_device_register(&ar5312_gpio_leds);
2077 +#endif
2078 +
2079 + /* Fix up MAC addresses if necessary */
2080 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
2081 + memcpy(config->enet0_mac, config->enet1_mac, 6);
2082 +
2083 + /* If ENET0 and ENET1 have the same mac address,
2084 + * increment the one from ENET1 */
2085 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
2086 + c = config->enet1_mac + 5;
2087 + while ((c >= config->enet1_mac) && !(++(*c)))
2088 + c--;
2089 + }
2090 +
2091 + switch(ar231x_devtype) {
2092 + case DEV_TYPE_AR5312:
2093 + ar5312_eth0_data.macaddr = config->enet0_mac;
2094 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
2095 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
2096 +
2097 + ar5312_eth1_data.macaddr = config->enet1_mac;
2098 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
2099 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
2100 +
2101 + if (!ar231x_board.radio)
2102 + return 0;
2103 +
2104 + if (*((u32 *) ar231x_board.radio) & AR531X_RADIO0_MASK)
2105 + ar231x_add_wmac(0, AR531X_WLAN0,
2106 + AR5312_IRQ_WLAN0_INTRS);
2107 +
2108 + break;
2109 + /*
2110 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
2111 + * of ENET1. Atheros calls it 'twisted' for a reason :)
2112 + */
2113 + case DEV_TYPE_AR2312:
2114 + case DEV_TYPE_AR2313:
2115 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
2116 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
2117 + ar5312_eth1_data.macaddr = config->enet0_mac;
2118 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
2119 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
2120 +
2121 + if (!ar231x_board.radio)
2122 + return 0;
2123 + break;
2124 + default:
2125 + break;
2126 + }
2127 +
2128 + if (*((u32 *) ar231x_board.radio) & AR531X_RADIO1_MASK)
2129 + ar231x_add_wmac(1, AR531X_WLAN1,
2130 + AR5312_IRQ_WLAN1_INTRS);
2131 +
2132 + return 0;
2133 +}
2134 +
2135 +
2136 +static void ar5312_restart(char *command)
2137 +{
2138 + /* reset the system */
2139 + local_irq_disable();
2140 + while(1) {
2141 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
2142 + }
2143 +}
2144 +
2145 +
2146 +/*
2147 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2148 + * to determine the predevisor value.
2149 + */
2150 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
2151 + 1,
2152 + 2,
2153 + 4,
2154 + 5
2155 +};
2156 +
2157 +
2158 +static int __init
2159 +ar5312_cpu_frequency(void)
2160 +{
2161 + unsigned int result;
2162 + unsigned int predivide_mask, predivide_shift;
2163 + unsigned int multiplier_mask, multiplier_shift;
2164 + unsigned int clockCtl1, preDivideSelect, preDivisor, multiplier;
2165 + unsigned int doubler_mask;
2166 + u16 devid;
2167 +
2168 + /* Trust the bootrom's idea of cpu frequency. */
2169 + if ((result = ar231x_read_reg(AR5312_SCRATCH)))
2170 + return result;
2171 +
2172 + devid = ar231x_board.devid;
2173 + devid &= AR531X_REV_MAJ;
2174 + devid >>= AR531X_REV_MAJ_S;
2175 + if (devid == AR531X_REV_MAJ_AR2313) {
2176 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2177 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2178 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2179 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2180 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2181 + } else { /* AR5312 and AR2312 */
2182 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2183 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2184 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2185 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2186 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2187 + }
2188 +
2189 + /*
2190 + * Clocking is derived from a fixed 40MHz input clock.
2191 + *
2192 + * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
2193 + * sysFreq = cpuFreq / 4 (used for APB clock, serial,
2194 + * flash, Timer, Watchdog Timer)
2195 + *
2196 + * cntFreq = cpuFreq / 2 (use for CPU count/compare)
2197 + *
2198 + * So, for example, with a PLL multiplier of 5, we have
2199 + *
2200 + * cpuFreq = 200MHz
2201 + * sysFreq = 50MHz
2202 + * cntFreq = 100MHz
2203 + *
2204 + * We compute the CPU frequency, based on PLL settings.
2205 + */
2206 +
2207 + clockCtl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2208 + preDivideSelect = (clockCtl1 & predivide_mask) >> predivide_shift;
2209 + preDivisor = CLOCKCTL1_PREDIVIDE_TABLE[preDivideSelect];
2210 + multiplier = (clockCtl1 & multiplier_mask) >> multiplier_shift;
2211 +
2212 + if (clockCtl1 & doubler_mask) {
2213 + multiplier = multiplier << 1;
2214 + }
2215 + return (40000000 / preDivisor) * multiplier;
2216 +}
2217 +
2218 +static inline int
2219 +ar5312_sys_frequency(void)
2220 +{
2221 + return ar5312_cpu_frequency() / 4;
2222 +}
2223 +
2224 +void __init
2225 +ar5312_time_init(void)
2226 +{
2227 + if (!IS_5312())
2228 + return;
2229 +
2230 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2231 +}
2232 +
2233 +
2234 +void __init
2235 +ar5312_prom_init(void)
2236 +{
2237 + u32 memsize, memcfg, bank0AC, bank1AC;
2238 + u32 devid;
2239 +
2240 + if (!IS_5312())
2241 + return;
2242 +
2243 + devid = ar231x_read_reg(AR531X_REV);
2244 + devid &= AR531X_REV_MAJ | AR531X_REV_MIN;
2245 +
2246 + /* Detect memory size */
2247 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2248 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2249 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2250 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0)
2251 + + (bank1AC ? (1 << (bank1AC+1)) : 0);
2252 + memsize <<= 20;
2253 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2254 + ar231x_gpiodev = &ar5312_gpiodev;
2255 + ar231x_board.devid = (u16) devid;
2256 +}
2257 +
2258 +void __init
2259 +ar5312_plat_setup(void)
2260 +{
2261 + if (!IS_5312())
2262 + return;
2263 +
2264 + /* Clear any lingering AHB errors */
2265 + ar231x_read_reg(AR531X_PROCADDR);
2266 + ar231x_read_reg(AR531X_DMAADDR);
2267 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2268 +
2269 + _machine_restart = ar5312_restart;
2270 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), ar5312_sys_frequency());
2271 +}
2272 +
2273 --- /dev/null
2274 +++ b/arch/mips/ar231x/pci.c
2275 @@ -0,0 +1,231 @@
2276 +/*
2277 + * This program is free software; you can redistribute it and/or
2278 + * modify it under the terms of the GNU General Public License
2279 + * as published by the Free Software Foundation; either version 2
2280 + * of the License, or (at your option) any later version.
2281 + *
2282 + * This program is distributed in the hope that it will be useful,
2283 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2284 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2285 + * GNU General Public License for more details.
2286 + *
2287 + * You should have received a copy of the GNU General Public License
2288 + * along with this program; if not, write to the Free Software
2289 + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
2290 + */
2291 +
2292 +#include <linux/types.h>
2293 +#include <linux/pci.h>
2294 +#include <linux/kernel.h>
2295 +#include <linux/init.h>
2296 +#include <linux/mm.h>
2297 +#include <linux/spinlock.h>
2298 +#include <linux/delay.h>
2299 +#include <linux/irq.h>
2300 +#include <asm/bootinfo.h>
2301 +#include <asm/paccess.h>
2302 +#include <asm/irq_cpu.h>
2303 +#include <asm/io.h>
2304 +#include <ar231x_platform.h>
2305 +#include <ar231x.h>
2306 +#include <ar2315_regs.h>
2307 +
2308 +#define AR531X_MEM_BASE 0x80800000UL
2309 +#define AR531X_MEM_SIZE 0x00ffffffUL
2310 +#define AR531X_IO_SIZE 0x00007fffUL
2311 +
2312 +#define IS_2315() (current_cpu_data.cputype == CPU_4KEC)
2313 +
2314 +static unsigned long configspace;
2315 +
2316 +static int config_access(int devfn, int where, int size, u32 *ptr, bool write)
2317 +{
2318 + unsigned long flags;
2319 + int func = PCI_FUNC(devfn);
2320 + int dev = PCI_SLOT(devfn);
2321 + u32 value = 0;
2322 + int err = 0;
2323 + u32 addr;
2324 +
2325 + if (((dev != 0) && (dev != 3)) || (func > 2))
2326 + return PCIBIOS_DEVICE_NOT_FOUND;
2327 +
2328 + /* Select Configuration access */
2329 + local_irq_save(flags);
2330 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
2331 + mb();
2332 +
2333 + addr = (u32) configspace + (1 << (13 + dev)) + (func << 8) + where;
2334 + if (size == 1)
2335 + addr ^= 0x3;
2336 + else if (size == 2)
2337 + addr ^= 0x2;
2338 +
2339 + if (write) {
2340 + value = *ptr;
2341 + if (size == 1)
2342 + err = put_dbe(value, (u8 *) addr);
2343 + else if (size == 2)
2344 + err = put_dbe(value, (u16 *) addr);
2345 + else if (size == 4)
2346 + err = put_dbe(value, (u32 *) addr);
2347 + } else {
2348 + if (size == 1)
2349 + err = get_dbe(value, (u8 *) addr);
2350 + else if (size == 2)
2351 + err = get_dbe(value, (u16 *) addr);
2352 + else if (size == 4)
2353 + err = get_dbe(value, (u32 *) addr);
2354 + if (err)
2355 + *ptr = 0xffffffff;
2356 + else
2357 + *ptr = value;
2358 + }
2359 +
2360 + /* Select Memory access */
2361 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
2362 + local_irq_restore(flags);
2363 +
2364 + return (err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL);
2365 +}
2366 +
2367 +static int ar231x_pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * value)
2368 +{
2369 + return config_access(devfn, where, size, value, 0);
2370 +}
2371 +
2372 +static int ar231x_pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 value)
2373 +{
2374 + return config_access(devfn, where, size, &value, 1);
2375 +}
2376 +
2377 +struct pci_ops ar231x_pci_ops = {
2378 + .read = ar231x_pci_read,
2379 + .write = ar231x_pci_write,
2380 +};
2381 +
2382 +static struct resource ar231x_mem_resource = {
2383 + .name = "AR531x PCI MEM",
2384 + .start = AR531X_MEM_BASE,
2385 + .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE - 1 + 0x4000000,
2386 + .flags = IORESOURCE_MEM,
2387 +};
2388 +
2389 +static struct resource ar231x_io_resource = {
2390 + .name = "AR531x PCI I/O",
2391 + .start = AR531X_MEM_BASE + AR531X_MEM_SIZE - AR531X_IO_SIZE,
2392 + .end = AR531X_MEM_BASE + AR531X_MEM_SIZE - 1,
2393 + .flags = IORESOURCE_IO,
2394 +};
2395 +
2396 +struct pci_controller ar231x_pci_controller = {
2397 + .pci_ops = &ar231x_pci_ops,
2398 + .mem_resource = &ar231x_mem_resource,
2399 + .io_resource = &ar231x_io_resource,
2400 + .mem_offset = 0x00000000UL,
2401 + .io_offset = 0x00000000UL,
2402 +};
2403 +
2404 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
2405 +{
2406 + return AR2315_IRQ_LCBUS_PCI;
2407 +}
2408 +
2409 +int pcibios_plat_dev_init(struct pci_dev *dev)
2410 +{
2411 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 5);
2412 + pci_write_config_word(dev, 0x40, 0);
2413 +
2414 + /* Clear any pending Abort or external Interrupts
2415 + * and enable interrupt processing */
2416 + ar231x_mask_reg(AR2315_PCI_INTEN_REG, AR2315_PCI_INT_ENABLE, 0);
2417 + ar231x_write_reg(AR2315_PCI_INT_STATUS, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
2418 + ar231x_write_reg(AR2315_PCI_INT_MASK, (AR2315_PCI_ABORT_INT | AR2315_PCI_EXT_INT));
2419 + ar231x_mask_reg(AR2315_PCI_INTEN_REG, 0, AR2315_PCI_INT_ENABLE);
2420 +
2421 + return 0;
2422 +}
2423 +
2424 +static void
2425 +ar2315_pci_fixup(struct pci_dev *dev)
2426 +{
2427 + unsigned int devfn = dev->devfn;
2428 +
2429 + if (dev->bus->number != 0)
2430 + return;
2431 +
2432 + /* Only fix up the PCI host settings */
2433 + if ((PCI_SLOT(devfn) != 3) || (PCI_FUNC(devfn) != 0))
2434 + return;
2435 +
2436 + /* Fix up MBARs */
2437 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, HOST_PCI_MBAR0);
2438 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, HOST_PCI_MBAR1);
2439 + pci_write_config_dword(dev, PCI_BASE_ADDRESS_2, HOST_PCI_MBAR2);
2440 + pci_write_config_dword(dev, PCI_COMMAND,
2441 + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
2442 + PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
2443 + PCI_COMMAND_FAST_BACK);
2444 +}
2445 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, ar2315_pci_fixup);
2446 +
2447 +static int __init
2448 +ar2315_pci_init(void)
2449 +{
2450 + u32 reg;
2451 +
2452 + if (!IS_2315())
2453 + return -ENODEV;
2454 +
2455 + configspace = (unsigned long) ioremap_nocache(0x80000000, 1*1024*1024); /* Remap PCI config space */
2456 + ar231x_pci_controller.io_map_base =
2457 + (unsigned long) ioremap_nocache(AR531X_MEM_BASE + AR531X_MEM_SIZE, AR531X_IO_SIZE);
2458 + set_io_port_base(ar231x_pci_controller.io_map_base); /* PCI I/O space */
2459 +
2460 + reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
2461 + msleep(10);
2462 +
2463 + reg &= ~AR2315_RESET_PCIDMA;
2464 + ar231x_write_reg(AR2315_RESET, reg);
2465 + msleep(10);
2466 +
2467 + ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
2468 + AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
2469 +
2470 + ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
2471 + (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
2472 + ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
2473 + ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
2474 + AR2315_IF_PCI | AR2315_IF_PCI_HOST | AR2315_IF_PCI_INTR |
2475 + (AR2315_IF_PCI_CLK_OUTPUT_CLK << AR2315_IF_PCI_CLK_SHIFT));
2476 +
2477 + /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
2478 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
2479 + AR2315_PCIRST_LOW);
2480 + msleep(100);
2481 +
2482 + /* Bring the PCI out of reset */
2483 + ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
2484 + AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
2485 +
2486 + ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
2487 + 0x1E | /* 1GB uncached */
2488 + (1 << 5) | /* Enable uncached */
2489 + (0x2 << 30) /* Base: 0x80000000 */
2490 + );
2491 + ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
2492 +
2493 + msleep(500);
2494 +
2495 + /* dirty hack - anyone with a datasheet that knows the memory map ? */
2496 + ioport_resource.start = 0x10000000;
2497 + ioport_resource.end = 0xffffffff;
2498 + iomem_resource.start = 0x10000000;
2499 + iomem_resource.end = 0xffffffff;
2500 +
2501 + register_pci_controller(&ar231x_pci_controller);
2502 +
2503 + return 0;
2504 +}
2505 +
2506 +arch_initcall(ar2315_pci_init);
2507 --- /dev/null
2508 +++ b/arch/mips/ar231x/ar2315.c
2509 @@ -0,0 +1,688 @@
2510 +/*
2511 + * This file is subject to the terms and conditions of the GNU General Public
2512 + * License. See the file "COPYING" in the main directory of this archive
2513 + * for more details.
2514 + *
2515 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2516 + * Copyright (C) 2006 FON Technology, SL.
2517 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2518 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2519 + */
2520 +
2521 +/*
2522 + * Platform devices for Atheros SoCs
2523 + */
2524 +
2525 +#include <linux/autoconf.h>
2526 +#include <linux/init.h>
2527 +#include <linux/module.h>
2528 +#include <linux/types.h>
2529 +#include <linux/string.h>
2530 +#include <linux/platform_device.h>
2531 +#include <linux/kernel.h>
2532 +#include <linux/reboot.h>
2533 +#include <linux/delay.h>
2534 +#include <linux/leds.h>
2535 +#include <asm/bootinfo.h>
2536 +#include <asm/reboot.h>
2537 +#include <asm/time.h>
2538 +#include <asm/irq.h>
2539 +#include <asm/io.h>
2540 +#include <asm/gpio.h>
2541 +
2542 +#include <ar231x_platform.h>
2543 +#include <ar2315_regs.h>
2544 +#include <ar231x.h>
2545 +#include "devices.h"
2546 +#include "ar2315.h"
2547 +
2548 +#define IS_2315() (current_cpu_data.cputype == CPU_4KEC)
2549 +
2550 +static u32 gpiointmask = 0, gpiointval = 0;
2551 +
2552 +static inline void ar2315_gpio_irq(void)
2553 +{
2554 + u32 pend;
2555 + int bit;
2556 +
2557 + /* only do one gpio interrupt at a time */
2558 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2559 + if (!pend)
2560 + return;
2561 +
2562 + bit = fls(pend);
2563 + pend ^= (1 << bit);
2564 + gpiointval ^= (1 << bit);
2565 +
2566 + /* ACK the interrupt only if we handled all bits */
2567 + if (!pend)
2568 + ar231x_write_reg(AR2315_ISR, ar231x_read_reg(AR2315_IMR) | ~AR2315_ISR_GPIO);
2569 +
2570 + do_IRQ(AR531X_GPIO_IRQ_BASE + fls(pend) - 1);
2571 +}
2572 +
2573 +#ifdef CONFIG_ATHEROS_AR2315_PCI
2574 +static inline void pci_abort_irq(void)
2575 +{
2576 + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_ABORT_INT);
2577 +}
2578 +
2579 +static inline void pci_ack_irq(void)
2580 +{
2581 + ar231x_write_reg(AR2315_PCI_INT_STATUS, AR2315_PCI_EXT_INT);
2582 +}
2583 +
2584 +void ar2315_pci_irq(int irq)
2585 +{
2586 + if (ar231x_read_reg(AR2315_PCI_INT_STATUS) == AR2315_PCI_ABORT_INT)
2587 + pci_abort_irq();
2588 + else {
2589 + do_IRQ(irq);
2590 + pci_ack_irq();
2591 + }
2592 +}
2593 +#endif /* CONFIG_ATHEROS_AR2315_PCI */
2594 +
2595 +/*
2596 + * Called when an interrupt is received, this function
2597 + * determines exactly which interrupt it was, and it
2598 + * invokes the appropriate handler.
2599 + *
2600 + * Implicitly, we also define interrupt priority by
2601 + * choosing which to dispatch first.
2602 + */
2603 +static void
2604 +ar2315_irq_dispatch(void)
2605 +{
2606 + int pending = read_c0_status() & read_c0_cause();
2607 +
2608 + if (pending & CAUSEF_IP3)
2609 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2610 + else if (pending & CAUSEF_IP4)
2611 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2612 +#ifdef CONFIG_ATHEROS_AR2315_PCI
2613 + else if (pending & CAUSEF_IP5)
2614 + ar2315_pci_irq(AR2315_IRQ_LCBUS_PCI);
2615 +#endif
2616 + else if (pending & CAUSEF_IP2) {
2617 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) & ar231x_read_reg(AR2315_IMR);
2618 +
2619 + if (misc_intr & AR2315_ISR_SPI)
2620 + do_IRQ(AR531X_MISC_IRQ_SPI);
2621 + else if (misc_intr & AR2315_ISR_TIMER)
2622 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2623 + else if (misc_intr & AR2315_ISR_AHB)
2624 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2625 + else if (misc_intr & AR2315_ISR_GPIO)
2626 + ar2315_gpio_irq();
2627 + else if (misc_intr & AR2315_ISR_UART0)
2628 + do_IRQ(AR531X_MISC_IRQ_UART0);
2629 + else if (misc_intr & AR2315_ISR_WD)
2630 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2631 + else
2632 + do_IRQ(AR531X_MISC_IRQ_NONE);
2633 + } else if (pending & CAUSEF_IP7)
2634 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2635 +}
2636 +
2637 +static void ar2315_set_gpiointmask(int gpio, int level)
2638 +{
2639 + u32 reg;
2640 +
2641 +
2642 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2643 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2644 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2645 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2646 +}
2647 +
2648 +static void ar2315_gpio_intr_enable(unsigned int irq)
2649 +{
2650 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2651 + u32 reg;
2652 +
2653 + gpiointmask &= ~(1 << gpio);
2654 +
2655 + /* reconfigure GPIO line as input */
2656 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2657 + reg &= ~(AR2315_GPIO_CR_M(gpio));
2658 + reg |= AR2315_GPIO_CR_I(gpio);
2659 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2660 +
2661 + /* Enable interrupt with edge detection */
2662 + ar2315_set_gpiointmask(gpio, 3);
2663 +}
2664 +
2665 +static void ar2315_gpio_intr_disable(unsigned int irq)
2666 +{
2667 + unsigned int gpio = irq - AR531X_GPIO_IRQ_BASE;
2668 +
2669 + gpiointmask |= (1 << gpio);
2670 +
2671 + /* Disable interrupt */
2672 + ar2315_set_gpiointmask(gpio, 0);
2673 +}
2674 +
2675 +static struct irq_chip ar2315_gpio_intr_controller = {
2676 + .typename = "AR2315-GPIO",
2677 + .disable = ar2315_gpio_intr_disable,
2678 + .ack = ar2315_gpio_intr_disable,
2679 + .mask_ack = ar2315_gpio_intr_disable,
2680 + .unmask = ar2315_gpio_intr_enable,
2681 + .eoi = ar2315_gpio_intr_enable,
2682 +};
2683 +
2684 +static void
2685 +ar2315_misc_intr_enable(unsigned int irq)
2686 +{
2687 + unsigned int imr;
2688 +
2689 + imr = ar231x_read_reg(AR2315_IMR);
2690 + switch(irq) {
2691 + case AR531X_MISC_IRQ_SPI:
2692 + imr |= AR2315_ISR_SPI;
2693 + break;
2694 + case AR531X_MISC_IRQ_TIMER:
2695 + imr |= AR2315_ISR_TIMER;
2696 + break;
2697 + case AR531X_MISC_IRQ_AHB_PROC:
2698 + imr |= AR2315_ISR_AHB;
2699 + break;
2700 + case AR531X_MISC_IRQ_GPIO:
2701 + imr |= AR2315_ISR_GPIO;
2702 + break;
2703 + case AR531X_MISC_IRQ_UART0:
2704 + imr |= AR2315_ISR_UART0;
2705 + break;
2706 + case AR531X_MISC_IRQ_WATCHDOG:
2707 + imr |= AR2315_ISR_WD;
2708 + break;
2709 + default:
2710 + break;
2711 + }
2712 + ar231x_write_reg(AR2315_IMR, imr);
2713 +}
2714 +
2715 +static void
2716 +ar2315_misc_intr_disable(unsigned int irq)
2717 +{
2718 + unsigned int imr;
2719 +
2720 + imr = ar231x_read_reg(AR2315_IMR);
2721 + switch(irq) {
2722 + case AR531X_MISC_IRQ_SPI:
2723 + imr &= ~AR2315_ISR_SPI;
2724 + break;
2725 + case AR531X_MISC_IRQ_TIMER:
2726 + imr &= ~AR2315_ISR_TIMER;
2727 + break;
2728 + case AR531X_MISC_IRQ_AHB_PROC:
2729 + imr &= ~AR2315_ISR_AHB;
2730 + break;
2731 + case AR531X_MISC_IRQ_GPIO:
2732 + imr &= ~AR2315_ISR_GPIO;
2733 + break;
2734 + case AR531X_MISC_IRQ_UART0:
2735 + imr &= ~AR2315_ISR_UART0;
2736 + break;
2737 + case AR531X_MISC_IRQ_WATCHDOG:
2738 + imr &= ~AR2315_ISR_WD;
2739 + break;
2740 + default:
2741 + break;
2742 + }
2743 + ar231x_write_reg(AR2315_IMR, imr);
2744 +}
2745 +
2746 +static unsigned int
2747 +ar2315_misc_intr_startup(unsigned int irq)
2748 +{
2749 + ar2315_misc_intr_enable(irq);
2750 + return 0;
2751 +}
2752 +
2753 +static void
2754 +ar2315_misc_intr_end(unsigned int irq)
2755 +{
2756 + if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
2757 + ar2315_misc_intr_enable(irq);
2758 +}
2759 +
2760 +
2761 +static struct irq_chip ar2315_misc_intr_controller = {
2762 + .typename = "AR2315-MISC",
2763 + .startup = ar2315_misc_intr_startup,
2764 + .shutdown = ar2315_misc_intr_disable,
2765 + .enable = ar2315_misc_intr_enable,
2766 + .disable = ar2315_misc_intr_disable,
2767 + .ack = ar2315_misc_intr_disable,
2768 + .end = ar2315_misc_intr_end,
2769 +};
2770 +
2771 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2772 +{
2773 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2774 + ar231x_read_reg(AR2315_AHB_ERR1);
2775 +
2776 + printk(KERN_ERR "AHB fatal error\n");
2777 + machine_restart("AHB error"); /* Catastrophic failure */
2778 +
2779 + return IRQ_HANDLED;
2780 +}
2781 +
2782 +static struct irqaction ar2315_ahb_proc_interrupt = {
2783 + .handler = ar2315_ahb_proc_handler,
2784 + .flags = IRQF_DISABLED,
2785 + .name = "ar2315_ahb_proc_interrupt",
2786 +};
2787 +
2788 +static struct irqaction cascade = {
2789 + .handler = no_action,
2790 + .flags = IRQF_DISABLED,
2791 + .name = "cascade",
2792 +};
2793 +
2794 +void
2795 +ar2315_irq_init(void)
2796 +{
2797 + int i;
2798 +
2799 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2800 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2801 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2802 + int irq = AR531X_MISC_IRQ_BASE + i;
2803 + irq_desc[irq].status = IRQ_DISABLED;
2804 + irq_desc[irq].action = NULL;
2805 + irq_desc[irq].depth = 1;
2806 + irq_desc[irq].chip = &ar2315_misc_intr_controller;
2807 + }
2808 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2809 + int irq = AR531X_GPIO_IRQ_BASE + i;
2810 + irq_desc[irq].status = IRQ_DISABLED;
2811 + irq_desc[irq].action = NULL;
2812 + irq_desc[irq].depth = 1;
2813 + irq_desc[irq].chip = &ar2315_gpio_intr_controller;
2814 + }
2815 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2816 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2817 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2818 +}
2819 +
2820 +const struct ar231x_gpiodev ar2315_gpiodev;
2821 +
2822 +static u32
2823 +ar2315_gpio_get_output(void)
2824 +{
2825 + u32 reg;
2826 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2827 + reg &= ar2315_gpiodev.valid_mask;
2828 + return reg;
2829 +}
2830 +
2831 +static u32
2832 +ar2315_gpio_set_output(u32 mask, u32 val)
2833 +{
2834 + u32 reg;
2835 +
2836 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2837 + reg &= ~mask;
2838 + reg |= val;
2839 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2840 + return reg;
2841 +}
2842 +
2843 +static u32
2844 +ar2315_gpio_get(void)
2845 +{
2846 + u32 reg;
2847 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2848 + reg &= ar2315_gpiodev.valid_mask;
2849 + return reg;
2850 +}
2851 +
2852 +static u32
2853 +ar2315_gpio_set(u32 mask, u32 value)
2854 +{
2855 + u32 reg;
2856 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2857 + reg &= ~mask;
2858 + reg |= value;
2859 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2860 + return reg;
2861 +}
2862 +
2863 +const struct ar231x_gpiodev ar2315_gpiodev = {
2864 + .valid_mask = (1 << 22) - 1,
2865 + .get_output = ar2315_gpio_get_output,
2866 + .set_output = ar2315_gpio_set_output,
2867 + .get = ar2315_gpio_get,
2868 + .set = ar2315_gpio_set,
2869 +};
2870 +
2871 +static struct ar231x_eth ar2315_eth_data = {
2872 + .reset_base = AR2315_RESET,
2873 + .reset_mac = AR2315_RESET_ENET0,
2874 + .reset_phy = AR2315_RESET_EPHY0,
2875 + .phy_base = AR2315_ENET0,
2876 + .config = &ar231x_board,
2877 +};
2878 +
2879 +static struct resource ar2315_spiflash_res[] = {
2880 + {
2881 + .name = "flash_base",
2882 + .flags = IORESOURCE_MEM,
2883 + .start = KSEG1ADDR(AR2315_SPI_READ),
2884 + .end = KSEG1ADDR(AR2315_SPI_READ) + 0x1000000 - 1,
2885 + },
2886 + {
2887 + .name = "flash_regs",
2888 + .flags = IORESOURCE_MEM,
2889 + .start = 0x11300000,
2890 + .end = 0x11300012,
2891 + },
2892 +};
2893 +
2894 +static struct platform_device ar2315_spiflash = {
2895 + .id = 0,
2896 + .name = "spiflash",
2897 + .resource = ar2315_spiflash_res,
2898 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2899 +};
2900 +
2901 +static struct platform_device ar2315_wdt = {
2902 + .id = 0,
2903 + .name = "ar2315_wdt",
2904 +};
2905 +
2906 +#define SPI_FLASH_CTL 0x00
2907 +#define SPI_FLASH_OPCODE 0x04
2908 +#define SPI_FLASH_DATA 0x08
2909 +
2910 +static inline u32
2911 +spiflash_read_reg(int reg)
2912 +{
2913 + return ar231x_read_reg(KSEG1ADDR(AR2315_SPI) + reg);
2914 +}
2915 +
2916 +static inline void
2917 +spiflash_write_reg(int reg, u32 data)
2918 +{
2919 + ar231x_write_reg(KSEG1ADDR(AR2315_SPI) + reg, data);
2920 +}
2921 +
2922 +static u32
2923 +spiflash_wait_status(void)
2924 +{
2925 + u32 reg;
2926 +
2927 + do {
2928 + reg = spiflash_read_reg(SPI_FLASH_CTL);
2929 + } while (reg & SPI_CTL_BUSY);
2930 +
2931 + return reg;
2932 +}
2933 +
2934 +static u8
2935 +spiflash_probe(void)
2936 +{
2937 + u32 reg;
2938 +
2939 + reg = spiflash_wait_status();
2940 + reg &= ~SPI_CTL_TX_RX_CNT_MASK;
2941 + reg |= (1 << 4) | 4 | SPI_CTL_START;
2942 +
2943 + spiflash_write_reg(SPI_FLASH_OPCODE, 0xab);
2944 + spiflash_write_reg(SPI_FLASH_CTL, reg);
2945 +
2946 + reg = spiflash_wait_status();
2947 + reg = spiflash_read_reg(SPI_FLASH_DATA);
2948 + reg &= 0xff;
2949 +
2950 + return (u8) reg;
2951 +}
2952 +
2953 +
2954 +#define STM_8MBIT_SIGNATURE 0x13
2955 +#define STM_16MBIT_SIGNATURE 0x14
2956 +#define STM_32MBIT_SIGNATURE 0x15
2957 +#define STM_64MBIT_SIGNATURE 0x16
2958 +#define STM_128MBIT_SIGNATURE 0x17
2959 +
2960 +static u8 __init *
2961 +ar2315_flash_limit(void)
2962 +{
2963 + u32 flash_size = 0;
2964 +
2965 + /* probe the flash chip size */
2966 + switch(spiflash_probe()) {
2967 + case STM_8MBIT_SIGNATURE:
2968 + flash_size = 0x00100000;
2969 + break;
2970 + case STM_16MBIT_SIGNATURE:
2971 + flash_size = 0x00200000;
2972 + break;
2973 + case STM_32MBIT_SIGNATURE:
2974 + flash_size = 0x00400000;
2975 + break;
2976 + case STM_64MBIT_SIGNATURE:
2977 + flash_size = 0x00800000;
2978 + break;
2979 + case STM_128MBIT_SIGNATURE:
2980 + flash_size = 0x01000000;
2981 + break;
2982 + }
2983 +
2984 + ar2315_spiflash_res[0].end = ar2315_spiflash_res[0].start +
2985 + flash_size - 1;
2986 + return (u8 *) ar2315_spiflash_res[0].end + 1;
2987 +}
2988 +
2989 +#ifdef CONFIG_LEDS_GPIO
2990 +static struct gpio_led ar2315_leds[6];
2991 +static struct gpio_led_platform_data ar2315_led_data = {
2992 + .leds = (void *) ar2315_leds,
2993 +};
2994 +
2995 +static struct platform_device ar2315_gpio_leds = {
2996 + .name = "leds-gpio",
2997 + .id = -1,
2998 + .dev = {
2999 + .platform_data = (void *) &ar2315_led_data,
3000 + }
3001 +};
3002 +
3003 +static void __init
3004 +ar2315_init_gpio(void)
3005 +{
3006 + static char led_names[6][6];
3007 + int i, led = 0;
3008 +
3009 + ar2315_led_data.num_leds = 0;
3010 + for(i = 1; i < 8; i++)
3011 + {
3012 + if((i == AR2315_RESET_GPIO) ||
3013 + (i == ar231x_board.config->resetConfigGpio))
3014 + continue;
3015 +
3016 + if(i == ar231x_board.config->sysLedGpio)
3017 + strcpy(led_names[led], "wlan");
3018 + else
3019 + sprintf(led_names[led], "gpio%d", i);
3020 +
3021 + ar2315_leds[led].name = led_names[led];
3022 + ar2315_leds[led].gpio = i;
3023 + ar2315_leds[led].active_low = 0;
3024 + led++;
3025 + }
3026 + ar2315_led_data.num_leds = led;
3027 + platform_device_register(&ar2315_gpio_leds);
3028 +}
3029 +#else
3030 +static inline void ar2315_init_gpio(void)
3031 +{
3032 +}
3033 +#endif
3034 +
3035 +int __init
3036 +ar2315_init_devices(void)
3037 +{
3038 + if (!IS_2315())
3039 + return 0;
3040 +
3041 + /* Find board configuration */
3042 + ar231x_find_config(ar2315_flash_limit());
3043 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
3044 +
3045 + ar2315_init_gpio();
3046 + platform_device_register(&ar2315_wdt);
3047 + platform_device_register(&ar2315_spiflash);
3048 + ar231x_add_ethernet(0, AR2315_ENET0, AR2315_IRQ_ENET0_INTRS,
3049 + &ar2315_eth_data);
3050 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
3051 +
3052 + return 0;
3053 +}
3054 +
3055 +static void
3056 +ar2315_restart(char *command)
3057 +{
3058 + void (*mips_reset_vec)(void) = (void *) 0xbfc00000;
3059 +
3060 + local_irq_disable();
3061 +
3062 + /* try reset the system via reset control */
3063 + ar231x_write_reg(AR2315_COLD_RESET,AR2317_RESET_SYSTEM);
3064 +
3065 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits a workaround.
3066 + * give it some time to attempt a gpio based hardware reset
3067 + * (atheros reference design workaround) */
3068 + gpio_direction_output(AR2315_RESET_GPIO, 0);
3069 + mdelay(100);
3070 +
3071 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
3072 + * workaround. Attempt to jump to the mips reset location -
3073 + * the boot loader itself might be able to recover the system */
3074 + mips_reset_vec();
3075 +}
3076 +
3077 +
3078 +/*
3079 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
3080 + * to determine the predevisor value.
3081 + */
3082 +static int __initdata CLOCKCTL1_PREDIVIDE_TABLE[4] = {
3083 + 1,
3084 + 2,
3085 + 4,
3086 + 5
3087 +};
3088 +
3089 +static int __initdata PLLC_DIVIDE_TABLE[5] = {
3090 + 2,
3091 + 3,
3092 + 4,
3093 + 6,
3094 + 3
3095 +};
3096 +
3097 +static unsigned int __init
3098 +ar2315_sys_clk(unsigned int clockCtl)
3099 +{
3100 + unsigned int pllcCtrl,cpuDiv;
3101 + unsigned int pllcOut,refdiv,fdiv,divby2;
3102 + unsigned int clkDiv;
3103 +
3104 + pllcCtrl = ar231x_read_reg(AR2315_PLLC_CTL);
3105 + refdiv = (pllcCtrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
3106 + refdiv = CLOCKCTL1_PREDIVIDE_TABLE[refdiv];
3107 + fdiv = (pllcCtrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
3108 + divby2 = (pllcCtrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
3109 + divby2 += 1;
3110 + pllcOut = (40000000/refdiv)*(2*divby2)*fdiv;
3111 +
3112 +
3113 + /* clkm input selected */
3114 + switch(clockCtl & CPUCLK_CLK_SEL_M) {
3115 + case 0:
3116 + case 1:
3117 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKM_DIV_M) >> PLLC_CLKM_DIV_S];
3118 + break;
3119 + case 2:
3120 + clkDiv = PLLC_DIVIDE_TABLE[(pllcCtrl & PLLC_CLKC_DIV_M) >> PLLC_CLKC_DIV_S];
3121 + break;
3122 + default:
3123 + pllcOut = 40000000;
3124 + clkDiv = 1;
3125 + break;
3126 + }
3127 + cpuDiv = (clockCtl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
3128 + cpuDiv = cpuDiv * 2 ?: 1;
3129 + return (pllcOut/(clkDiv * cpuDiv));
3130 +}
3131 +
3132 +static inline unsigned int
3133 +ar2315_cpu_frequency(void)
3134 +{
3135 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
3136 +}
3137 +
3138 +static inline unsigned int
3139 +ar2315_apb_frequency(void)
3140 +{
3141 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
3142 +}
3143 +
3144 +void __init
3145 +ar2315_time_init(void)
3146 +{
3147 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
3148 +}
3149 +
3150 +void __init
3151 +ar2315_prom_init(void)
3152 +{
3153 + u32 memsize, memcfg, devid;
3154 +
3155 + if (!IS_2315())
3156 + return;
3157 +
3158 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
3159 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
3160 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
3161 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
3162 + memsize <<= 3;
3163 + add_memory_region(0, memsize, BOOT_MEM_RAM);
3164 +
3165 + /* Detect the hardware based on the device ID */
3166 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
3167 + switch(devid) {
3168 + case 0x90:
3169 + case 0x91:
3170 + ar231x_devtype = DEV_TYPE_AR2317;
3171 + break;
3172 + default:
3173 + ar231x_devtype = DEV_TYPE_AR2315;
3174 + break;
3175 + }
3176 + ar231x_gpiodev = &ar2315_gpiodev;
3177 + ar231x_board.devid = devid;
3178 +}
3179 +
3180 +void __init
3181 +ar2315_plat_setup(void)
3182 +{
3183 + u32 config;
3184 +
3185 + if (!IS_2315())
3186 + return;
3187 +
3188 + /* Clear any lingering AHB errors */
3189 + config = read_c0_config();
3190 + write_c0_config(config & ~0x3);
3191 + ar231x_write_reg(AR2315_AHB_ERR0,AHB_ERROR_DET);
3192 + ar231x_read_reg(AR2315_AHB_ERR1);
3193 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
3194 +
3195 + _machine_restart = ar2315_restart;
3196 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), ar2315_apb_frequency());
3197 +}
3198 --- /dev/null
3199 +++ b/arch/mips/ar231x/ar2315.h
3200 @@ -0,0 +1,37 @@
3201 +#ifndef __AR2315_H
3202 +#define __AR2315_H
3203 +
3204 +#ifdef CONFIG_ATHEROS_AR2315
3205 +
3206 +extern void ar2315_irq_init(void);
3207 +extern int ar2315_init_devices(void);
3208 +extern void ar2315_prom_init(void);
3209 +extern void ar2315_plat_setup(void);
3210 +extern void ar2315_time_init(void);
3211 +
3212 +#else
3213 +
3214 +static inline void ar2315_irq_init(void)
3215 +{
3216 +}
3217 +
3218 +static inline int ar2315_init_devices(void)
3219 +{
3220 + return 0;
3221 +}
3222 +
3223 +static inline void ar2315_prom_init(void)
3224 +{
3225 +}
3226 +
3227 +static inline void ar2315_plat_setup(void)
3228 +{
3229 +}
3230 +
3231 +static inline void ar2315_time_init(void)
3232 +{
3233 +}
3234 +
3235 +#endif
3236 +
3237 +#endif
3238 --- /dev/null
3239 +++ b/arch/mips/ar231x/ar5312.h
3240 @@ -0,0 +1,38 @@
3241 +#ifndef __AR5312_H
3242 +#define __AR5312_H
3243 +
3244 +#ifdef CONFIG_ATHEROS_AR5312
3245 +
3246 +extern void ar5312_irq_init(void);
3247 +extern int ar5312_init_devices(void);
3248 +extern void ar5312_prom_init(void);
3249 +extern void ar5312_plat_setup(void);
3250 +extern void ar5312_time_init(void);
3251 +extern void ar5312_time_init(void);
3252 +
3253 +#else
3254 +
3255 +static inline void ar5312_irq_init(void)
3256 +{
3257 +}
3258 +
3259 +static inline int ar5312_init_devices(void)
3260 +{
3261 + return 0;
3262 +}
3263 +
3264 +static inline void ar5312_prom_init(void)
3265 +{
3266 +}
3267 +
3268 +static inline void ar5312_plat_setup(void)
3269 +{
3270 +}
3271 +
3272 +static inline void ar5312_time_init(void)
3273 +{
3274 +}
3275 +
3276 +#endif
3277 +
3278 +#endif
3279 --- /dev/null
3280 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
3281 @@ -0,0 +1,54 @@
3282 +#ifndef __AR531X_H
3283 +#define __AR531X_H
3284 +
3285 +#define AR531X_MISC_IRQ_BASE 0x20
3286 +#define AR531X_GPIO_IRQ_BASE 0x30
3287 +
3288 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
3289 +#define AR531X_IRQ_NONE MIPS_CPU_IRQ_BASE+0
3290 +#define AR531X_IRQ_CPU_CLOCK MIPS_CPU_IRQ_BASE+7 /* C0_CAUSE: 0x8000 */
3291 +
3292 +/* Miscellaneous interrupts, which share IP6 */
3293 +#define AR531X_MISC_IRQ_NONE AR531X_MISC_IRQ_BASE+0
3294 +#define AR531X_MISC_IRQ_TIMER AR531X_MISC_IRQ_BASE+1
3295 +#define AR531X_MISC_IRQ_AHB_PROC AR531X_MISC_IRQ_BASE+2
3296 +#define AR531X_MISC_IRQ_AHB_DMA AR531X_MISC_IRQ_BASE+3
3297 +#define AR531X_MISC_IRQ_GPIO AR531X_MISC_IRQ_BASE+4
3298 +#define AR531X_MISC_IRQ_UART0 AR531X_MISC_IRQ_BASE+5
3299 +#define AR531X_MISC_IRQ_UART0_DMA AR531X_MISC_IRQ_BASE+6
3300 +#define AR531X_MISC_IRQ_WATCHDOG AR531X_MISC_IRQ_BASE+7
3301 +#define AR531X_MISC_IRQ_LOCAL AR531X_MISC_IRQ_BASE+8
3302 +#define AR531X_MISC_IRQ_SPI AR531X_MISC_IRQ_BASE+9
3303 +#define AR531X_MISC_IRQ_COUNT 10
3304 +
3305 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
3306 +#define AR531X_GPIO_IRQ_NONE AR531X_GPIO_IRQ_BASE+0
3307 +#define AR531X_GPIO_IRQ(n) AR531X_GPIO_IRQ_BASE+n
3308 +#define AR531X_GPIO_IRQ_COUNT 22
3309 +
3310 +static inline u32
3311 +ar231x_read_reg(u32 reg)
3312 +{
3313 + return __raw_readl((u32 *) reg);
3314 +}
3315 +
3316 +static inline void
3317 +ar231x_write_reg(u32 reg, u32 val)
3318 +{
3319 + __raw_writel(val, (u32 *)reg);
3320 +}
3321 +
3322 +static inline u32
3323 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
3324 +{
3325 + u32 ret;
3326 +
3327 + ret = ar231x_read_reg(reg);
3328 + ret &= ~mask;
3329 + ret |= val;
3330 + ar231x_write_reg(reg, ret);
3331 +
3332 + return ret;
3333 +}
3334 +
3335 +#endif
3336 --- /dev/null
3337 +++ b/arch/mips/ar231x/devices.h
3338 @@ -0,0 +1,27 @@
3339 +#ifndef __AR231X_DEVICES_H
3340 +#define __AR231X_DEVICES_H
3341 +
3342 +enum {
3343 + /* handled by ar5312.c */
3344 + DEV_TYPE_AR2312,
3345 + DEV_TYPE_AR2313,
3346 + DEV_TYPE_AR5312,
3347 +
3348 + /* handled by ar2315.c */
3349 + DEV_TYPE_AR2315,
3350 + DEV_TYPE_AR2316,
3351 + DEV_TYPE_AR2317,
3352 +
3353 + DEV_TYPE_UNKNOWN
3354 +};
3355 +
3356 +extern int ar231x_devtype;
3357 +extern struct ar231x_board_config ar231x_board;
3358 +extern void (*ar231x_irq_dispatch)(void);
3359 +
3360 +extern int ar231x_find_config(u8 *flash_limit);
3361 +extern void ar231x_serial_setup(u32 mapbase, unsigned int uartclk);
3362 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
3363 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
3364 +
3365 +#endif
3366 --- /dev/null
3367 +++ b/arch/mips/ar231x/devices.c
3368 @@ -0,0 +1,174 @@
3369 +#include <linux/kernel.h>
3370 +#include <linux/init.h>
3371 +#include <linux/serial.h>
3372 +#include <linux/serial_core.h>
3373 +#include <linux/serial_8250.h>
3374 +#include <linux/platform_device.h>
3375 +#include <ar231x_platform.h>
3376 +#include <ar231x.h>
3377 +#include "devices.h"
3378 +#include "ar5312.h"
3379 +#include "ar2315.h"
3380 +
3381 +struct ar231x_board_config ar231x_board;
3382 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
3383 +const struct ar231x_gpiodev *ar231x_gpiodev;
3384 +
3385 +static struct resource ar231x_eth0_res[] = {
3386 + {
3387 + .name = "eth0_membase",
3388 + .flags = IORESOURCE_MEM,
3389 + },
3390 + {
3391 + .name = "eth0_irq",
3392 + .flags = IORESOURCE_IRQ,
3393 + }
3394 +};
3395 +
3396 +static struct resource ar231x_eth1_res[] = {
3397 + {
3398 + .name = "eth1_membase",
3399 + .flags = IORESOURCE_MEM,
3400 + },
3401 + {
3402 + .name = "eth1_irq",
3403 + .flags = IORESOURCE_IRQ,
3404 + }
3405 +};
3406 +
3407 +static struct platform_device ar231x_eth[] = {
3408 + {
3409 + .id = 0,
3410 + .name = "ar231x-eth",
3411 + .resource = ar231x_eth0_res,
3412 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3413 + },
3414 + {
3415 + .id = 1,
3416 + .name = "ar231x-eth",
3417 + .resource = ar231x_eth1_res,
3418 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3419 + }
3420 +};
3421 +
3422 +static struct resource ar231x_wmac0_res[] = {
3423 + {
3424 + .name = "wmac0_membase",
3425 + .flags = IORESOURCE_MEM,
3426 + },
3427 + {
3428 + .name = "wmac0_irq",
3429 + .flags = IORESOURCE_IRQ,
3430 + }
3431 +};
3432 +
3433 +static struct resource ar231x_wmac1_res[] = {
3434 + {
3435 + .name = "wmac1_membase",
3436 + .flags = IORESOURCE_MEM,
3437 + },
3438 + {
3439 + .name = "wmac1_irq",
3440 + .flags = IORESOURCE_IRQ,
3441 + }
3442 +};
3443 +
3444 +
3445 +static struct platform_device ar231x_wmac[] = {
3446 + {
3447 + .id = 0,
3448 + .name = "ar231x-wmac",
3449 + .resource = ar231x_wmac0_res,
3450 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3451 + .dev.platform_data = &ar231x_board,
3452 + },
3453 + {
3454 + .id = 1,
3455 + .name = "ar231x-wmac",
3456 + .resource = ar231x_wmac1_res,
3457 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3458 + .dev.platform_data = &ar231x_board,
3459 + },
3460 +};
3461 +
3462 +static const char *devtype_strings[] = {
3463 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3464 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3465 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3466 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3467 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3468 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3469 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3470 +};
3471 +
3472 +const char *get_system_type(void)
3473 +{
3474 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3475 + !devtype_strings[ar231x_devtype])
3476 + return devtype_strings[DEV_TYPE_UNKNOWN];
3477 + return devtype_strings[ar231x_devtype];
3478 +}
3479 +
3480 +
3481 +int __init
3482 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3483 +{
3484 + struct resource *res;
3485 +
3486 + ar231x_eth[nr].dev.platform_data = pdata;
3487 + res = &ar231x_eth[nr].resource[0];
3488 + res->start = base;
3489 + res->end = base + 0x2000 - 1;
3490 + res++;
3491 + res->start = irq;
3492 + res->end = irq;
3493 + return platform_device_register(&ar231x_eth[nr]);
3494 +}
3495 +
3496 +void __init
3497 +ar231x_serial_setup(u32 mapbase, unsigned int uartclk)
3498 +{
3499 + struct uart_port s;
3500 +
3501 + memset(&s, 0, sizeof(s));
3502 +
3503 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3504 + s.iotype = UPIO_MEM;
3505 + s.irq = AR531X_MISC_IRQ_UART0;
3506 + s.regshift = 2;
3507 + s.mapbase = mapbase;
3508 + s.uartclk = uartclk;
3509 + s.membase = (void __iomem *)s.mapbase;
3510 +
3511 + early_serial_setup(&s);
3512 +}
3513 +
3514 +int __init
3515 +ar231x_add_wmac(int nr, u32 base, int irq)
3516 +{
3517 + struct resource *res;
3518 +
3519 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3520 + res = &ar231x_wmac[nr].resource[0];
3521 + res->start = base;
3522 + res->end = base + 0x10000 - 1;
3523 + res++;
3524 + res->start = irq;
3525 + res->end = irq;
3526 + return platform_device_register(&ar231x_wmac[nr]);
3527 +}
3528 +
3529 +static int __init ar231x_register_devices(void)
3530 +{
3531 + static struct resource res = {
3532 + .start = 0xFFFFFFFF,
3533 + };
3534 +
3535 + platform_device_register_simple("GPIODEV", 0, &res, 1);
3536 + ar5312_init_devices();
3537 + ar2315_init_devices();
3538 +
3539 + return 0;
3540 +}
3541 +
3542 +device_initcall(ar231x_register_devices);
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