012009a91a31773a65458066b89c97d0a7a24701
[openwrt/staging/florian.git] / target / linux / brcm-2.4 / files / arch / mips / bcm947xx / pcibios.c
1 /*
2 * Low-Level PCI and SB support for BCM47xx (Linux support code)
3 *
4 * Copyright 2006, Broadcom Corporation
5 * All Rights Reserved.
6 *
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11 *
12 * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
13 */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <asm/io.h>
23 #include <asm/irq.h>
24 #include <asm/paccess.h>
25
26 #include <typedefs.h>
27 #include <osl.h>
28 #include <bcmutils.h>
29 #include <sbconfig.h>
30 #include <sbutils.h>
31 #include <hndpci.h>
32 #include <pcicfg.h>
33 #include <bcmdevs.h>
34 #include <bcmnvram.h>
35
36 /* Global SB handle */
37 extern sb_t *bcm947xx_sbh;
38 extern spinlock_t bcm947xx_sbh_lock;
39
40 /* Convenience */
41 #define sbh bcm947xx_sbh
42 #define sbh_lock bcm947xx_sbh_lock
43
44 static int
45 sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
46 {
47 unsigned long flags;
48 int ret;
49
50 spin_lock_irqsave(&sbh_lock, flags);
51 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
52 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
53 spin_unlock_irqrestore(&sbh_lock, flags);
54 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
55 }
56
57 static int
58 sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
59 {
60 unsigned long flags;
61 int ret;
62
63 spin_lock_irqsave(&sbh_lock, flags);
64 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
65 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
66 spin_unlock_irqrestore(&sbh_lock, flags);
67 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
68 }
69
70 static int
71 sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
72 {
73 unsigned long flags;
74 int ret;
75
76 spin_lock_irqsave(&sbh_lock, flags);
77 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
78 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
79 spin_unlock_irqrestore(&sbh_lock, flags);
80 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
81 }
82
83 static int
84 sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
85 {
86 unsigned long flags;
87 int ret;
88
89 spin_lock_irqsave(&sbh_lock, flags);
90 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
91 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
92 spin_unlock_irqrestore(&sbh_lock, flags);
93 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
94 }
95
96 static int
97 sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
98 {
99 unsigned long flags;
100 int ret;
101
102 spin_lock_irqsave(&sbh_lock, flags);
103 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
104 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
105 spin_unlock_irqrestore(&sbh_lock, flags);
106 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
107 }
108
109 static int
110 sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
111 {
112 unsigned long flags;
113 int ret;
114
115 spin_lock_irqsave(&sbh_lock, flags);
116 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
117 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
118 spin_unlock_irqrestore(&sbh_lock, flags);
119 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
120 }
121
122 static struct pci_ops pcibios_ops = {
123 sbpci_read_config_byte,
124 sbpci_read_config_word,
125 sbpci_read_config_dword,
126 sbpci_write_config_byte,
127 sbpci_write_config_word,
128 sbpci_write_config_dword
129 };
130
131
132 void __init
133 pcibios_init(void)
134 {
135 ulong flags;
136
137 if (!(sbh = sb_kattach()))
138 panic("sb_kattach failed");
139 spin_lock_init(&sbh_lock);
140
141 spin_lock_irqsave(&sbh_lock, flags);
142 sbpci_init(sbh);
143 spin_unlock_irqrestore(&sbh_lock, flags);
144
145 set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
146
147 /* Scan the SB bus */
148 pci_scan_bus(0, &pcibios_ops, NULL);
149
150 }
151
152 char * __init
153 pcibios_setup(char *str)
154 {
155 if (!strncmp(str, "ban=", 4)) {
156 sbpci_ban(simple_strtoul(str + 4, NULL, 0));
157 return NULL;
158 }
159
160 return (str);
161 }
162
163 static u32 pci_iobase = 0x100;
164 static u32 pci_membase = SB_PCI_DMA;
165 static u32 pcmcia_membase = 0x40004000;
166
167 void __init
168 pcibios_fixup_bus(struct pci_bus *b)
169 {
170 struct list_head *ln;
171 struct pci_dev *d;
172 struct resource *res;
173 int pos, size;
174 u32 *base;
175 u8 irq;
176
177 printk("PCI: Fixing up bus %d\n", b->number);
178
179 /* Fix up SB */
180 if (b->number == 0) {
181 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
182 d = pci_dev_b(ln);
183 /* Fix up interrupt lines */
184 pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
185 d->irq = irq + 2;
186 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
187 }
188 }
189
190 /* Fix up external PCI */
191 else {
192 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
193 d = pci_dev_b(ln);
194 /* Fix up resource bases */
195 for (pos = 0; pos < 6; pos++) {
196 res = &d->resource[pos];
197 base = (res->flags & IORESOURCE_IO) ? &pci_iobase : ((b->number == 2) ? &pcmcia_membase : &pci_membase);
198 if (res->end) {
199 size = res->end - res->start + 1;
200 if (*base & (size - 1))
201 *base = (*base + size) & ~(size - 1);
202 res->start = *base;
203 res->end = res->start + size - 1;
204 *base += size;
205 pci_write_config_dword(d,
206 PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
207 }
208 /* Fix up PCI bridge BAR0 only */
209 if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
210 break;
211 }
212 /* Fix up interrupt lines */
213 if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
214 d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
215 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
216 }
217 }
218 }
219
220 unsigned int
221 pcibios_assign_all_busses(void)
222 {
223 return 1;
224 }
225
226 void
227 pcibios_align_resource(void *data, struct resource *res,
228 unsigned long size, unsigned long align)
229 {
230 }
231
232 int
233 pcibios_enable_resources(struct pci_dev *dev)
234 {
235 u16 cmd, old_cmd;
236 int idx;
237 struct resource *r;
238
239 /* External PCI only */
240 if (dev->bus->number == 0)
241 return 0;
242
243 pci_read_config_word(dev, PCI_COMMAND, &cmd);
244 old_cmd = cmd;
245 for (idx = 0; idx < 6; idx++) {
246 r = &dev->resource[idx];
247 if (r->flags & IORESOURCE_IO)
248 cmd |= PCI_COMMAND_IO;
249 if (r->flags & IORESOURCE_MEM)
250 cmd |= PCI_COMMAND_MEMORY;
251 }
252 if (dev->resource[PCI_ROM_RESOURCE].start)
253 cmd |= PCI_COMMAND_MEMORY;
254 if (cmd != old_cmd) {
255 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
256 pci_write_config_word(dev, PCI_COMMAND, cmd);
257 }
258 return 0;
259 }
260
261 int
262 pcibios_enable_device(struct pci_dev *dev, int mask)
263 {
264 ulong flags;
265 uint coreidx;
266 void *regs;
267
268 /* External PCI device enable */
269 if (dev->bus->number != 0)
270 return pcibios_enable_resources(dev);
271
272 /* These cores come out of reset enabled */
273 if (dev->device == SB_MIPS ||
274 dev->device == SB_MIPS33 ||
275 dev->device == SB_EXTIF ||
276 dev->device == SB_CC)
277 return 0;
278
279 spin_lock_irqsave(&sbh_lock, flags);
280 coreidx = sb_coreidx(sbh);
281 regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
282 if (!regs)
283 return PCIBIOS_DEVICE_NOT_FOUND;
284
285 /*
286 * The USB core requires a special bit to be set during core
287 * reset to enable host (OHCI) mode. Resetting the SB core in
288 * pcibios_enable_device() is a hack for compatibility with
289 * vanilla usb-ohci so that it does not have to know about
290 * SB. A driver that wants to use the USB core in device mode
291 * should know about SB and should reset the bit back to 0
292 * after calling pcibios_enable_device().
293 */
294 if (sb_coreid(sbh) == SB_USB) {
295 sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
296 sb_core_reset(sbh, 1 << 29, 0);
297 }
298 /*
299 * USB 2.0 special considerations:
300 *
301 * 1. Since the core supports both OHCI and EHCI functions, it must
302 * only be reset once.
303 *
304 * 2. In addition to the standard SB reset sequence, the Host Control
305 * Register must be programmed to bring the USB core and various
306 * phy components out of reset.
307 */
308 else if (sb_coreid(sbh) == SB_USB20H) {
309 if (!sb_iscoreup(sbh)) {
310 sb_core_reset(sbh, 0, 0);
311 writel(0x7FF, (ulong)regs + 0x200);
312 udelay(1);
313 }
314 } else
315 sb_core_reset(sbh, 0, 0);
316
317 sb_setcoreidx(sbh, coreidx);
318 spin_unlock_irqrestore(&sbh_lock, flags);
319
320 return 0;
321 }
322
323 void
324 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
325 struct resource *res, int resource)
326 {
327 unsigned long where, size;
328 u32 reg;
329
330 /* External PCI only */
331 if (dev->bus->number == 0)
332 return;
333
334 where = PCI_BASE_ADDRESS_0 + (resource * 4);
335 size = res->end - res->start;
336 pci_read_config_dword(dev, where, &reg);
337
338 if (dev->bus->number == 1)
339 reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
340 else
341 reg = res->start;
342
343 pci_write_config_dword(dev, where, reg);
344 }
345
346 static void __init
347 quirk_sbpci_bridge(struct pci_dev *dev)
348 {
349 if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
350 return;
351
352 printk("PCI: Fixing up bridge\n");
353
354 /* Enable PCI bridge bus mastering and memory space */
355 pci_set_master(dev);
356 pcibios_enable_resources(dev);
357
358 /* Enable PCI bridge BAR1 prefetch and burst */
359 pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
360 }
361
362 struct pci_fixup pcibios_fixups[] = {
363 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
364 { 0 }
365 };
366
367 /*
368 * If we set up a device for bus mastering, we need to check the latency
369 * timer as certain crappy BIOSes forget to set it properly.
370 */
371 unsigned int pcibios_max_latency = 255;
372
373 void pcibios_set_master(struct pci_dev *dev)
374 {
375 u8 lat;
376 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
377 if (lat < 16)
378 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
379 else if (lat > pcibios_max_latency)
380 lat = pcibios_max_latency;
381 else
382 return;
383 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
384 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
385 }
386