fix pci init for brcm-2.4 with atheros wifi cards
[openwrt/staging/florian.git] / target / linux / brcm-2.4 / files / arch / mips / bcm947xx / pcibios.c
1 /*
2 * Low-Level PCI and SB support for BCM47xx (Linux support code)
3 *
4 * Copyright 2006, Broadcom Corporation
5 * All Rights Reserved.
6 *
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
11 *
12 * $Id: pcibios.c,v 1.1.1.9 2006/02/27 03:42:55 honor Exp $
13 */
14
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
18 #include <linux/sched.h>
19 #include <linux/pci.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <asm/io.h>
23 #include <asm/irq.h>
24 #include <asm/paccess.h>
25
26 #include <typedefs.h>
27 #include <osl.h>
28 #include <bcmutils.h>
29 #include <sbconfig.h>
30 #include <sbutils.h>
31 #include <hndpci.h>
32 #include <pcicfg.h>
33 #include <bcmdevs.h>
34 #include <bcmnvram.h>
35
36 /* Global SB handle */
37 extern sb_t *bcm947xx_sbh;
38 extern spinlock_t bcm947xx_sbh_lock;
39
40 /* Convenience */
41 #define sbh bcm947xx_sbh
42 #define sbh_lock bcm947xx_sbh_lock
43
44 static int
45 sbpci_read_config_byte(struct pci_dev *dev, int where, u8 *value)
46 {
47 unsigned long flags;
48 int ret;
49
50 spin_lock_irqsave(&sbh_lock, flags);
51 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
52 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
53 spin_unlock_irqrestore(&sbh_lock, flags);
54 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
55 }
56
57 static int
58 sbpci_read_config_word(struct pci_dev *dev, int where, u16 *value)
59 {
60 unsigned long flags;
61 int ret;
62
63 spin_lock_irqsave(&sbh_lock, flags);
64 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
65 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
66 spin_unlock_irqrestore(&sbh_lock, flags);
67 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
68 }
69
70 static int
71 sbpci_read_config_dword(struct pci_dev *dev, int where, u32 *value)
72 {
73 unsigned long flags;
74 int ret;
75
76 spin_lock_irqsave(&sbh_lock, flags);
77 ret = sbpci_read_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
78 PCI_FUNC(dev->devfn), where, value, sizeof(*value));
79 spin_unlock_irqrestore(&sbh_lock, flags);
80 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
81 }
82
83 static int
84 sbpci_write_config_byte(struct pci_dev *dev, int where, u8 value)
85 {
86 unsigned long flags;
87 int ret;
88
89 spin_lock_irqsave(&sbh_lock, flags);
90 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
91 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
92 spin_unlock_irqrestore(&sbh_lock, flags);
93 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
94 }
95
96 static int
97 sbpci_write_config_word(struct pci_dev *dev, int where, u16 value)
98 {
99 unsigned long flags;
100 int ret;
101
102 spin_lock_irqsave(&sbh_lock, flags);
103 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
104 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
105 spin_unlock_irqrestore(&sbh_lock, flags);
106 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
107 }
108
109 static int
110 sbpci_write_config_dword(struct pci_dev *dev, int where, u32 value)
111 {
112 unsigned long flags;
113 int ret;
114
115 spin_lock_irqsave(&sbh_lock, flags);
116 ret = sbpci_write_config(sbh, dev->bus->number, PCI_SLOT(dev->devfn),
117 PCI_FUNC(dev->devfn), where, &value, sizeof(value));
118 spin_unlock_irqrestore(&sbh_lock, flags);
119 return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
120 }
121
122 static struct pci_ops pcibios_ops = {
123 sbpci_read_config_byte,
124 sbpci_read_config_word,
125 sbpci_read_config_dword,
126 sbpci_write_config_byte,
127 sbpci_write_config_word,
128 sbpci_write_config_dword
129 };
130
131
132 void __init
133 pcibios_init(void)
134 {
135 ulong flags;
136
137 if (!(sbh = sb_kattach()))
138 panic("sb_kattach failed");
139 spin_lock_init(&sbh_lock);
140
141 spin_lock_irqsave(&sbh_lock, flags);
142 sbpci_init(sbh);
143 spin_unlock_irqrestore(&sbh_lock, flags);
144
145 set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
146 mdelay(300); /* workaround for atheros cards */
147
148 /* Scan the SB bus */
149 pci_scan_bus(0, &pcibios_ops, NULL);
150
151 }
152
153 char * __init
154 pcibios_setup(char *str)
155 {
156 if (!strncmp(str, "ban=", 4)) {
157 sbpci_ban(simple_strtoul(str + 4, NULL, 0));
158 return NULL;
159 }
160
161 return (str);
162 }
163
164 static u32 pci_iobase = 0x100;
165 static u32 pci_membase = SB_PCI_DMA;
166 static u32 pcmcia_membase = 0x40004000;
167
168 void __init
169 pcibios_fixup_bus(struct pci_bus *b)
170 {
171 struct list_head *ln;
172 struct pci_dev *d;
173 struct resource *res;
174 int pos, size;
175 u32 *base;
176 u8 irq;
177
178 printk("PCI: Fixing up bus %d\n", b->number);
179
180 /* Fix up SB */
181 if (b->number == 0) {
182 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
183 d = pci_dev_b(ln);
184 /* Fix up interrupt lines */
185 pci_read_config_byte(d, PCI_INTERRUPT_LINE, &irq);
186 d->irq = irq + 2;
187 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
188 }
189 }
190
191 /* Fix up external PCI */
192 else {
193 for (ln = b->devices.next; ln != &b->devices; ln = ln->next) {
194 d = pci_dev_b(ln);
195 /* Fix up resource bases */
196 for (pos = 0; pos < 6; pos++) {
197 res = &d->resource[pos];
198 base = (res->flags & IORESOURCE_IO) ? &pci_iobase : ((b->number == 2) ? &pcmcia_membase : &pci_membase);
199 if (res->end) {
200 size = res->end - res->start + 1;
201 if (*base & (size - 1))
202 *base = (*base + size) & ~(size - 1);
203 res->start = *base;
204 res->end = res->start + size - 1;
205 *base += size;
206 pci_write_config_dword(d,
207 PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
208 }
209 /* Fix up PCI bridge BAR0 only */
210 if (b->number == 1 && PCI_SLOT(d->devfn) == 0)
211 break;
212 }
213 /* Fix up interrupt lines */
214 if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
215 d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
216 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
217 }
218 }
219 }
220
221 unsigned int
222 pcibios_assign_all_busses(void)
223 {
224 return 1;
225 }
226
227 void
228 pcibios_align_resource(void *data, struct resource *res,
229 unsigned long size, unsigned long align)
230 {
231 }
232
233 int
234 pcibios_enable_resources(struct pci_dev *dev)
235 {
236 u16 cmd, old_cmd;
237 int idx;
238 struct resource *r;
239
240 /* External PCI only */
241 if (dev->bus->number == 0)
242 return 0;
243
244 pci_read_config_word(dev, PCI_COMMAND, &cmd);
245 old_cmd = cmd;
246 for (idx = 0; idx < 6; idx++) {
247 r = &dev->resource[idx];
248 if (r->flags & IORESOURCE_IO)
249 cmd |= PCI_COMMAND_IO;
250 if (r->flags & IORESOURCE_MEM)
251 cmd |= PCI_COMMAND_MEMORY;
252 }
253 if (dev->resource[PCI_ROM_RESOURCE].start)
254 cmd |= PCI_COMMAND_MEMORY;
255 if (cmd != old_cmd) {
256 printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd);
257 pci_write_config_word(dev, PCI_COMMAND, cmd);
258 }
259 return 0;
260 }
261
262 int
263 pcibios_enable_device(struct pci_dev *dev, int mask)
264 {
265 ulong flags;
266 uint coreidx;
267 void *regs;
268
269 /* External PCI device enable */
270 if (dev->bus->number != 0)
271 return pcibios_enable_resources(dev);
272
273 /* These cores come out of reset enabled */
274 if (dev->device == SB_MIPS ||
275 dev->device == SB_MIPS33 ||
276 dev->device == SB_EXTIF ||
277 dev->device == SB_CC)
278 return 0;
279
280 spin_lock_irqsave(&sbh_lock, flags);
281 coreidx = sb_coreidx(sbh);
282 regs = sb_setcoreidx(sbh, PCI_SLOT(dev->devfn));
283 if (!regs)
284 return PCIBIOS_DEVICE_NOT_FOUND;
285
286 /*
287 * The USB core requires a special bit to be set during core
288 * reset to enable host (OHCI) mode. Resetting the SB core in
289 * pcibios_enable_device() is a hack for compatibility with
290 * vanilla usb-ohci so that it does not have to know about
291 * SB. A driver that wants to use the USB core in device mode
292 * should know about SB and should reset the bit back to 0
293 * after calling pcibios_enable_device().
294 */
295 if (sb_coreid(sbh) == SB_USB) {
296 sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
297 sb_core_reset(sbh, 1 << 29, 0);
298 }
299 /*
300 * USB 2.0 special considerations:
301 *
302 * 1. Since the core supports both OHCI and EHCI functions, it must
303 * only be reset once.
304 *
305 * 2. In addition to the standard SB reset sequence, the Host Control
306 * Register must be programmed to bring the USB core and various
307 * phy components out of reset.
308 */
309 else if (sb_coreid(sbh) == SB_USB20H) {
310 if (!sb_iscoreup(sbh)) {
311 sb_core_reset(sbh, 0, 0);
312 writel(0x7FF, (ulong)regs + 0x200);
313 udelay(1);
314 }
315 } else
316 sb_core_reset(sbh, 0, 0);
317
318 sb_setcoreidx(sbh, coreidx);
319 spin_unlock_irqrestore(&sbh_lock, flags);
320
321 return 0;
322 }
323
324 void
325 pcibios_update_resource(struct pci_dev *dev, struct resource *root,
326 struct resource *res, int resource)
327 {
328 unsigned long where, size;
329 u32 reg;
330
331 /* External PCI only */
332 if (dev->bus->number == 0)
333 return;
334
335 where = PCI_BASE_ADDRESS_0 + (resource * 4);
336 size = res->end - res->start;
337 pci_read_config_dword(dev, where, &reg);
338
339 if (dev->bus->number == 1)
340 reg = (reg & size) | (((u32)(res->start - root->start)) & ~size);
341 else
342 reg = res->start;
343
344 pci_write_config_dword(dev, where, reg);
345 }
346
347 static void __init
348 quirk_sbpci_bridge(struct pci_dev *dev)
349 {
350 if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
351 return;
352
353 printk("PCI: Fixing up bridge\n");
354
355 /* Enable PCI bridge bus mastering and memory space */
356 pci_set_master(dev);
357 pcibios_enable_resources(dev);
358
359 /* Enable PCI bridge BAR1 prefetch and burst */
360 pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
361 }
362
363 struct pci_fixup pcibios_fixups[] = {
364 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, quirk_sbpci_bridge },
365 { 0 }
366 };
367
368 /*
369 * If we set up a device for bus mastering, we need to check the latency
370 * timer as certain crappy BIOSes forget to set it properly.
371 */
372 unsigned int pcibios_max_latency = 255;
373
374 void pcibios_set_master(struct pci_dev *dev)
375 {
376 u8 lat;
377 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
378 if (lat < 16)
379 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
380 else if (lat > pcibios_max_latency)
381 lat = pcibios_max_latency;
382 else
383 return;
384 printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat);
385 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
386 }
387