target/linux/ath79/dts/ar724x.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2 #include <dt-bindings/clock/ath79-clk.h>
   3 #include "ath79.dtsi"
   4
   5 / {
   6         compatible = "qca,ar7240";
   7
   8         #address-cells = <1>;
   9         #size-cells = <1>;
  10
  11         chosen {
  12                 bootargs = "console=ttyS0,115200";
  13         };
  14
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         device_type = "cpu";
  21                         compatible = "mips,mips24Kc";
  22                         clocks = <&pll ATH79_CLK_CPU>;
  23                         reg = <0>;
  24                 };
  25         };
  26
  27         ahb: ahb {
  28                 apb {
  29                         ddr_ctrl: memory-controller@18000000 {
  30                                 compatible = "qca,ar9132-ddr-controller",
  31                                                 "qca,ar7240-ddr-controller";
  32                                 reg = <0x18000000 0x100>;
  33
  34                                 #qca,ddr-wb-channel-cells = <1>;
  35                         };
  36
  37                         uart: uart@18020000 {
  38                                 compatible = "ns16550a";
  39                                 reg = <0x18020000 0x20>;
  40                                 interrupts = <3>;
  41
  42                                 clocks = <&pll ATH79_CLK_AHB>;
  43                                 clock-names = "uart";
  44
  45                                 reg-io-width = <4>;
  46                                 reg-shift = <2>;
  47                                 no-loopback-test;
  48
  49                                 status = "disabled";
  50                         };
  51
  52                         gpio: gpio@18040000 {
  53                                 compatible = "qca,ar7240-gpio",
  54                                                 "qca,ar7100-gpio";
  55                                 reg = <0x18040000 0x30>;
  56                                 interrupts = <2>;
  57
  58                                 ngpios = <18>;
  59
  60                                 gpio-controller;
  61                                 #gpio-cells = <2>;
  62
  63                                 interrupt-controller;
  64                                 #interrupt-cells = <2>;
  65                         };
  66
  67                         pll: pll-controller@18050000 {
  68                                 compatible = "qca,ar7240-pll",
  69                                                 "qca,ar7240-pll";
  70                                 reg = <0x18050000 0x20>;
  71
  72                                 clock-names = "ref";
  73                                 /* The board must provides the ref clock */
  74
  75                                 #clock-cells = <1>;
  76                                 clock-output-names = "cpu", "ddr", "ahb";
  77                         };
  78
  79                         wdt: wdt@18060008 {
  80                                 compatible = "qca,ar7130-wdt";
  81                                 reg = <0x18060008 0x8>;
  82
  83                                 interrupts = <4>;
  84
  85                                 clocks = <&pll ATH79_CLK_AHB>;
  86                                 clock-names = "wdt";
  87                         };
  88
  89                         rst: reset-controller@1806001c {
  90                                 compatible = "qca,ar7240-reset",
  91                                                 "qca,ar7100-reset";
  92                                 reg = <0x1806001c 0x4>;
  93
  94                                 #reset-cells = <1>;
  95                         };
  96
  97                         pcie: pcie-controller@180c0000 {
  98                                 compatible = "qcom,ar7240-pci";
  99                                 #address-cells = <3>;
 100                                 #size-cells = <2>;
 101                                 bus-range = <0x0 0x0>;
 102                                 reg = <0x180c0000 0x1000>, /* CRP */
 103                                       <0x180f0000 0x100>,  /* CTRL */
 104                                       <0x14000000 0x1000>; /* CFG */
 105                                 reg-names = "crp_base", "ctrl_base", "cfg_base";
 106                                 ranges = <0x2000000 0 0x10000000 0x10000000 0 0x04000000        /* pci memory */
 107                                           0x1000000 0 0x00000000 0x0000000 0 0x000001>;         /* io space */
 108                                 interrupt-parent = <&cpuintc>;
 109                                 interrupts = <2>;
 110
 111                                 interrupt-controller;
 112                                 #interrupt-cells = <1>;
 113
 114                                 interrupt-map-mask = <0 0 0 1>;
 115                                 interrupt-map = <0 0 0 0 &pcie 0>;
 116                                 status = "disabled";
 117                         };
 118                 };
 119
 120                 spi: spi@1f000000 {
 121                         compatible = "qca,ar7240-spi",
 122                                         "qca,ar7100-spi";
 123                         reg = <0x1f000000 0x10>;
 124
 125                         clocks = <&pll ATH79_CLK_AHB>;
 126                         clock-names = "ahb";
 127
 128                         status = "disabled";
 129
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                 };
 133         };
 134 };
 135
 136 &cpuintc {
 137         qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;
 138         qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,
 139                                 <&ddr_ctrl 0>, <&ddr_ctrl 1>;
 140 };