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[openwrt/staging/lynxis/omap.git] / target / linux / ar71xx / files / arch / mips / ath79 / dev-eth.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2012 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22 #include <linux/clk.h>
23 #include <linux/sizes.h>
24
25 #include <asm/mach-ath79/ath79.h>
26 #include <asm/mach-ath79/ar71xx_regs.h>
27 #include <asm/mach-ath79/irq.h>
28
29 #include "common.h"
30 #include "dev-eth.h"
31
32 unsigned char ath79_mac_base[ETH_ALEN] __initdata;
33
34 static struct resource ath79_mdio0_resources[] = {
35 {
36 .name = "mdio_base",
37 .flags = IORESOURCE_MEM,
38 .start = AR71XX_GE0_BASE,
39 .end = AR71XX_GE0_BASE + 0x200 - 1,
40 }
41 };
42
43 struct ag71xx_mdio_platform_data ath79_mdio0_data;
44
45 struct platform_device ath79_mdio0_device = {
46 .name = "ag71xx-mdio",
47 .id = 0,
48 .resource = ath79_mdio0_resources,
49 .num_resources = ARRAY_SIZE(ath79_mdio0_resources),
50 .dev = {
51 .platform_data = &ath79_mdio0_data,
52 },
53 };
54
55 static struct resource ath79_mdio1_resources[] = {
56 {
57 .name = "mdio_base",
58 .flags = IORESOURCE_MEM,
59 .start = AR71XX_GE1_BASE,
60 .end = AR71XX_GE1_BASE + 0x200 - 1,
61 }
62 };
63
64 struct ag71xx_mdio_platform_data ath79_mdio1_data;
65
66 struct platform_device ath79_mdio1_device = {
67 .name = "ag71xx-mdio",
68 .id = 1,
69 .resource = ath79_mdio1_resources,
70 .num_resources = ARRAY_SIZE(ath79_mdio1_resources),
71 .dev = {
72 .platform_data = &ath79_mdio1_data,
73 },
74 };
75
76 static void ath79_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
77 {
78 void __iomem *base;
79 u32 t;
80
81 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
82
83 t = __raw_readl(base + cfg_reg);
84 t &= ~(3 << shift);
85 t |= (2 << shift);
86 __raw_writel(t, base + cfg_reg);
87 udelay(100);
88
89 __raw_writel(pll_val, base + pll_reg);
90
91 t |= (3 << shift);
92 __raw_writel(t, base + cfg_reg);
93 udelay(100);
94
95 t &= ~(3 << shift);
96 __raw_writel(t, base + cfg_reg);
97 udelay(100);
98
99 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
100 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
101
102 iounmap(base);
103 }
104
105 static void __init ath79_mii_ctrl_set_if(unsigned int reg,
106 unsigned int mii_if)
107 {
108 void __iomem *base;
109 u32 t;
110
111 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
112
113 t = __raw_readl(base + reg);
114 t &= ~(AR71XX_MII_CTRL_IF_MASK);
115 t |= (mii_if & AR71XX_MII_CTRL_IF_MASK);
116 __raw_writel(t, base + reg);
117
118 iounmap(base);
119 }
120
121 static void ath79_mii_ctrl_set_speed(unsigned int reg, unsigned int speed)
122 {
123 void __iomem *base;
124 unsigned int mii_speed;
125 u32 t;
126
127 switch (speed) {
128 case SPEED_10:
129 mii_speed = AR71XX_MII_CTRL_SPEED_10;
130 break;
131 case SPEED_100:
132 mii_speed = AR71XX_MII_CTRL_SPEED_100;
133 break;
134 case SPEED_1000:
135 mii_speed = AR71XX_MII_CTRL_SPEED_1000;
136 break;
137 default:
138 BUG();
139 }
140
141 base = ioremap(AR71XX_MII_BASE, AR71XX_MII_SIZE);
142
143 t = __raw_readl(base + reg);
144 t &= ~(AR71XX_MII_CTRL_SPEED_MASK << AR71XX_MII_CTRL_SPEED_SHIFT);
145 t |= mii_speed << AR71XX_MII_CTRL_SPEED_SHIFT;
146 __raw_writel(t, base + reg);
147
148 iounmap(base);
149 }
150
151 static unsigned long ar934x_get_mdio_ref_clock(void)
152 {
153 void __iomem *base;
154 unsigned long ret;
155 u32 t;
156
157 base = ioremap(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
158
159 ret = 0;
160 t = __raw_readl(base + AR934X_PLL_SWITCH_CLOCK_CONTROL_REG);
161 if (t & AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL) {
162 ret = 100 * 1000 * 1000;
163 } else {
164 struct clk *clk;
165
166 clk = clk_get(NULL, "ref");
167 if (!IS_ERR(clk))
168 ret = clk_get_rate(clk);
169 }
170
171 iounmap(base);
172
173 return ret;
174 }
175
176 void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
177 {
178 struct platform_device *mdio_dev;
179 struct ag71xx_mdio_platform_data *mdio_data;
180 unsigned int max_id;
181
182 if (ath79_soc == ATH79_SOC_AR9341 ||
183 ath79_soc == ATH79_SOC_AR9342 ||
184 ath79_soc == ATH79_SOC_AR9344 ||
185 ath79_soc == ATH79_SOC_QCA9556 ||
186 ath79_soc == ATH79_SOC_QCA9558 ||
187 ath79_soc == ATH79_SOC_QCA956X)
188 max_id = 1;
189 else
190 max_id = 0;
191
192 if (id > max_id) {
193 printk(KERN_ERR "ar71xx: invalid MDIO id %u\n", id);
194 return;
195 }
196
197 switch (ath79_soc) {
198 case ATH79_SOC_AR7241:
199 case ATH79_SOC_AR9330:
200 case ATH79_SOC_AR9331:
201 case ATH79_SOC_QCA9533:
202 case ATH79_SOC_TP9343:
203 mdio_dev = &ath79_mdio1_device;
204 mdio_data = &ath79_mdio1_data;
205 break;
206
207 case ATH79_SOC_AR9341:
208 case ATH79_SOC_AR9342:
209 case ATH79_SOC_AR9344:
210 case ATH79_SOC_QCA9556:
211 case ATH79_SOC_QCA9558:
212 case ATH79_SOC_QCA956X:
213 if (id == 0) {
214 mdio_dev = &ath79_mdio0_device;
215 mdio_data = &ath79_mdio0_data;
216 } else {
217 mdio_dev = &ath79_mdio1_device;
218 mdio_data = &ath79_mdio1_data;
219 }
220 break;
221
222 case ATH79_SOC_AR7242:
223 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
224 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
225 AR71XX_ETH0_PLL_SHIFT);
226 /* fall through */
227 default:
228 mdio_dev = &ath79_mdio0_device;
229 mdio_data = &ath79_mdio0_data;
230 break;
231 }
232
233 mdio_data->phy_mask = phy_mask;
234
235 switch (ath79_soc) {
236 case ATH79_SOC_AR7240:
237 mdio_data->is_ar7240 = 1;
238 /* fall through */
239 case ATH79_SOC_AR7241:
240 mdio_data->builtin_switch = 1;
241 break;
242
243 case ATH79_SOC_AR9330:
244 mdio_data->is_ar9330 = 1;
245 /* fall through */
246 case ATH79_SOC_AR9331:
247 mdio_data->builtin_switch = 1;
248 break;
249
250 case ATH79_SOC_AR9341:
251 case ATH79_SOC_AR9342:
252 case ATH79_SOC_AR9344:
253 if (id == 1) {
254 mdio_data->builtin_switch = 1;
255 mdio_data->ref_clock = ar934x_get_mdio_ref_clock();
256 mdio_data->mdio_clock = 6250000;
257 }
258 mdio_data->is_ar934x = 1;
259 break;
260
261 case ATH79_SOC_QCA9533:
262 case ATH79_SOC_TP9343:
263 mdio_data->builtin_switch = 1;
264 break;
265
266 case ATH79_SOC_QCA9556:
267 case ATH79_SOC_QCA9558:
268 mdio_data->is_ar934x = 1;
269 break;
270
271 case ATH79_SOC_QCA956X:
272 if (id == 1)
273 mdio_data->builtin_switch = 1;
274 mdio_data->is_ar934x = 1;
275 break;
276
277 default:
278 break;
279 }
280
281 platform_device_register(mdio_dev);
282 }
283
284 struct ath79_eth_pll_data ath79_eth0_pll_data;
285 struct ath79_eth_pll_data ath79_eth1_pll_data;
286
287 static u32 ath79_get_eth_pll(unsigned int mac, int speed)
288 {
289 struct ath79_eth_pll_data *pll_data;
290 u32 pll_val;
291
292 switch (mac) {
293 case 0:
294 pll_data = &ath79_eth0_pll_data;
295 break;
296 case 1:
297 pll_data = &ath79_eth1_pll_data;
298 break;
299 default:
300 BUG();
301 }
302
303 switch (speed) {
304 case SPEED_10:
305 pll_val = pll_data->pll_10;
306 break;
307 case SPEED_100:
308 pll_val = pll_data->pll_100;
309 break;
310 case SPEED_1000:
311 pll_val = pll_data->pll_1000;
312 break;
313 default:
314 BUG();
315 }
316
317 return pll_val;
318 }
319
320 static void ath79_set_speed_ge0(int speed)
321 {
322 u32 val = ath79_get_eth_pll(0, speed);
323
324 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
325 val, AR71XX_ETH0_PLL_SHIFT);
326 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
327 }
328
329 static void ath79_set_speed_ge1(int speed)
330 {
331 u32 val = ath79_get_eth_pll(1, speed);
332
333 ath79_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
334 val, AR71XX_ETH1_PLL_SHIFT);
335 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
336 }
337
338 static void ar7242_set_speed_ge0(int speed)
339 {
340 u32 val = ath79_get_eth_pll(0, speed);
341 void __iomem *base;
342
343 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
344 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
345 iounmap(base);
346 }
347
348 static void ar91xx_set_speed_ge0(int speed)
349 {
350 u32 val = ath79_get_eth_pll(0, speed);
351
352 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH0_INT_CLOCK,
353 val, AR913X_ETH0_PLL_SHIFT);
354 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII0_CTRL, speed);
355 }
356
357 static void ar91xx_set_speed_ge1(int speed)
358 {
359 u32 val = ath79_get_eth_pll(1, speed);
360
361 ath79_set_pll(AR913X_PLL_REG_ETH_CONFIG, AR913X_PLL_REG_ETH1_INT_CLOCK,
362 val, AR913X_ETH1_PLL_SHIFT);
363 ath79_mii_ctrl_set_speed(AR71XX_MII_REG_MII1_CTRL, speed);
364 }
365
366 static void ar934x_set_speed_ge0(int speed)
367 {
368 void __iomem *base;
369 u32 val = ath79_get_eth_pll(0, speed);
370
371 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
372 __raw_writel(val, base + AR934X_PLL_ETH_XMII_CONTROL_REG);
373 iounmap(base);
374 }
375
376 static void qca955x_set_speed_xmii(int speed)
377 {
378 void __iomem *base;
379 u32 val = ath79_get_eth_pll(0, speed);
380
381 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
382 __raw_writel(val, base + QCA955X_PLL_ETH_XMII_CONTROL_REG);
383 iounmap(base);
384 }
385
386 static void qca955x_set_speed_sgmii(int speed)
387 {
388 void __iomem *base;
389 u32 val = ath79_get_eth_pll(1, speed);
390
391 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
392 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
393 iounmap(base);
394 }
395
396 static void qca956x_set_speed_sgmii(int speed)
397 {
398 void __iomem *base;
399 u32 val = ath79_get_eth_pll(0, speed);
400
401 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
402 __raw_writel(val, base + QCA955X_PLL_ETH_SGMII_CONTROL_REG);
403 iounmap(base);
404 }
405
406 static void ath79_set_speed_dummy(int speed)
407 {
408 }
409
410 static void ath79_ddr_flush_ge0(void)
411 {
412 ath79_ddr_wb_flush(0);
413 }
414
415 static void ath79_ddr_flush_ge1(void)
416 {
417 ath79_ddr_wb_flush(1);
418 }
419
420 static struct resource ath79_eth0_resources[] = {
421 {
422 .name = "mac_base",
423 .flags = IORESOURCE_MEM,
424 .start = AR71XX_GE0_BASE,
425 .end = AR71XX_GE0_BASE + 0x200 - 1,
426 }, {
427 .name = "mac_irq",
428 .flags = IORESOURCE_IRQ,
429 .start = ATH79_CPU_IRQ(4),
430 .end = ATH79_CPU_IRQ(4),
431 },
432 };
433
434 struct ag71xx_platform_data ath79_eth0_data = {
435 .reset_bit = AR71XX_RESET_GE0_MAC,
436 };
437
438 struct platform_device ath79_eth0_device = {
439 .name = "ag71xx",
440 .id = 0,
441 .resource = ath79_eth0_resources,
442 .num_resources = ARRAY_SIZE(ath79_eth0_resources),
443 .dev = {
444 .platform_data = &ath79_eth0_data,
445 },
446 };
447
448 static struct resource ath79_eth1_resources[] = {
449 {
450 .name = "mac_base",
451 .flags = IORESOURCE_MEM,
452 .start = AR71XX_GE1_BASE,
453 .end = AR71XX_GE1_BASE + 0x200 - 1,
454 }, {
455 .name = "mac_irq",
456 .flags = IORESOURCE_IRQ,
457 .start = ATH79_CPU_IRQ(5),
458 .end = ATH79_CPU_IRQ(5),
459 },
460 };
461
462 struct ag71xx_platform_data ath79_eth1_data = {
463 .reset_bit = AR71XX_RESET_GE1_MAC,
464 };
465
466 struct platform_device ath79_eth1_device = {
467 .name = "ag71xx",
468 .id = 1,
469 .resource = ath79_eth1_resources,
470 .num_resources = ARRAY_SIZE(ath79_eth1_resources),
471 .dev = {
472 .platform_data = &ath79_eth1_data,
473 },
474 };
475
476 struct ag71xx_switch_platform_data ath79_switch_data;
477
478 #define AR71XX_PLL_VAL_1000 0x00110000
479 #define AR71XX_PLL_VAL_100 0x00001099
480 #define AR71XX_PLL_VAL_10 0x00991099
481
482 #define AR724X_PLL_VAL_1000 0x00110000
483 #define AR724X_PLL_VAL_100 0x00001099
484 #define AR724X_PLL_VAL_10 0x00991099
485
486 #define AR7242_PLL_VAL_1000 0x16000000
487 #define AR7242_PLL_VAL_100 0x00000101
488 #define AR7242_PLL_VAL_10 0x00001616
489
490 #define AR913X_PLL_VAL_1000 0x1a000000
491 #define AR913X_PLL_VAL_100 0x13000a44
492 #define AR913X_PLL_VAL_10 0x00441099
493
494 #define AR933X_PLL_VAL_1000 0x00110000
495 #define AR933X_PLL_VAL_100 0x00001099
496 #define AR933X_PLL_VAL_10 0x00991099
497
498 #define AR934X_PLL_VAL_1000 0x16000000
499 #define AR934X_PLL_VAL_100 0x00000101
500 #define AR934X_PLL_VAL_10 0x00001616
501
502 #define QCA956X_PLL_VAL_1000 0x03000000
503 #define QCA956X_PLL_VAL_100 0x00000101
504 #define QCA956X_PLL_VAL_10 0x00001919
505
506 static void __init ath79_init_eth_pll_data(unsigned int id)
507 {
508 struct ath79_eth_pll_data *pll_data;
509 u32 pll_10, pll_100, pll_1000;
510
511 switch (id) {
512 case 0:
513 pll_data = &ath79_eth0_pll_data;
514 break;
515 case 1:
516 pll_data = &ath79_eth1_pll_data;
517 break;
518 default:
519 BUG();
520 }
521
522 switch (ath79_soc) {
523 case ATH79_SOC_AR7130:
524 case ATH79_SOC_AR7141:
525 case ATH79_SOC_AR7161:
526 pll_10 = AR71XX_PLL_VAL_10;
527 pll_100 = AR71XX_PLL_VAL_100;
528 pll_1000 = AR71XX_PLL_VAL_1000;
529 break;
530
531 case ATH79_SOC_AR7240:
532 case ATH79_SOC_AR7241:
533 pll_10 = AR724X_PLL_VAL_10;
534 pll_100 = AR724X_PLL_VAL_100;
535 pll_1000 = AR724X_PLL_VAL_1000;
536 break;
537
538 case ATH79_SOC_AR7242:
539 pll_10 = AR7242_PLL_VAL_10;
540 pll_100 = AR7242_PLL_VAL_100;
541 pll_1000 = AR7242_PLL_VAL_1000;
542 break;
543
544 case ATH79_SOC_AR9130:
545 case ATH79_SOC_AR9132:
546 pll_10 = AR913X_PLL_VAL_10;
547 pll_100 = AR913X_PLL_VAL_100;
548 pll_1000 = AR913X_PLL_VAL_1000;
549 break;
550
551 case ATH79_SOC_AR9330:
552 case ATH79_SOC_AR9331:
553 pll_10 = AR933X_PLL_VAL_10;
554 pll_100 = AR933X_PLL_VAL_100;
555 pll_1000 = AR933X_PLL_VAL_1000;
556 break;
557
558 case ATH79_SOC_AR9341:
559 case ATH79_SOC_AR9342:
560 case ATH79_SOC_AR9344:
561 case ATH79_SOC_QCA9533:
562 case ATH79_SOC_QCA9556:
563 case ATH79_SOC_QCA9558:
564 case ATH79_SOC_TP9343:
565 pll_10 = AR934X_PLL_VAL_10;
566 pll_100 = AR934X_PLL_VAL_100;
567 pll_1000 = AR934X_PLL_VAL_1000;
568 break;
569
570 case ATH79_SOC_QCA956X:
571 pll_10 = QCA956X_PLL_VAL_10;
572 pll_100 = QCA956X_PLL_VAL_100;
573 pll_1000 = QCA956X_PLL_VAL_1000;
574 break;
575
576 default:
577 BUG();
578 }
579
580 if (!pll_data->pll_10)
581 pll_data->pll_10 = pll_10;
582
583 if (!pll_data->pll_100)
584 pll_data->pll_100 = pll_100;
585
586 if (!pll_data->pll_1000)
587 pll_data->pll_1000 = pll_1000;
588 }
589
590 static int __init ath79_setup_phy_if_mode(unsigned int id,
591 struct ag71xx_platform_data *pdata)
592 {
593 unsigned int mii_if;
594
595 switch (id) {
596 case 0:
597 switch (ath79_soc) {
598 case ATH79_SOC_AR7130:
599 case ATH79_SOC_AR7141:
600 case ATH79_SOC_AR7161:
601 case ATH79_SOC_AR9130:
602 case ATH79_SOC_AR9132:
603 switch (pdata->phy_if_mode) {
604 case PHY_INTERFACE_MODE_MII:
605 mii_if = AR71XX_MII0_CTRL_IF_MII;
606 break;
607 case PHY_INTERFACE_MODE_GMII:
608 mii_if = AR71XX_MII0_CTRL_IF_GMII;
609 break;
610 case PHY_INTERFACE_MODE_RGMII:
611 mii_if = AR71XX_MII0_CTRL_IF_RGMII;
612 break;
613 case PHY_INTERFACE_MODE_RMII:
614 mii_if = AR71XX_MII0_CTRL_IF_RMII;
615 break;
616 default:
617 return -EINVAL;
618 }
619 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII0_CTRL, mii_if);
620 break;
621
622 case ATH79_SOC_AR7240:
623 case ATH79_SOC_AR7241:
624 case ATH79_SOC_AR9330:
625 case ATH79_SOC_AR9331:
626 case ATH79_SOC_QCA9533:
627 case ATH79_SOC_TP9343:
628 pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
629 break;
630
631 case ATH79_SOC_AR7242:
632 /* FIXME */
633
634 case ATH79_SOC_AR9341:
635 case ATH79_SOC_AR9342:
636 case ATH79_SOC_AR9344:
637 switch (pdata->phy_if_mode) {
638 case PHY_INTERFACE_MODE_MII:
639 case PHY_INTERFACE_MODE_GMII:
640 case PHY_INTERFACE_MODE_RGMII:
641 case PHY_INTERFACE_MODE_RMII:
642 break;
643 default:
644 return -EINVAL;
645 }
646 break;
647
648 case ATH79_SOC_QCA9556:
649 case ATH79_SOC_QCA9558:
650 case ATH79_SOC_QCA956X:
651 switch (pdata->phy_if_mode) {
652 case PHY_INTERFACE_MODE_MII:
653 case PHY_INTERFACE_MODE_RGMII:
654 case PHY_INTERFACE_MODE_SGMII:
655 break;
656 default:
657 return -EINVAL;
658 }
659 break;
660
661 default:
662 BUG();
663 }
664 break;
665 case 1:
666 switch (ath79_soc) {
667 case ATH79_SOC_AR7130:
668 case ATH79_SOC_AR7141:
669 case ATH79_SOC_AR7161:
670 case ATH79_SOC_AR9130:
671 case ATH79_SOC_AR9132:
672 switch (pdata->phy_if_mode) {
673 case PHY_INTERFACE_MODE_RMII:
674 mii_if = AR71XX_MII1_CTRL_IF_RMII;
675 break;
676 case PHY_INTERFACE_MODE_RGMII:
677 mii_if = AR71XX_MII1_CTRL_IF_RGMII;
678 break;
679 default:
680 return -EINVAL;
681 }
682 ath79_mii_ctrl_set_if(AR71XX_MII_REG_MII1_CTRL, mii_if);
683 break;
684
685 case ATH79_SOC_AR7240:
686 case ATH79_SOC_AR7241:
687 case ATH79_SOC_AR9330:
688 case ATH79_SOC_AR9331:
689 case ATH79_SOC_QCA956X:
690 case ATH79_SOC_TP9343:
691 pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
692 break;
693
694 case ATH79_SOC_AR7242:
695 /* FIXME */
696
697 case ATH79_SOC_AR9341:
698 case ATH79_SOC_AR9342:
699 case ATH79_SOC_AR9344:
700 case ATH79_SOC_QCA9533:
701 switch (pdata->phy_if_mode) {
702 case PHY_INTERFACE_MODE_MII:
703 case PHY_INTERFACE_MODE_GMII:
704 break;
705 default:
706 return -EINVAL;
707 }
708 break;
709
710 case ATH79_SOC_QCA9556:
711 case ATH79_SOC_QCA9558:
712 switch (pdata->phy_if_mode) {
713 case PHY_INTERFACE_MODE_MII:
714 case PHY_INTERFACE_MODE_RGMII:
715 case PHY_INTERFACE_MODE_SGMII:
716 break;
717 default:
718 return -EINVAL;
719 }
720 break;
721
722 default:
723 BUG();
724 }
725 break;
726 }
727
728 return 0;
729 }
730
731 void __init ath79_setup_ar933x_phy4_switch(bool mac, bool mdio)
732 {
733 void __iomem *base;
734 u32 t;
735
736 base = ioremap(AR933X_GMAC_BASE, AR933X_GMAC_SIZE);
737
738 t = __raw_readl(base + AR933X_GMAC_REG_ETH_CFG);
739 t &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
740 if (mac)
741 t |= AR933X_ETH_CFG_SW_PHY_SWAP;
742 if (mdio)
743 t |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
744 __raw_writel(t, base + AR933X_GMAC_REG_ETH_CFG);
745
746 iounmap(base);
747 }
748
749 void __init ath79_setup_ar934x_eth_cfg(u32 mask)
750 {
751 void __iomem *base;
752 u32 t;
753
754 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
755
756 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
757
758 t &= ~(AR934X_ETH_CFG_RGMII_GMAC0 |
759 AR934X_ETH_CFG_MII_GMAC0 |
760 AR934X_ETH_CFG_GMII_GMAC0 |
761 AR934X_ETH_CFG_SW_ONLY_MODE |
762 AR934X_ETH_CFG_SW_PHY_SWAP);
763
764 t |= mask;
765
766 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
767 /* flush write */
768 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
769
770 iounmap(base);
771 }
772
773 void __init ath79_setup_ar934x_eth_rx_delay(unsigned int rxd,
774 unsigned int rxdv)
775 {
776 void __iomem *base;
777 u32 t;
778
779 rxd &= AR934X_ETH_CFG_RXD_DELAY_MASK;
780 rxdv &= AR934X_ETH_CFG_RDV_DELAY_MASK;
781
782 base = ioremap(AR934X_GMAC_BASE, AR934X_GMAC_SIZE);
783
784 t = __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
785
786 t &= ~(AR934X_ETH_CFG_RXD_DELAY_MASK << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
787 AR934X_ETH_CFG_RDV_DELAY_MASK << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
788
789 t |= (rxd << AR934X_ETH_CFG_RXD_DELAY_SHIFT |
790 rxdv << AR934X_ETH_CFG_RDV_DELAY_SHIFT);
791
792 __raw_writel(t, base + AR934X_GMAC_REG_ETH_CFG);
793 /* flush write */
794 __raw_readl(base + AR934X_GMAC_REG_ETH_CFG);
795
796 iounmap(base);
797 }
798
799 void __init ath79_setup_qca955x_eth_cfg(u32 mask)
800 {
801 void __iomem *base;
802 u32 t;
803
804 base = ioremap(QCA955X_GMAC_BASE, QCA955X_GMAC_SIZE);
805
806 t = __raw_readl(base + QCA955X_GMAC_REG_ETH_CFG);
807
808 t &= ~(QCA955X_ETH_CFG_RGMII_EN | QCA955X_ETH_CFG_GE0_SGMII);
809
810 t |= mask;
811
812 __raw_writel(t, base + QCA955X_GMAC_REG_ETH_CFG);
813
814 iounmap(base);
815 }
816
817 static int ath79_eth_instance __initdata;
818 void __init ath79_register_eth(unsigned int id)
819 {
820 struct platform_device *pdev;
821 struct ag71xx_platform_data *pdata;
822 int err;
823
824 if (id > 1) {
825 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
826 return;
827 }
828
829 ath79_init_eth_pll_data(id);
830
831 if (id == 0)
832 pdev = &ath79_eth0_device;
833 else
834 pdev = &ath79_eth1_device;
835
836 pdata = pdev->dev.platform_data;
837
838 pdata->max_frame_len = 1540;
839 pdata->desc_pktlen_mask = 0xfff;
840
841 err = ath79_setup_phy_if_mode(id, pdata);
842 if (err) {
843 printk(KERN_ERR
844 "ar71xx: invalid PHY interface mode for GE%u\n", id);
845 return;
846 }
847
848 if (id == 0)
849 pdata->ddr_flush = ath79_ddr_flush_ge0;
850 else
851 pdata->ddr_flush = ath79_ddr_flush_ge1;
852
853 switch (ath79_soc) {
854 case ATH79_SOC_AR7130:
855 if (id == 0)
856 pdata->set_speed = ath79_set_speed_ge0;
857 else
858 pdata->set_speed = ath79_set_speed_ge1;
859 break;
860
861 case ATH79_SOC_AR7141:
862 case ATH79_SOC_AR7161:
863 if (id == 0)
864 pdata->set_speed = ath79_set_speed_ge0;
865 else
866 pdata->set_speed = ath79_set_speed_ge1;
867 pdata->has_gbit = 1;
868 break;
869
870 case ATH79_SOC_AR7242:
871 if (id == 0) {
872 pdata->reset_bit |= AR724X_RESET_GE0_MDIO |
873 AR71XX_RESET_GE0_PHY;
874 pdata->set_speed = ar7242_set_speed_ge0;
875 } else {
876 pdata->reset_bit |= AR724X_RESET_GE1_MDIO |
877 AR71XX_RESET_GE1_PHY;
878 pdata->set_speed = ath79_set_speed_dummy;
879 }
880 pdata->has_gbit = 1;
881 pdata->is_ar724x = 1;
882
883 if (!pdata->fifo_cfg1)
884 pdata->fifo_cfg1 = 0x0010ffff;
885 if (!pdata->fifo_cfg2)
886 pdata->fifo_cfg2 = 0x015500aa;
887 if (!pdata->fifo_cfg3)
888 pdata->fifo_cfg3 = 0x01f00140;
889 break;
890
891 case ATH79_SOC_AR7241:
892 if (id == 0)
893 pdata->reset_bit |= AR724X_RESET_GE0_MDIO;
894 else
895 pdata->reset_bit |= AR724X_RESET_GE1_MDIO;
896 /* fall through */
897 case ATH79_SOC_AR7240:
898 if (id == 0) {
899 pdata->reset_bit |= AR71XX_RESET_GE0_PHY;
900 pdata->set_speed = ath79_set_speed_dummy;
901
902 pdata->phy_mask = BIT(4);
903 } else {
904 pdata->reset_bit |= AR71XX_RESET_GE1_PHY;
905 pdata->set_speed = ath79_set_speed_dummy;
906
907 pdata->speed = SPEED_1000;
908 pdata->duplex = DUPLEX_FULL;
909 pdata->switch_data = &ath79_switch_data;
910 pdata->builtin_switch = 1;
911
912 ath79_switch_data.phy_poll_mask |= BIT(4);
913 }
914 pdata->has_gbit = 1;
915 pdata->is_ar724x = 1;
916 if (ath79_soc == ATH79_SOC_AR7240)
917 pdata->is_ar7240 = 1;
918
919 if (!pdata->fifo_cfg1)
920 pdata->fifo_cfg1 = 0x0010ffff;
921 if (!pdata->fifo_cfg2)
922 pdata->fifo_cfg2 = 0x015500aa;
923 if (!pdata->fifo_cfg3)
924 pdata->fifo_cfg3 = 0x01f00140;
925 break;
926
927 case ATH79_SOC_AR9132:
928 pdata->has_gbit = 1;
929 /* fall through */
930 case ATH79_SOC_AR9130:
931 if (id == 0)
932 pdata->set_speed = ar91xx_set_speed_ge0;
933 else
934 pdata->set_speed = ar91xx_set_speed_ge1;
935 pdata->is_ar91xx = 1;
936 break;
937
938 case ATH79_SOC_AR9330:
939 case ATH79_SOC_AR9331:
940 if (id == 0) {
941 pdata->reset_bit = AR933X_RESET_GE0_MAC |
942 AR933X_RESET_GE0_MDIO;
943 pdata->set_speed = ath79_set_speed_dummy;
944
945 pdata->phy_mask = BIT(4);
946 } else {
947 pdata->reset_bit = AR933X_RESET_GE1_MAC |
948 AR933X_RESET_GE1_MDIO;
949 pdata->set_speed = ath79_set_speed_dummy;
950
951 pdata->speed = SPEED_1000;
952 pdata->has_gbit = 1;
953 pdata->duplex = DUPLEX_FULL;
954 pdata->switch_data = &ath79_switch_data;
955 pdata->builtin_switch = 1;
956
957 ath79_switch_data.phy_poll_mask |= BIT(4);
958 }
959
960 pdata->is_ar724x = 1;
961
962 if (!pdata->fifo_cfg1)
963 pdata->fifo_cfg1 = 0x0010ffff;
964 if (!pdata->fifo_cfg2)
965 pdata->fifo_cfg2 = 0x015500aa;
966 if (!pdata->fifo_cfg3)
967 pdata->fifo_cfg3 = 0x01f00140;
968 break;
969
970 case ATH79_SOC_AR9341:
971 case ATH79_SOC_AR9342:
972 case ATH79_SOC_AR9344:
973 case ATH79_SOC_QCA9533:
974 if (id == 0) {
975 pdata->reset_bit = AR934X_RESET_GE0_MAC |
976 AR934X_RESET_GE0_MDIO;
977 pdata->set_speed = ar934x_set_speed_ge0;
978 } else {
979 pdata->reset_bit = AR934X_RESET_GE1_MAC |
980 AR934X_RESET_GE1_MDIO;
981 pdata->set_speed = ath79_set_speed_dummy;
982
983 pdata->switch_data = &ath79_switch_data;
984 pdata->builtin_switch = 1;
985
986 /* reset the built-in switch */
987 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
988 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
989 }
990
991 pdata->has_gbit = 1;
992 pdata->is_ar724x = 1;
993
994 pdata->max_frame_len = SZ_16K - 1;
995 pdata->desc_pktlen_mask = SZ_16K - 1;
996
997 if (!pdata->fifo_cfg1)
998 pdata->fifo_cfg1 = 0x0010ffff;
999 if (!pdata->fifo_cfg2)
1000 pdata->fifo_cfg2 = 0x015500aa;
1001 if (!pdata->fifo_cfg3)
1002 pdata->fifo_cfg3 = 0x01f00140;
1003 break;
1004
1005 case ATH79_SOC_TP9343:
1006 if (id == 0) {
1007 pdata->reset_bit = AR933X_RESET_GE0_MAC |
1008 AR933X_RESET_GE0_MDIO;
1009 pdata->set_speed = ath79_set_speed_dummy;
1010
1011 if (!pdata->phy_mask)
1012 pdata->phy_mask = BIT(4);
1013 } else {
1014 pdata->reset_bit = AR933X_RESET_GE1_MAC |
1015 AR933X_RESET_GE1_MDIO;
1016 pdata->set_speed = ath79_set_speed_dummy;
1017
1018 pdata->speed = SPEED_1000;
1019 pdata->duplex = DUPLEX_FULL;
1020 pdata->switch_data = &ath79_switch_data;
1021 pdata->builtin_switch = 1;
1022
1023 ath79_switch_data.phy_poll_mask |= BIT(4);
1024 }
1025
1026 pdata->has_gbit = 1;
1027 pdata->is_ar724x = 1;
1028
1029 if (!pdata->fifo_cfg1)
1030 pdata->fifo_cfg1 = 0x0010ffff;
1031 if (!pdata->fifo_cfg2)
1032 pdata->fifo_cfg2 = 0x015500aa;
1033 if (!pdata->fifo_cfg3)
1034 pdata->fifo_cfg3 = 0x01f00140;
1035 break;
1036
1037 case ATH79_SOC_QCA9556:
1038 case ATH79_SOC_QCA9558:
1039 if (id == 0) {
1040 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1041 QCA955X_RESET_GE0_MDIO;
1042 pdata->set_speed = qca955x_set_speed_xmii;
1043 } else {
1044 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1045 QCA955X_RESET_GE1_MDIO;
1046 pdata->set_speed = qca955x_set_speed_sgmii;
1047 pdata->builtin_switch = 1;
1048 }
1049
1050 pdata->has_gbit = 1;
1051 pdata->is_ar724x = 1;
1052
1053 /*
1054 * Limit the maximum frame length to 4095 bytes.
1055 * Although the documentation says that the hardware
1056 * limit is 16383 bytes but that does not work in
1057 * practice. It seems that the hardware only updates
1058 * the lowest 12 bits of the packet length field
1059 * in the RX descriptor.
1060 */
1061 pdata->max_frame_len = SZ_4K - 1;
1062 pdata->desc_pktlen_mask = SZ_16K - 1;
1063
1064 if (!pdata->fifo_cfg1)
1065 pdata->fifo_cfg1 = 0x0010ffff;
1066 if (!pdata->fifo_cfg2)
1067 pdata->fifo_cfg2 = 0x015500aa;
1068 if (!pdata->fifo_cfg3)
1069 pdata->fifo_cfg3 = 0x01f00140;
1070 break;
1071
1072 case ATH79_SOC_QCA956X:
1073 if (id == 0) {
1074 pdata->reset_bit = QCA955X_RESET_GE0_MAC |
1075 QCA955X_RESET_GE0_MDIO;
1076
1077 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_SGMII)
1078 pdata->set_speed = qca956x_set_speed_sgmii;
1079 else
1080 pdata->set_speed = ath79_set_speed_ge0;
1081 } else {
1082 pdata->reset_bit = QCA955X_RESET_GE1_MAC |
1083 QCA955X_RESET_GE1_MDIO;
1084
1085 pdata->set_speed = ath79_set_speed_dummy;
1086
1087 pdata->switch_data = &ath79_switch_data;
1088
1089 pdata->speed = SPEED_1000;
1090 pdata->duplex = DUPLEX_FULL;
1091 pdata->builtin_switch = 1;
1092
1093 /* reset the built-in switch */
1094 ath79_device_reset_set(AR934X_RESET_ETH_SWITCH);
1095 ath79_device_reset_clear(AR934X_RESET_ETH_SWITCH);
1096 }
1097
1098 pdata->has_gbit = 1;
1099 pdata->is_ar724x = 1;
1100
1101 if (!pdata->fifo_cfg1)
1102 pdata->fifo_cfg1 = 0x0010ffff;
1103 if (!pdata->fifo_cfg2)
1104 pdata->fifo_cfg2 = 0x015500aa;
1105 if (!pdata->fifo_cfg3)
1106 pdata->fifo_cfg3 = 0x01f00140;
1107 break;
1108
1109 default:
1110 BUG();
1111 }
1112
1113 switch (pdata->phy_if_mode) {
1114 case PHY_INTERFACE_MODE_GMII:
1115 case PHY_INTERFACE_MODE_RGMII:
1116 case PHY_INTERFACE_MODE_SGMII:
1117 if (!pdata->has_gbit) {
1118 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
1119 id);
1120 return;
1121 }
1122 /* fallthrough */
1123 default:
1124 break;
1125 }
1126
1127 if (!is_valid_ether_addr(pdata->mac_addr)) {
1128 random_ether_addr(pdata->mac_addr);
1129 printk(KERN_DEBUG
1130 "ar71xx: using random MAC address for eth%d\n",
1131 ath79_eth_instance);
1132 }
1133
1134 if (pdata->mii_bus_dev == NULL) {
1135 switch (ath79_soc) {
1136 case ATH79_SOC_AR9341:
1137 case ATH79_SOC_AR9342:
1138 case ATH79_SOC_AR9344:
1139 if (id == 0)
1140 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1141 else
1142 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1143 break;
1144
1145 case ATH79_SOC_AR7241:
1146 case ATH79_SOC_AR9330:
1147 case ATH79_SOC_AR9331:
1148 case ATH79_SOC_QCA9533:
1149 case ATH79_SOC_TP9343:
1150 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1151 break;
1152
1153 case ATH79_SOC_QCA9556:
1154 case ATH79_SOC_QCA9558:
1155 /* don't assign any MDIO device by default */
1156 break;
1157
1158 case ATH79_SOC_QCA956X:
1159 if (pdata->phy_if_mode != PHY_INTERFACE_MODE_SGMII)
1160 pdata->mii_bus_dev = &ath79_mdio1_device.dev;
1161 break;
1162
1163 default:
1164 pdata->mii_bus_dev = &ath79_mdio0_device.dev;
1165 break;
1166 }
1167 }
1168
1169 /* Reset the device */
1170 ath79_device_reset_set(pdata->reset_bit);
1171 msleep(100);
1172
1173 ath79_device_reset_clear(pdata->reset_bit);
1174 msleep(100);
1175
1176 platform_device_register(pdev);
1177 ath79_eth_instance++;
1178 }
1179
1180 void __init ath79_set_mac_base(unsigned char *mac)
1181 {
1182 memcpy(ath79_mac_base, mac, ETH_ALEN);
1183 }
1184
1185 void __init ath79_parse_ascii_mac(char *mac_str, u8 *mac)
1186 {
1187 int t;
1188
1189 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
1190 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1191
1192 if (t != ETH_ALEN)
1193 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
1194 &mac[0], &mac[1], &mac[2], &mac[3], &mac[4], &mac[5]);
1195
1196 if (t != ETH_ALEN || !is_valid_ether_addr(mac)) {
1197 memset(mac, 0, ETH_ALEN);
1198 printk(KERN_DEBUG "ar71xx: invalid mac address \"%s\"\n",
1199 mac_str);
1200 }
1201 }
1202
1203 static void __init ath79_set_mac_base_ascii(char *str)
1204 {
1205 u8 mac[ETH_ALEN];
1206
1207 ath79_parse_ascii_mac(str, mac);
1208 ath79_set_mac_base(mac);
1209 }
1210
1211 static int __init ath79_ethaddr_setup(char *str)
1212 {
1213 ath79_set_mac_base_ascii(str);
1214 return 1;
1215 }
1216 __setup("ethaddr=", ath79_ethaddr_setup);
1217
1218 static int __init ath79_kmac_setup(char *str)
1219 {
1220 ath79_set_mac_base_ascii(str);
1221 return 1;
1222 }
1223 __setup("kmac=", ath79_kmac_setup);
1224
1225 void __init ath79_init_mac(unsigned char *dst, const unsigned char *src,
1226 int offset)
1227 {
1228 int t;
1229
1230 if (!dst)
1231 return;
1232
1233 if (!src || !is_valid_ether_addr(src)) {
1234 memset(dst, '\0', ETH_ALEN);
1235 return;
1236 }
1237
1238 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
1239 t += offset;
1240
1241 dst[0] = src[0];
1242 dst[1] = src[1];
1243 dst[2] = src[2];
1244 dst[3] = (t >> 16) & 0xff;
1245 dst[4] = (t >> 8) & 0xff;
1246 dst[5] = t & 0xff;
1247 }
1248
1249 void __init ath79_init_local_mac(unsigned char *dst, const unsigned char *src)
1250 {
1251 int i;
1252
1253 if (!dst)
1254 return;
1255
1256 if (!src || !is_valid_ether_addr(src)) {
1257 memset(dst, '\0', ETH_ALEN);
1258 return;
1259 }
1260
1261 for (i = 0; i < ETH_ALEN; i++)
1262 dst[i] = src[i];
1263 dst[0] |= 0x02;
1264 }
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