ipq806x: add initial support for Netgear R7800
[openwrt/staging/lynxis/omap.git] / target / linux / ipq806x / files / arch / arm / boot / dts / qcom-ipq8065.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/soc/qcom,gsbi.h>
7 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/gpio/gpio.h>
10
11 / {
12 model = "Qualcomm IPQ8065";
13 compatible = "qcom,ipq8065";
14 interrupt-parent = <&intc>;
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "qcom,krait";
22 enable-method = "qcom,kpss-acc-v1";
23 device_type = "cpu";
24 reg = <0>;
25 next-level-cache = <&L2>;
26 qcom,acc = <&acc0>;
27 qcom,saw = <&saw0>;
28 clocks = <&kraitcc 0>;
29 clock-names = "cpu";
30 clock-latency = <100000>;
31 core-supply = <&smb208_s2a>;
32 voltage-tolerance = <5>;
33 cooling-min-state = <0>;
34 cooling-max-state = <10>;
35 #cooling-cells = <2>;
36
37 operating-points-0-0 = <
38 /* kHz uV */
39 1725000 1262500
40 1400000 1175000
41 1000000 1100000
42 800000 1050000
43 600000 1000000
44 384000 975000
45 >;
46 operating-points-0-1 = <
47 /* kHz uV */
48 1725000 1262500
49 1400000 1175000
50 1000000 1100000
51 800000 1050000
52 600000 1000000
53 384000 950000
54 >;
55 operating-points-0-2 = <
56 /* kHz uV */
57 1725000 1200000
58 1400000 1125000
59 1000000 1050000
60 800000 1000000
61 600000 950000
62 384000 925000
63 >;
64 operating-points-0-3 = <
65 /* kHz uV */
66 1725000 1175000
67 1400000 1100000
68 1000000 1025000
69 800000 975000
70 600000 925000
71 384000 900000
72 >;
73 operating-points-0-4 = <
74 /* kHz uV */
75 1725000 1150000
76 1400000 1075000
77 1000000 1000000
78 800000 950000
79 600000 900000
80 384000 875000
81 >;
82 operating-points-0-5 = <
83 /* kHz uV */
84 1725000 1100000
85 1400000 1025000
86 1000000 950000
87 800000 900000
88 600000 850000
89 384000 825000
90 >;
91 operating-points-0-6 = <
92 /* kHz uV */
93 1725000 1050000
94 1400000 975000
95 1000000 900000
96 800000 850000
97 600000 800000
98 384000 775000
99 >;
100 };
101
102 cpu@1 {
103 compatible = "qcom,krait";
104 enable-method = "qcom,kpss-acc-v1";
105 device_type = "cpu";
106 reg = <1>;
107 next-level-cache = <&L2>;
108 qcom,acc = <&acc1>;
109 qcom,saw = <&saw1>;
110 clocks = <&kraitcc 1>;
111 clock-names = "cpu";
112 clock-latency = <100000>;
113 core-supply = <&smb208_s2b>;
114
115 operating-points-0-0 = <
116 /* kHz uV */
117 1725000 1262500
118 1400000 1175000
119 1000000 1100000
120 800000 1050000
121 600000 1000000
122 384000 975000
123 >;
124 operating-points-0-1 = <
125 /* kHz uV */
126 1725000 1262500
127 1400000 1175000
128 1000000 1100000
129 800000 1050000
130 600000 1000000
131 384000 950000
132 >;
133 operating-points-0-2 = <
134 /* kHz uV */
135 1725000 1200000
136 1400000 1125000
137 1000000 1050000
138 800000 1000000
139 600000 950000
140 384000 925000
141 >;
142 operating-points-0-3 = <
143 /* kHz uV */
144 1725000 1175000
145 1400000 1100000
146 1000000 1025000
147 800000 975000
148 600000 925000
149 384000 900000
150 >;
151 operating-points-0-4 = <
152 /* kHz uV */
153 1725000 1150000
154 1400000 1075000
155 1000000 1000000
156 800000 950000
157 600000 900000
158 384000 875000
159 >;
160 operating-points-0-5 = <
161 /* kHz uV */
162 1725000 1100000
163 1400000 1025000
164 1000000 950000
165 800000 900000
166 600000 850000
167 384000 825000
168 >;
169 operating-points-0-6 = <
170 /* kHz uV */
171 1725000 1050000
172 1400000 975000
173 1000000 900000
174 800000 850000
175 600000 800000
176 384000 775000
177 >;
178 cooling-min-state = <0>;
179 cooling-max-state = <10>;
180 #cooling-cells = <2>;
181 };
182
183 L2: l2-cache {
184 compatible = "cache";
185 cache-level = <2>;
186 clocks = <&kraitcc 4>;
187 clock-names = "cache";
188 cache-points-kHz = <
189 /* kHz uV CPU kHz */
190 1200000 1150000 1200000
191 1000000 1100000 600000
192 384000 1100000 384000
193 >;
194 vdd_dig-supply = <&smb208_s1a>;
195 };
196 };
197
198 cpu-pmu {
199 compatible = "qcom,krait-pmu";
200 interrupts = <1 10 0x304>;
201 };
202
203 reserved-memory {
204 #address-cells = <1>;
205 #size-cells = <1>;
206 ranges;
207
208 nss@40000000 {
209 reg = <0x40000000 0x1000000>;
210 no-map;
211 };
212
213 smem: smem@41000000 {
214 reg = <0x41000000 0x200000>;
215 no-map;
216 };
217 };
218
219 clocks {
220 sleep_clk: sleep_clk {
221 compatible = "fixed-clock";
222 clock-frequency = <32768>;
223 #clock-cells = <0>;
224 };
225 };
226
227 kraitcc: clock-controller {
228 compatible = "qcom,krait-cc-v1";
229 #clock-cells = <1>;
230 };
231
232 qcom,pvs {
233 qcom,pvs-format-a;
234 qcom,speed0-pvs0-bin-v0 =
235 < 1725000000 1262500 >,
236 < 1400000000 1175000 >,
237 < 1000000000 1100000 >,
238 < 800000000 1050000 >,
239 < 600000000 1000000 >,
240 < 384000000 975000 >;
241 qcom,speed0-pvs1-bin-v0 =
242 < 1725000000 1262500 >,
243 < 1400000000 1175000 >,
244 < 1000000000 1100000 >,
245 < 800000000 1050000 >,
246 < 600000000 1000000 >,
247 < 384000000 950000 >;
248 qcom,speed0-pvs2-bin-v0 =
249 < 1725000000 1200000 >,
250 < 1400000000 1125000 >,
251 < 1000000000 1050000 >,
252 < 800000000 1000000 >,
253 < 600000000 950000 >,
254 < 384000000 925000 >;
255 qcom,speed0-pvs3-bin-v0 =
256 < 1725000000 1175000 >,
257 < 1400000000 1100000 >,
258 < 1000000000 1025000 >,
259 < 800000000 975000 >,
260 < 600000000 925000 >,
261 < 384000000 900000 >;
262 qcom,speed0-pvs4-bin-v0 =
263 < 1725000000 1150000 >,
264 < 1400000000 1075000 >,
265 < 1000000000 1000000 >,
266 < 800000000 950000 >,
267 < 600000000 900000 >,
268 < 384000000 875000 >;
269 qcom,speed0-pvs5-bin-v0 =
270 < 1725000000 1100000 >,
271 < 1400000000 1025000 >,
272 < 1000000000 950000 >,
273 < 800000000 900000 >,
274 < 600000000 850000 >,
275 < 384000000 825000 >;
276 qcom,speed0-pvs6-bin-v0 =
277 < 1725000000 1050000 >,
278 < 1400000000 975000 >,
279 < 1000000000 900000 >,
280 < 800000000 850000 >,
281 < 600000000 800000 >,
282 < 384000000 775000 >;
283 };
284
285 soc: soc {
286 #address-cells = <1>;
287 #size-cells = <1>;
288 ranges;
289 compatible = "simple-bus";
290
291 imem: memory@700000 {
292 compatible = "qcom,imem-ipq8064", "syscon";
293 reg = <0x00700000 0x1000>;
294 #address-cells = <1>;
295 #size-cells = <1>;
296 ranges = <0x0 0x00700000 0x1000>;
297 };
298
299 rpm@108000 {
300 compatible = "qcom,rpm-ipq8064";
301 reg = <0x108000 0x1000>;
302 qcom,ipc = <&l2cc 0x8 2>;
303
304 interrupts = <0 19 0>,
305 <0 21 0>,
306 <0 22 0>;
307 interrupt-names = "ack",
308 "err",
309 "wakeup";
310
311 #address-cells = <1>;
312 #size-cells = <0>;
313
314 smb208_s1a: smb208-s1a {
315 compatible = "qcom,rpm-smb208";
316 reg = <QCOM_RPM_SMB208_S1a>;
317
318 regulator-min-microvolt = <1050000>;
319 regulator-max-microvolt = <1150000>;
320
321 qcom,switch-mode-frequency = <1200000>;
322
323 };
324
325 smb208_s1b: smb208-s1b {
326 compatible = "qcom,rpm-smb208";
327 reg = <QCOM_RPM_SMB208_S1b>;
328
329 regulator-min-microvolt = <1050000>;
330 regulator-max-microvolt = <1150000>;
331
332 qcom,switch-mode-frequency = <1200000>;
333 };
334
335 smb208_s2a: smb208-s2a {
336 compatible = "qcom,rpm-smb208";
337 reg = <QCOM_RPM_SMB208_S2a>;
338
339 regulator-min-microvolt = < 800000>;
340 regulator-max-microvolt = <1275000>;
341
342 qcom,switch-mode-frequency = <1400000>;
343 };
344
345 smb208_s2b: smb208-s2b {
346 compatible = "qcom,rpm-smb208";
347 reg = <QCOM_RPM_SMB208_S2b>;
348
349 regulator-min-microvolt = < 800000>;
350 regulator-max-microvolt = <1275000>;
351
352 qcom,switch-mode-frequency = <1400000>;
353 };
354
355 cxo_clk: cxo-clk {
356 #clock-cells = <0>;
357 compatible = "qcom,rpm-clk";
358 reg = <QCOM_RPM_CXO_CLK>;
359 qcom,rpm-clk-name = "cxo";
360 qcom,rpm-clk-freq = <25000000>;
361 qcom,rpm-clk-active-only;
362 };
363
364 pxo_clk: pxo-clk {
365 #clock-cells = <0>;
366 compatible = "qcom,rpm-clk";
367 reg = <QCOM_RPM_PXO_CLK>;
368 qcom,rpm-clk-name = "pxo";
369 qcom,rpm-clk-freq = <25000000>;
370 qcom,rpm-clk-active-only;
371 };
372
373 ebi1_clk: ebi1-clk {
374 #clock-cells = <0>;
375 compatible = "qcom,rpm-clk";
376 reg = <QCOM_RPM_EBI1_CLK>;
377 qcom,rpm-clk-name = "ebi1";
378 qcom,rpm-clk-freq = <533000000>;
379 qcom,rpm-clk-active-only;
380 };
381
382 apps_fabric_clk: apps-fabric-clk {
383 #clock-cells = <0>;
384 compatible = "qcom,rpm-clk";
385 reg = <QCOM_RPM_APPS_FABRIC_CLK>;
386 qcom,rpm-clk-name = "apps-fabric";
387 qcom,rpm-clk-freq = <533000000>;
388 qcom,rpm-clk-active-only;
389 };
390
391 nss_fabric0_clk: nss-fabric0-clk {
392 #clock-cells = <0>;
393 compatible = "qcom,rpm-clk";
394 reg = <QCOM_RPM_NSS_FABRIC_0_CLK>;
395 qcom,rpm-clk-name = "nss-fabric0";
396 qcom,rpm-clk-freq = <533000000>;
397 qcom,rpm-clk-active-only;
398 };
399
400 nss_fabric1_clk: nss-fabric1-clk {
401 #clock-cells = <0>;
402 compatible = "qcom,rpm-clk";
403 reg = <QCOM_RPM_NSS_FABRIC_1_CLK>;
404 qcom,rpm-clk-name = "nss-fabric1";
405 qcom,rpm-clk-freq = <266000000>;
406 qcom,rpm-clk-active-only;
407 };
408 };
409
410 rng@1a500000 {
411 compatible = "qcom,prng";
412 reg = <0x1a500000 0x200>;
413 clocks = <&gcc PRNG_CLK>;
414 clock-names = "core";
415 };
416
417 qcom,msm-imem@2A03F000 {
418 compatible = "qcom,msm-imem";
419 reg = <0x2A03F000 0x1000>; /* Address and size of IMEM */
420 ranges = <0x0 0x2A03F000 0x1000>;
421 #address-cells = <1>;
422 #size-cells = <1>;
423
424 download_mode@0 {
425 compatible = "qcom,msm-imem-download_mode";
426 reg = <0x0 8>;
427 };
428
429 restart_reason@65c {
430 compatible = "qcom,msm-imem-restart_reason";
431 reg = <0x65c 4>;
432 };
433
434 l2_dump_offset@14 {
435 compatible = "qcom,msm-imem-l2_dump_offset";
436 reg = <0x14 8>;
437 };
438 };
439
440 qcom_pinmux: pinmux@800000 {
441 compatible = "qcom,ipq8064-pinctrl";
442 reg = <0x800000 0x4000>;
443
444 gpio-controller;
445 #gpio-cells = <2>;
446 interrupt-controller;
447 #interrupt-cells = <2>;
448 interrupts = <0 32 0x4>;
449
450 pcie0_pins: pcie0_pinmux {
451 mux {
452 pins = "gpio3";
453 function = "pcie1_rst";
454 drive-strength = <12>;
455 bias-disable;
456 };
457 };
458
459 pcie1_pins: pcie1_pinmux {
460 mux {
461 pins = "gpio48";
462 function = "pcie2_rst";
463 drive-strength = <12>;
464 bias-disable;
465 };
466 };
467
468 pcie2_pins: pcie2_pinmux {
469 mux {
470 pins = "gpio63";
471 function = "pcie3_rst";
472 drive-strength = <12>;
473 bias-disable;
474 };
475 };
476 };
477
478 intc: interrupt-controller@2000000 {
479 compatible = "qcom,msm-qgic2";
480 interrupt-controller;
481 #interrupt-cells = <3>;
482 reg = <0x02000000 0x1000>,
483 <0x02002000 0x1000>;
484 };
485
486 timer@200a000 {
487 compatible = "qcom,kpss-timer", "qcom,msm-timer";
488 interrupts = <1 1 0x301>,
489 <1 2 0x301>,
490 <1 3 0x301>,
491 <1 4 0x301>,
492 <1 5 0x301>;
493 reg = <0x0200a000 0x100>;
494 clock-frequency = <25000000>,
495 <32768>;
496 clocks = <&sleep_clk>;
497 clock-names = "sleep";
498 cpu-offset = <0x80000>;
499 };
500
501 acc0: clock-controller@2088000 {
502 compatible = "qcom,kpss-acc-v1";
503 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
504 clock-output-names = "acpu0_aux";
505 };
506
507 acc1: clock-controller@2098000 {
508 compatible = "qcom,kpss-acc-v1";
509 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
510 clock-output-names = "acpu1_aux";
511 };
512
513 l2cc: clock-controller@2011000 {
514 compatible = "qcom,kpss-gcc", "syscon";
515 reg = <0x2011000 0x1000>;
516 clock-output-names = "acpu_l2_aux";
517 };
518
519 saw0: regulator@2089000 {
520 compatible = "qcom,saw2";
521 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
522 regulator;
523 };
524
525 saw1: regulator@2099000 {
526 compatible = "qcom,saw2";
527 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
528 regulator;
529 };
530
531 gsbi2: gsbi@12480000 {
532 compatible = "qcom,gsbi-v1.0.0";
533 cell-index = <2>;
534 reg = <0x12480000 0x100>;
535 clocks = <&gcc GSBI2_H_CLK>;
536 clock-names = "iface";
537 #address-cells = <1>;
538 #size-cells = <1>;
539 ranges;
540 status = "disabled";
541
542 syscon-tcsr = <&tcsr>;
543
544 uart2: serial@12490000 {
545 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
546 reg = <0x12490000 0x1000>,
547 <0x12480000 0x1000>;
548 interrupts = <0 195 0x0>;
549 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
550 clock-names = "core", "iface";
551 status = "disabled";
552 };
553
554 i2c@124a0000 {
555 compatible = "qcom,i2c-qup-v1.1.1";
556 reg = <0x124a0000 0x1000>;
557 interrupts = <0 196 0>;
558
559 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
560 clock-names = "core", "iface";
561 status = "disabled";
562
563 #address-cells = <1>;
564 #size-cells = <0>;
565 };
566
567 };
568
569 gsbi4: gsbi@16300000 {
570 compatible = "qcom,gsbi-v1.0.0";
571 cell-index = <4>;
572 reg = <0x16300000 0x100>;
573 clocks = <&gcc GSBI4_H_CLK>;
574 clock-names = "iface";
575 #address-cells = <1>;
576 #size-cells = <1>;
577 ranges;
578 status = "disabled";
579
580 syscon-tcsr = <&tcsr>;
581
582 uart4: serial@16340000 {
583 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
584 reg = <0x16340000 0x1000>,
585 <0x16300000 0x1000>;
586 interrupts = <0 152 0x0>;
587 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
588 clock-names = "core", "iface";
589 status = "disabled";
590 };
591
592 i2c@16380000 {
593 compatible = "qcom,i2c-qup-v1.1.1";
594 reg = <0x16380000 0x1000>;
595 interrupts = <0 153 0>;
596
597 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
598 clock-names = "core", "iface";
599 status = "disabled";
600
601 #address-cells = <1>;
602 #size-cells = <0>;
603 };
604 };
605
606 gsbi5: gsbi@1a200000 {
607 compatible = "qcom,gsbi-v1.0.0";
608 cell-index = <5>;
609 reg = <0x1a200000 0x100>;
610 clocks = <&gcc GSBI5_H_CLK>;
611 clock-names = "iface";
612 #address-cells = <1>;
613 #size-cells = <1>;
614 ranges;
615 status = "disabled";
616
617 syscon-tcsr = <&tcsr>;
618
619 uart5: serial@1a240000 {
620 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
621 reg = <0x1a240000 0x1000>,
622 <0x1a200000 0x1000>;
623 interrupts = <0 154 0x0>;
624 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
625 clock-names = "core", "iface";
626 status = "disabled";
627 };
628
629 i2c@1a280000 {
630 compatible = "qcom,i2c-qup-v1.1.1";
631 reg = <0x1a280000 0x1000>;
632 interrupts = <0 155 0>;
633
634 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
635 clock-names = "core", "iface";
636 status = "disabled";
637
638 #address-cells = <1>;
639 #size-cells = <0>;
640 };
641
642 spi@1a280000 {
643 compatible = "qcom,spi-qup-v1.1.1";
644 reg = <0x1a280000 0x1000>;
645 interrupts = <0 155 0>;
646
647 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
648 clock-names = "core", "iface";
649 status = "disabled";
650
651 #address-cells = <1>;
652 #size-cells = <0>;
653 };
654 };
655
656 sata_phy: sata-phy@1b400000 {
657 compatible = "qcom,ipq806x-sata-phy";
658 reg = <0x1b400000 0x200>;
659
660 clocks = <&gcc SATA_PHY_CFG_CLK>;
661 clock-names = "cfg";
662
663 #phy-cells = <0>;
664 status = "disabled";
665 };
666
667 sata@29000000 {
668 compatible = "qcom,ipq806x-ahci", "generic-ahci";
669 reg = <0x29000000 0x180>;
670
671 interrupts = <0 209 0x0>;
672
673 clocks = <&gcc SFAB_SATA_S_H_CLK>,
674 <&gcc SATA_H_CLK>,
675 <&gcc SATA_A_CLK>,
676 <&gcc SATA_RXOOB_CLK>,
677 <&gcc SATA_PMALIVE_CLK>;
678 clock-names = "slave_face", "iface", "core",
679 "rxoob", "pmalive";
680
681 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
682 assigned-clock-rates = <100000000>, <100000000>;
683
684 phys = <&sata_phy>;
685 phy-names = "sata-phy";
686 status = "disabled";
687 };
688
689 qcom,ssbi@500000 {
690 compatible = "qcom,ssbi";
691 reg = <0x00500000 0x1000>;
692 qcom,controller-type = "pmic-arbiter";
693 };
694
695 gcc: clock-controller@900000 {
696 compatible = "qcom,gcc-ipq8064";
697 reg = <0x00900000 0x4000>;
698 #clock-cells = <1>;
699 #reset-cells = <1>;
700 };
701
702 tcsr: syscon@1a400000 {
703 compatible = "qcom,tcsr-ipq8064", "syscon";
704 reg = <0x1a400000 0x100>;
705 };
706
707 tsens: tsens-ipq806x {
708 compatible = "qcom,ipq806x-tsens";
709 reg = <0x900000 0x3678>, <0x700000 0x420>;
710 reg-names = "tsens_physical", "tsens_eeprom_physical";
711 interrupts = <0 178 0>;
712 qcom,sensors = <11>;
713 qcom,tsens_factor = <1000>;
714 qcom,slope = <1176 1176 1154 1176 1111 1132 1132 1199 1132 1199 1132>;
715 };
716
717 qcom,msm-thermal {
718 compatible = "qcom,msm-thermal";
719 qcom,sensor-id = <0>;
720 qcom,poll-ms = <250>;
721 qcom,limit-temp = <105>;
722 qcom,temp-hysteresis = <10>;
723 qcom,freq-step = <2>;
724 qcom,core-limit-temp = <115>;
725 qcom,core-temp-hysteresis = <10>;
726 qcom,core-control-mask = <0xe>;
727 };
728
729 sfpb_mutex_block: syscon@1200600 {
730 compatible = "syscon";
731 reg = <0x01200600 0x100>;
732 };
733
734 hs_phy_1: phy@100f8800 {
735 compatible = "qcom,dwc3-hs-usb-phy";
736 reg = <0x100f8800 0x30>;
737 clocks = <&gcc USB30_1_UTMI_CLK>;
738 clock-names = "ref";
739 #phy-cells = <0>;
740
741 status = "disabled";
742 };
743
744 ss_phy_1: phy@100f8830 {
745 compatible = "qcom,dwc3-ss-usb-phy";
746 reg = <0x100f8830 0x30>;
747 clocks = <&gcc USB30_1_MASTER_CLK>;
748 clock-names = "ref";
749 #phy-cells = <0>;
750
751 status = "disabled";
752 };
753
754 hs_phy_0: phy@110f8800 {
755 compatible = "qcom,dwc3-hs-usb-phy";
756 reg = <0x110f8800 0x30>;
757 clocks = <&gcc USB30_0_UTMI_CLK>;
758 clock-names = "ref";
759 #phy-cells = <0>;
760
761 status = "disabled";
762 };
763
764 ss_phy_0: phy@110f8830 {
765 compatible = "qcom,dwc3-ss-usb-phy";
766 reg = <0x110f8830 0x30>;
767 clocks = <&gcc USB30_0_MASTER_CLK>;
768 clock-names = "ref";
769 #phy-cells = <0>;
770
771 status = "disabled";
772 };
773
774 usb3_0: usb30@0 {
775 compatible = "qcom,dwc3";
776 #address-cells = <1>;
777 #size-cells = <1>;
778 clocks = <&gcc USB30_0_MASTER_CLK>;
779 clock-names = "core";
780
781 ranges;
782
783 status = "disabled";
784 resets = <&gcc USB30_0_MASTER_RESET>;
785 reset-names = "usb30_mstr_rst";
786
787 dwc3@11000000 {
788 compatible = "snps,dwc3";
789 reg = <0x11000000 0xcd00>;
790 interrupts = <0 110 0x4>;
791 phys = <&hs_phy_0>, <&ss_phy_0>;
792 phy-names = "usb2-phy", "usb3-phy";
793 tx-fifo-resize;
794 dr_mode = "host";
795 };
796 };
797
798 usb3_1: usb30@1 {
799 compatible = "qcom,dwc3";
800 #address-cells = <1>;
801 #size-cells = <1>;
802 clocks = <&gcc USB30_1_MASTER_CLK>;
803 clock-names = "core";
804
805 ranges;
806
807 status = "disabled";
808
809 dwc3@10000000 {
810 compatible = "snps,dwc3";
811 reg = <0x10000000 0xcd00>;
812 interrupts = <0 205 0x4>;
813 phys = <&hs_phy_1>, <&ss_phy_1>;
814 phy-names = "usb2-phy", "usb3-phy";
815 tx-fifo-resize;
816 dr_mode = "host";
817 };
818 };
819
820 pcie0: pci@1b500000 {
821 compatible = "qcom,pcie-v0";
822 reg = <0x1b500000 0x1000
823 0x1b502000 0x80
824 0x1b600000 0x100
825 0x0ff00000 0x100000>;
826 reg-names = "dbi", "elbi", "parf", "config";
827 device_type = "pci";
828 linux,pci-domain = <0>;
829 bus-range = <0x00 0xff>;
830 num-lanes = <1>;
831 #address-cells = <3>;
832 #size-cells = <2>;
833
834 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
835 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
836
837 interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
838 interrupt-names = "msi";
839 #interrupt-cells = <1>;
840 interrupt-map-mask = <0 0 0 0x7>;
841 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
842 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
843 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
844 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
845
846 clocks = <&gcc PCIE_A_CLK>,
847 <&gcc PCIE_H_CLK>,
848 <&gcc PCIE_PHY_CLK>,
849 <&gcc PCIE_AUX_CLK>,
850 <&gcc PCIE_ALT_REF_CLK>;
851 clock-names = "core", "iface", "phy", "aux", "ref";
852
853 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
854 assigned-clock-rates = <100000000>;
855
856 resets = <&gcc PCIE_ACLK_RESET>,
857 <&gcc PCIE_HCLK_RESET>,
858 <&gcc PCIE_POR_RESET>,
859 <&gcc PCIE_PCI_RESET>,
860 <&gcc PCIE_PHY_RESET>,
861 <&gcc PCIE_EXT_RESET>;
862 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
863
864 pinctrl-0 = <&pcie0_pins>;
865 pinctrl-names = "default";
866
867 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
868
869 status = "disabled";
870 };
871
872 pcie1: pci@1b700000 {
873 compatible = "qcom,pcie-v0";
874 reg = <0x1b700000 0x1000
875 0x1b702000 0x80
876 0x1b800000 0x100
877 0x31f00000 0x100000>;
878 reg-names = "dbi", "elbi", "parf", "config";
879 device_type = "pci";
880 linux,pci-domain = <1>;
881 bus-range = <0x00 0xff>;
882 num-lanes = <1>;
883 #address-cells = <3>;
884 #size-cells = <2>;
885
886 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
887 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
888
889 interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
890 interrupt-names = "msi";
891 #interrupt-cells = <1>;
892 interrupt-map-mask = <0 0 0 0x7>;
893 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
894 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
895 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
896 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
897
898 clocks = <&gcc PCIE_1_A_CLK>,
899 <&gcc PCIE_1_H_CLK>,
900 <&gcc PCIE_1_PHY_CLK>,
901 <&gcc PCIE_1_AUX_CLK>,
902 <&gcc PCIE_1_ALT_REF_CLK>;
903 clock-names = "core", "iface", "phy", "aux", "ref";
904
905 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
906 assigned-clock-rates = <100000000>;
907
908 resets = <&gcc PCIE_1_ACLK_RESET>,
909 <&gcc PCIE_1_HCLK_RESET>,
910 <&gcc PCIE_1_POR_RESET>,
911 <&gcc PCIE_1_PCI_RESET>,
912 <&gcc PCIE_1_PHY_RESET>,
913 <&gcc PCIE_1_EXT_RESET>;
914 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
915
916 pinctrl-0 = <&pcie1_pins>;
917 pinctrl-names = "default";
918
919 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
920
921 status = "disabled";
922 };
923
924 pcie2: pci@1b900000 {
925 compatible = "qcom,pcie-v0";
926 reg = <0x1b900000 0x1000
927 0x1b902000 0x80
928 0x1ba00000 0x100
929 0x35f00000 0x100000>;
930 reg-names = "dbi", "elbi", "parf", "config";
931 device_type = "pci";
932 linux,pci-domain = <2>;
933 bus-range = <0x00 0xff>;
934 num-lanes = <1>;
935 #address-cells = <3>;
936 #size-cells = <2>;
937
938 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
939 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
940
941 interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
942 interrupt-names = "msi";
943 #interrupt-cells = <1>;
944 interrupt-map-mask = <0 0 0 0x7>;
945 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
946 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
947 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
948 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
949
950 clocks = <&gcc PCIE_2_A_CLK>,
951 <&gcc PCIE_2_H_CLK>,
952 <&gcc PCIE_2_PHY_CLK>,
953 <&gcc PCIE_2_AUX_CLK>,
954 <&gcc PCIE_2_ALT_REF_CLK>;
955 clock-names = "core", "iface", "phy", "aux", "ref";
956
957 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
958 assigned-clock-rates = <100000000>;
959
960 resets = <&gcc PCIE_2_ACLK_RESET>,
961 <&gcc PCIE_2_HCLK_RESET>,
962 <&gcc PCIE_2_POR_RESET>,
963 <&gcc PCIE_2_PCI_RESET>,
964 <&gcc PCIE_2_PHY_RESET>,
965 <&gcc PCIE_2_EXT_RESET>;
966 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
967
968 pinctrl-0 = <&pcie2_pins>;
969 pinctrl-names = "default";
970
971 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
972
973 status = "disabled";
974 };
975
976 adm_dma: dma@18300000 {
977 compatible = "qcom,adm";
978 reg = <0x18300000 0x100000>;
979 interrupts = <0 170 0>;
980 #dma-cells = <1>;
981
982 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
983 clock-names = "core", "iface";
984
985 resets = <&gcc ADM0_RESET>,
986 <&gcc ADM0_PBUS_RESET>,
987 <&gcc ADM0_C0_RESET>,
988 <&gcc ADM0_C1_RESET>,
989 <&gcc ADM0_C2_RESET>;
990 reset-names = "clk", "pbus", "c0", "c1", "c2";
991 qcom,ee = <0>;
992
993 status = "disabled";
994 };
995
996 nand@1ac00000 {
997 compatible = "qcom,ebi2-nandc";
998 reg = <0x1ac00000 0x800>;
999
1000 clocks = <&gcc EBI2_CLK>,
1001 <&gcc EBI2_AON_CLK>;
1002 clock-names = "core", "aon";
1003
1004 dmas = <&adm_dma 3>;
1005 dma-names = "rxtx";
1006 qcom,cmd-crci = <15>;
1007 qcom,data-crci = <3>;
1008
1009 status = "disabled";
1010 };
1011
1012 nss_common: syscon@03000000 {
1013 compatible = "syscon";
1014 reg = <0x03000000 0x0000FFFF>;
1015 };
1016
1017 qsgmii_csr: syscon@1bb00000 {
1018 compatible = "syscon";
1019 reg = <0x1bb00000 0x000001FF>;
1020 };
1021
1022 gmac0: ethernet@37000000 {
1023 device_type = "network";
1024 compatible = "qcom,ipq806x-gmac";
1025 reg = <0x37000000 0x200000>;
1026 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1027 interrupt-names = "macirq";
1028
1029 qcom,nss-common = <&nss_common>;
1030 qcom,qsgmii-csr = <&qsgmii_csr>;
1031
1032 clocks = <&gcc GMAC_CORE1_CLK>;
1033 clock-names = "stmmaceth";
1034
1035 resets = <&gcc GMAC_CORE1_RESET>;
1036 reset-names = "stmmaceth";
1037
1038 status = "disabled";
1039 };
1040
1041 gmac1: ethernet@37200000 {
1042 device_type = "network";
1043 compatible = "qcom,ipq806x-gmac";
1044 reg = <0x37200000 0x200000>;
1045 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1046 interrupt-names = "macirq";
1047
1048 qcom,nss-common = <&nss_common>;
1049 qcom,qsgmii-csr = <&qsgmii_csr>;
1050
1051 clocks = <&gcc GMAC_CORE2_CLK>;
1052 clock-names = "stmmaceth";
1053
1054 resets = <&gcc GMAC_CORE2_RESET>;
1055 reset-names = "stmmaceth";
1056
1057 status = "disabled";
1058 };
1059
1060 gmac2: ethernet@37400000 {
1061 device_type = "network";
1062 compatible = "qcom,ipq806x-gmac";
1063 reg = <0x37400000 0x200000>;
1064 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1065 interrupt-names = "macirq";
1066
1067 qcom,nss-common = <&nss_common>;
1068 qcom,qsgmii-csr = <&qsgmii_csr>;
1069
1070 clocks = <&gcc GMAC_CORE3_CLK>;
1071 clock-names = "stmmaceth";
1072
1073 resets = <&gcc GMAC_CORE3_RESET>;
1074 reset-names = "stmmaceth";
1075
1076 status = "disabled";
1077 };
1078
1079 gmac3: ethernet@37600000 {
1080 device_type = "network";
1081 compatible = "qcom,ipq806x-gmac";
1082 reg = <0x37600000 0x200000>;
1083 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1084 interrupt-names = "macirq";
1085
1086 qcom,nss-common = <&nss_common>;
1087 qcom,qsgmii-csr = <&qsgmii_csr>;
1088
1089 clocks = <&gcc GMAC_CORE4_CLK>;
1090 clock-names = "stmmaceth";
1091
1092 resets = <&gcc GMAC_CORE4_RESET>;
1093 reset-names = "stmmaceth";
1094
1095 status = "disabled";
1096 };
1097 /* Temporary fixed regulator */
1098 vsdcc_fixed: vsdcc-regulator {
1099 compatible = "regulator-fixed";
1100 regulator-name = "SDCC Power";
1101 regulator-min-microvolt = <3300000>;
1102 regulator-max-microvolt = <3300000>;
1103 regulator-always-on;
1104 };
1105
1106 sdcc1bam:dma@12402000 {
1107 compatible = "qcom,bam-v1.3.0";
1108 reg = <0x12402000 0x8000>;
1109 interrupts = <0 98 0>;
1110 clocks = <&gcc SDC1_H_CLK>;
1111 clock-names = "bam_clk";
1112 #dma-cells = <1>;
1113 qcom,ee = <0>;
1114 };
1115
1116 sdcc3bam:dma@12182000 {
1117 compatible = "qcom,bam-v1.3.0";
1118 reg = <0x12182000 0x8000>;
1119 interrupts = <0 96 0>;
1120 clocks = <&gcc SDC3_H_CLK>;
1121 clock-names = "bam_clk";
1122 #dma-cells = <1>;
1123 qcom,ee = <0>;
1124 };
1125
1126 amba {
1127 compatible = "arm,amba-bus";
1128 #address-cells = <1>;
1129 #size-cells = <1>;
1130 ranges;
1131 sdcc1: sdcc@12400000 {
1132 status = "disabled";
1133 compatible = "arm,pl18x", "arm,primecell";
1134 arm,primecell-periphid = <0x00051180>;
1135 reg = <0x12400000 0x2000>;
1136 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1137 interrupt-names = "cmd_irq";
1138 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1139 clock-names = "mclk", "apb_pclk";
1140 bus-width = <8>;
1141 max-frequency = <48000000>;
1142 non-removable;
1143 cap-sd-highspeed;
1144 cap-mmc-highspeed;
1145 vmmc-supply = <&vsdcc_fixed>;
1146 #dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1147 #dma-names = "tx", "rx";
1148 };
1149
1150 sdcc3: sdcc@12180000 {
1151 compatible = "arm,pl18x", "arm,primecell";
1152 arm,primecell-periphid = <0x00051180>;
1153 status = "disabled";
1154 reg = <0x12180000 0x2000>;
1155 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1156 interrupt-names = "cmd_irq";
1157 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1158 clock-names = "mclk", "apb_pclk";
1159 bus-width = <8>;
1160 cap-sd-highspeed;
1161 cap-mmc-highspeed;
1162 max-frequency = <192000000>;
1163 #mmc-ddr-1_8v;
1164 sd-uhs-sdr50;
1165 vmmc-supply = <&vsdcc_fixed>;
1166 #dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1167 #dma-names = "tx", "rx";
1168 };
1169 };
1170
1171 };
1172
1173 sfpb_mutex: sfpb-mutex {
1174 compatible = "qcom,sfpb-mutex";
1175 syscon = <&sfpb_mutex_block 4 4>;
1176
1177 #hwlock-cells = <1>;
1178 };
1179
1180 smem {
1181 compatible = "qcom,smem";
1182 memory-region = <&smem>;
1183 hwlocks = <&sfpb_mutex 3>;
1184 };
1185 };