target/linux/ipq806x/patches-4.4/139-clk-qcom-Add-IPQ806X-s-HFPLLs.patch

   1 Content-Type: text/plain; charset="utf-8"
   2 MIME-Version: 1.0
   3 Content-Transfer-Encoding: 7bit
   4 Subject: [v3,08/13] clk: qcom: Add IPQ806X's HFPLLs
   5 From: Stephen Boyd <sboyd@codeaurora.org>
   6 X-Patchwork-Id: 6063241
   7 Message-Id: <1426920332-9340-9-git-send-email-sboyd@codeaurora.org>
   8 To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
   9 Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
  10         linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
  11         Viresh Kumar <viresh.kumar@linaro.org>
  12 Date: Fri, 20 Mar 2015 23:45:27 -0700
  13
  14 Describe the HFPLLs present on IPQ806X devices.
  15
  16 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  17
  18 ---
  19 drivers/clk/qcom/gcc-ipq806x.c | 83 ++++++++++++++++++++++++++++++++++++++++++
  20  1 file changed, 83 insertions(+)
  21
  22 --- a/drivers/clk/qcom/gcc-ipq806x.c
  23 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  24 @@ -30,6 +30,7 @@
  25  #include "clk-pll.h"
  26  #include "clk-rcg.h"
  27  #include "clk-branch.h"
  28 +#include "clk-hfpll.h"
  29  #include "reset.h"
  30
  31  static struct clk_pll pll0 = {
  32 @@ -113,6 +114,85 @@ static struct clk_regmap pll8_vote = {
  33         },
  34  };
  35
  36 +static struct hfpll_data hfpll0_data = {
  37 +       .mode_reg = 0x3200,
  38 +       .l_reg = 0x3208,
  39 +       .m_reg = 0x320c,
  40 +       .n_reg = 0x3210,
  41 +       .config_reg = 0x3204,
  42 +       .status_reg = 0x321c,
  43 +       .config_val = 0x7845c665,
  44 +       .droop_reg = 0x3214,
  45 +       .droop_val = 0x0108c000,
  46 +       .min_rate = 600000000UL,
  47 +       .max_rate = 1800000000UL,
  48 +};
  49 +
  50 +static struct clk_hfpll hfpll0 = {
  51 +       .d = &hfpll0_data,
  52 +       .clkr.hw.init = &(struct clk_init_data){
  53 +               .parent_names = (const char *[]){ "pxo" },
  54 +               .num_parents = 1,
  55 +               .name = "hfpll0",
  56 +               .ops = &clk_ops_hfpll,
  57 +               .flags = CLK_IGNORE_UNUSED,
  58 +       },
  59 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
  60 +};
  61 +
  62 +static struct hfpll_data hfpll1_data = {
  63 +       .mode_reg = 0x3240,
  64 +       .l_reg = 0x3248,
  65 +       .m_reg = 0x324c,
  66 +       .n_reg = 0x3250,
  67 +       .config_reg = 0x3244,
  68 +       .status_reg = 0x325c,
  69 +       .config_val = 0x7845c665,
  70 +       .droop_reg = 0x3314,
  71 +       .droop_val = 0x0108c000,
  72 +       .min_rate = 600000000UL,
  73 +       .max_rate = 1800000000UL,
  74 +};
  75 +
  76 +static struct clk_hfpll hfpll1 = {
  77 +       .d = &hfpll1_data,
  78 +       .clkr.hw.init = &(struct clk_init_data){
  79 +               .parent_names = (const char *[]){ "pxo" },
  80 +               .num_parents = 1,
  81 +               .name = "hfpll1",
  82 +               .ops = &clk_ops_hfpll,
  83 +               .flags = CLK_IGNORE_UNUSED,
  84 +       },
  85 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
  86 +};
  87 +
  88 +static struct hfpll_data hfpll_l2_data = {
  89 +       .mode_reg = 0x3300,
  90 +       .l_reg = 0x3308,
  91 +       .m_reg = 0x330c,
  92 +       .n_reg = 0x3310,
  93 +       .config_reg = 0x3304,
  94 +       .status_reg = 0x331c,
  95 +       .config_val = 0x7845c665,
  96 +       .droop_reg = 0x3314,
  97 +       .droop_val = 0x0108c000,
  98 +       .min_rate = 600000000UL,
  99 +       .max_rate = 1800000000UL,
 100 +};
 101 +
 102 +static struct clk_hfpll hfpll_l2 = {
 103 +               .d = &hfpll_l2_data,
 104 +               .clkr.hw.init = &(struct clk_init_data){
 105 +               .parent_names = (const char *[]){ "pxo" },
 106 +               .num_parents = 1,
 107 +               .name = "hfpll_l2",
 108 +               .ops = &clk_ops_hfpll,
 109 +               .flags = CLK_IGNORE_UNUSED,
 110 +       },
 111 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
 112 +};
 113 +
 114 +
 115  static struct clk_pll pll14 = {
 116         .l_reg = 0x31c4,
 117         .m_reg = 0x31c8,
 118 @@ -2837,6 +2917,9 @@ static struct clk_regmap *gcc_ipq806x_cl
 119         [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
 120         [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
 121         [NSSTCM_CLK] = &nss_tcm_clk.clkr,
 122 +       [PLL9] = &hfpll0.clkr,
 123 +       [PLL10] = &hfpll1.clkr,
 124 +       [PLL12] = &hfpll_l2.clkr,
 125  };
 126
 127  static const struct qcom_reset_map gcc_ipq806x_resets[] = {