target/linux/ipq806x/patches-4.4/140-clk-qcom-Add-support-for-Krait-clocks.patch

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   4 Subject: [v3,09/13] clk: qcom: Add support for Krait clocks
   5 From: Stephen Boyd <sboyd@codeaurora.org>
   6 X-Patchwork-Id: 6063251
   7 Message-Id: <1426920332-9340-10-git-send-email-sboyd@codeaurora.org>
   8 To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
   9 Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
  10         linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
  11         Viresh Kumar <viresh.kumar@linaro.org>
  12 Date: Fri, 20 Mar 2015 23:45:28 -0700
  13
  14 The Krait clocks are made up of a series of muxes and a divider
  15 that choose between a fixed rate clock and dedicated HFPLLs for
  16 each CPU. Instead of using mmio accesses to remux parents, the
  17 Krait implementation exposes the remux control via cp15
  18 registers. Support these clocks.
  19
  20 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  21
  22 ---
  23 drivers/clk/qcom/Kconfig     |   4 ++
  24  drivers/clk/qcom/Makefile    |   1 +
  25  drivers/clk/qcom/clk-krait.c | 166 +++++++++++++++++++++++++++++++++++++++++++
  26  drivers/clk/qcom/clk-krait.h |  49 +++++++++++++
  27  4 files changed, 220 insertions(+)
  28  create mode 100644 drivers/clk/qcom/clk-krait.c
  29  create mode 100644 drivers/clk/qcom/clk-krait.h
  30
  31 --- a/drivers/clk/qcom/Kconfig
  32 +++ b/drivers/clk/qcom/Kconfig
  33 @@ -114,3 +114,7 @@
  34           Support for the high-frequency PLLs present on Qualcomm devices.
  35           Say Y if you want to support CPU frequency scaling on devices
  36           such as MSM8974, APQ8084, etc.
  37 +
  38 +config KRAIT_CLOCKS
  39 +       bool
  40 +       select KRAIT_L2_ACCESSORS
  41 --- a/drivers/clk/qcom/Makefile
  42 +++ b/drivers/clk/qcom/Makefile
  43 @@ -8,6 +8,7 @@
  44  clk-qcom-y += clk-branch.o
  45  clk-qcom-y += clk-regmap-divider.o
  46  clk-qcom-y += clk-regmap-mux.o
  47 +clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
  48  clk-qcom-y += clk-hfpll.o
  49  clk-qcom-y += reset.o
  50  clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
  51
  52 --- /dev/null
  53 +++ b/drivers/clk/qcom/clk-krait.c
  54 @@ -0,0 +1,166 @@
  55 +/*
  56 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  57 + *
  58 + * This program is free software; you can redistribute it and/or modify
  59 + * it under the terms of the GNU General Public License version 2 and
  60 + * only version 2 as published by the Free Software Foundation.
  61 + *
  62 + * This program is distributed in the hope that it will be useful,
  63 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  64 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  65 + * GNU General Public License for more details.
  66 + */
  67 +
  68 +#include <linux/kernel.h>
  69 +#include <linux/module.h>
  70 +#include <linux/init.h>
  71 +#include <linux/io.h>
  72 +#include <linux/delay.h>
  73 +#include <linux/err.h>
  74 +#include <linux/clk-provider.h>
  75 +#include <linux/spinlock.h>
  76 +
  77 +#include <asm/krait-l2-accessors.h>
  78 +
  79 +#include "clk-krait.h"
  80 +
  81 +/* Secondary and primary muxes share the same cp15 register */
  82 +static DEFINE_SPINLOCK(krait_clock_reg_lock);
  83 +
  84 +#define LPL_SHIFT      8
  85 +static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
  86 +{
  87 +       unsigned long flags;
  88 +       u32 regval;
  89 +
  90 +       spin_lock_irqsave(&krait_clock_reg_lock, flags);
  91 +       regval = krait_get_l2_indirect_reg(mux->offset);
  92 +       regval &= ~(mux->mask << mux->shift);
  93 +       regval |= (sel & mux->mask) << mux->shift;
  94 +       if (mux->lpl) {
  95 +               regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
  96 +               regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
  97 +       }
  98 +       krait_set_l2_indirect_reg(mux->offset, regval);
  99 +       spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
 100 +
 101 +       /* Wait for switch to complete. */
 102 +       mb();
 103 +       udelay(1);
 104 +}
 105 +
 106 +static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
 107 +{
 108 +       struct krait_mux_clk *mux = to_krait_mux_clk(hw);
 109 +       u32 sel;
 110 +
 111 +       sel = clk_mux_reindex(index, mux->parent_map, 0);
 112 +       mux->en_mask = sel;
 113 +       /* Don't touch mux if CPU is off as it won't work */
 114 +       if (__clk_is_enabled(hw->clk))
 115 +               __krait_mux_set_sel(mux, sel);
 116 +       return 0;
 117 +}
 118 +
 119 +static u8 krait_mux_get_parent(struct clk_hw *hw)
 120 +{
 121 +       struct krait_mux_clk *mux = to_krait_mux_clk(hw);
 122 +       u32 sel;
 123 +
 124 +       sel = krait_get_l2_indirect_reg(mux->offset);
 125 +       sel >>= mux->shift;
 126 +       sel &= mux->mask;
 127 +       mux->en_mask = sel;
 128 +
 129 +       return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
 130 +}
 131 +
 132 +static struct clk_hw *krait_mux_get_safe_parent(struct clk_hw *hw)
 133 +{
 134 +       int i;
 135 +       struct krait_mux_clk *mux = to_krait_mux_clk(hw);
 136 +       int num_parents = clk_hw_get_num_parents(hw->clk);
 137 +
 138 +       i = mux->safe_sel;
 139 +       for (i = 0; i < num_parents; i++)
 140 +               if (mux->safe_sel == mux->parent_map[i])
 141 +                       break;
 142 +
 143 +       return __clk_get_hw(clk_hw_get_parent_by_index(hw->clk, i));
 144 +}
 145 +
 146 +static int krait_mux_enable(struct clk_hw *hw)
 147 +{
 148 +       struct krait_mux_clk *mux = to_krait_mux_clk(hw);
 149 +
 150 +       __krait_mux_set_sel(mux, mux->en_mask);
 151 +
 152 +       return 0;
 153 +}
 154 +
 155 +static void krait_mux_disable(struct clk_hw *hw)
 156 +{
 157 +       struct krait_mux_clk *mux = to_krait_mux_clk(hw);
 158 +
 159 +       __krait_mux_set_sel(mux, mux->safe_sel);
 160 +}
 161 +
 162 +const struct clk_ops krait_mux_clk_ops = {
 163 +       .enable = krait_mux_enable,
 164 +       .disable = krait_mux_disable,
 165 +       .set_parent = krait_mux_set_parent,
 166 +       .get_parent = krait_mux_get_parent,
 167 +       .determine_rate = __clk_mux_determine_rate_closest,
 168 +       .get_safe_parent = krait_mux_get_safe_parent,
 169 +};
 170 +EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
 171 +
 172 +/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
 173 +static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
 174 +                                 unsigned long *parent_rate)
 175 +{
 176 +       *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw->clk), rate * 2);
 177 +       return DIV_ROUND_UP(*parent_rate, 2);
 178 +}
 179 +
 180 +static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
 181 +                       unsigned long parent_rate)
 182 +{
 183 +       struct krait_div2_clk *d = to_krait_div2_clk(hw);
 184 +       unsigned long flags;
 185 +       u32 val;
 186 +       u32 mask = BIT(d->width) - 1;
 187 +
 188 +       if (d->lpl)
 189 +               mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
 190 +
 191 +       spin_lock_irqsave(&krait_clock_reg_lock, flags);
 192 +       val = krait_get_l2_indirect_reg(d->offset);
 193 +       val &= ~mask;
 194 +       krait_set_l2_indirect_reg(d->offset, val);
 195 +       spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
 196 +
 197 +       return 0;
 198 +}
 199 +
 200 +static unsigned long
 201 +krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 202 +{
 203 +       struct krait_div2_clk *d = to_krait_div2_clk(hw);
 204 +       u32 mask = BIT(d->width) - 1;
 205 +       u32 div;
 206 +
 207 +       div = krait_get_l2_indirect_reg(d->offset);
 208 +       div >>= d->shift;
 209 +       div &= mask;
 210 +       div = (div + 1) * 2;
 211 +
 212 +       return DIV_ROUND_UP(parent_rate, div);
 213 +}
 214 +
 215 +const struct clk_ops krait_div2_clk_ops = {
 216 +       .round_rate = krait_div2_round_rate,
 217 +       .set_rate = krait_div2_set_rate,
 218 +       .recalc_rate = krait_div2_recalc_rate,
 219 +};
 220 +EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
 221 --- /dev/null
 222 +++ b/drivers/clk/qcom/clk-krait.h
 223 @@ -0,0 +1,49 @@
 224 +/*
 225 + * Copyright (c) 2013, The Linux Foundation. All rights reserved.
 226 + *
 227 + * This program is free software; you can redistribute it and/or modify
 228 + * it under the terms of the GNU General Public License version 2 and
 229 + * only version 2 as published by the Free Software Foundation.
 230 + *
 231 + * This program is distributed in the hope that it will be useful,
 232 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 233 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 234 + * GNU General Public License for more details.
 235 + */
 236 +
 237 +#ifndef __QCOM_CLK_KRAIT_H
 238 +#define __QCOM_CLK_KRAIT_H
 239 +
 240 +#include <linux/clk-provider.h>
 241 +
 242 +struct krait_mux_clk {
 243 +       unsigned int    *parent_map;
 244 +       bool            has_safe_parent;
 245 +       u8              safe_sel;
 246 +       u32             offset;
 247 +       u32             mask;
 248 +       u32             shift;
 249 +       u32             en_mask;
 250 +       bool            lpl;
 251 +
 252 +       struct clk_hw   hw;
 253 +};
 254 +
 255 +#define to_krait_mux_clk(_hw) container_of(_hw, struct krait_mux_clk, hw)
 256 +
 257 +extern const struct clk_ops krait_mux_clk_ops;
 258 +
 259 +struct krait_div2_clk {
 260 +       u32             offset;
 261 +       u8              width;
 262 +       u32             shift;
 263 +       bool            lpl;
 264 +
 265 +       struct clk_hw   hw;
 266 +};
 267 +
 268 +#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
 269 +
 270 +extern const struct clk_ops krait_div2_clk_ops;
 271 +
 272 +#endif