target/linux/lantiq/patches-4.4/0301-xrx200-add-gphy-clk-src-device-tree-binding.patch

   1 --- a/arch/mips/lantiq/xway/sysctrl.c
   2 +++ b/arch/mips/lantiq/xway/sysctrl.c
   3 @@ -423,6 +423,20 @@ static void clkdev_add_clkout(void)
   4         }
   5  }
   6
   7 +static void set_phy_clock_source(struct device_node *np_cgu)
   8 +{
   9 +       u32 phy_clk_src, ifcc;
  10 +
  11 +       if (!np_cgu)
  12 +               return;
  13 +
  14 +       if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
  15 +               return;
  16 +
  17 +       ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
  18 +       ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
  19 +}
  20 +
  21  /* bring up all register ranges that we need for basic system control */
  22  void __init ltq_soc_init(void)
  23  {
  24 @@ -608,4 +622,6 @@ void __init ltq_soc_init(void)
  25
  26         if (of_machine_is_compatible("lantiq,vr9"))
  27                 xbar_fpi_burst_disable();
  28 +
  29 +       set_phy_clock_source(np_cgu);
  30  }