target/linux/mvebu/patches-3.10/0021-arm-mvebu-armada-xp-db-ensure-PCIe-range-is-specifie.patch

   1 From 67373874e07eb8c54ab27f8fe9998690e50b1e91 Mon Sep 17 00:00:00 2001
   2 From: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
   3 Date: Thu, 6 Jun 2013 11:21:23 +0200
   4 Subject: [PATCH 021/203] arm: mvebu: armada-xp-db: ensure PCIe range is
   5  specified
   6
   7 The ranges DT entry needed by the PCIe controller is defined at the
   8 SoC .dtsi level. However, some boards have a NOR flash, and to support
   9 it, they need to override the SoC-level ranges property to add an
  10 additional range. Since PCIe and NOR support came separately, some
  11 boards were not properly changed to include the PCIe range in their
  12 ranges property at the .dts level.
  13
  14 This commit fixes those platforms.
  15
  16 Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  17 Signed-off-by: Jason Cooper <jason@lakedaemon.net>
  18 ---
  19  arch/arm/boot/dts/armada-xp-db.dts | 1 +
  20  1 file changed, 1 insertion(+)
  21
  22 --- a/arch/arm/boot/dts/armada-xp-db.dts
  23 +++ b/arch/arm/boot/dts/armada-xp-db.dts
  24 @@ -31,6 +31,7 @@
  25
  26         soc {
  27                 ranges = <0          0 0xd0000000 0x100000      /* Internal registers 1MiB */
  28 +                         0xe0000000 0 0xe0000000 0x8100000     /* PCIe */
  29                           0xf0000000 0 0xf0000000 0x1000000>;   /* Device Bus, NOR 16MiB   */
  30
  31                 internal-regs {