ramips: move and rename out-of-tree mtk eth driver move the driver into shared 'files' directory and rename all symbols from mediatek/mtk to ralink. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
ramips: mt7620: add rgmii delays support At this moment mt7620 ethernet driver doesn't support rgmii delays configuration. SoC MT7620 have bits 2 and 3 in GPC1 an GPC2 to configure delays for rx and tx rgmii interface. This patch adds rx/tx rgmii delay configuration from dts. Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
ramips: move MTK MMC driver to files directory Move MTK MMC driver from "files-4.14" to "files" so kernel 5.4 can use it Signed-off-by: DENG Qingfang <dengqf6@mail2.sysu.edu.cn>
ramips: mt7530: remove redundant global attrs for port mirroring Global attributes enable_mirror_tx/enable_mirror_rx depend on runtime value of another global attribute mirror_source_port which just resides in the memory The same functionality can be achieved by directly setting port attribute of the same names. E.g. the following two groups of commands achieve the same thing swconfig dev switch0 set mirror_source_port 3 swconfig dev switch0 set enable_mirror_tx 1 swconfig dev switch0 set mirror_source_port 4 swconfig dev switch0 set enable_mirror_tx 1 swconfig dev switch0 port 3 set enable_mirror_tx 1 swconfig dev switch0 port 4 set enable_mirror_tx 1 Signed-off-by: Yousong Zhou <yszhou4tech@gmail.com>
ramips: gsw_mt7621: disable PORT 5 MAC RX/TX flow control by default Looking at the current upstream driver implementation, it seems like the TX/RX flow control is enabled only if the flow control pause option is resolved from the device/link partner advertisements (or otherwise set). On the other hand, our current in-tree driver force enables TX/RX flow control by default, thus possibly leading to TX timeouts if the other end sends pause frames (which are not properly handled?): WARNING: CPU: 3 PID: 0 at net/sched/sch_generic.c:320 dev_watchdog+0x1ac/0x324 NETDEV WATCHDOG: eth0 (mtk_soc_eth): transmit queue 0 timed out Disabling the flow control on PORT 5 MAC seems to fix this issues as the pause frames are then filtered out. While at it, I'm removing the if condition completely as suggested, since this code is run only on mt7621 SoC, so there is no need to check for the silicon revisions. Ref: https://lists.openwrt.org/pipermail/openwrt-devel/2017-November/009882.html Ref: https://forum.openwrt.org/t/mtk-soc-eth-watchdog-timeout-after-r11573/50000/12 Suggested-by: Felix Fietkau <nbd@nbd.name> Reported-by: Rosen Penev <rosenp@gmail.com> Signed-off-by: Petr Štetiar <ynezz@true.cz>
ramips: apply LED_POLARITY rt3050-esw on MT7628AN/MT7688 The device tree property "mediatek,led_polarity" is ignored for MT7628AN and MT7688. According to the datasheet both SoCs have the matching register. Therefore the property should be applied on these two devices as well. Signed-off-by: Maximilian Pachl <m@ximilian.info> Reviewed-by: Sungbo Eo <mans0n@gorani.run> Tested-by: Sungbo Eo <mans0n@gorani.run>
ramips: add MT7530 switch port-mirroring support Compile & run tested on MT7620, MT7621 Signed-off-by: Deng Qingfang <dengqf6@mail2.sysu.edu.cn> [Tested on Phicomm PSG1218 rev.A, MediaTek MT7620A ver:2 eco:6] Tested-by: MingHao Chen <cmheia@email.com>
ramips: mtk-mmc: mt76x8: check ESD_MODE before applying AGPIO_CFG Since mt76x8an ver1 eco2, SDXC pins can be switched to the following pinmap: sd_d1 -> PAD_I2S_SDI sd_d0 -> PAD_I2S_WS sd_cmd -> PAD_I2S_CLK sd_d3 -> PAD_I2C_SCLK sd_d2 -> PAD_I2C_SD sd_clk -> PAD_GPIO0 sd_wp -> PAD_TXD1 sd_cd -> PAD_RXD1 To use this pinmap, one would need to set ESD_MODE bit (bit 15) to 1 in GPIO1_MODE and switch other used pads into GPIO mode. In this mode, we don't need to switch ethernet pins to digital pad. Check ESD_MODE bit before applying AGPIO_CFG and use rt_sysc_m32 to set it. Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
ramips: mt7620: add EPHY base mdio address changing possibility In some boards is requred to change the ephy mdio base address. This patch add of property "mediatek,ephy-base-address" in gsw part, which allows to change ephy base address. Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com> [fixed indentation in header file] Signed-off-by: Petr Štetiar <ynezz@true.cz>
ramips: mt7620: fix external PHY autopolling The port initialisation is based on assumption that phy address and port number is the same. SoC allow different numbers and some board have it. Use phy address instead the port number to make sure that correct addresses are polled. In situation when only one PHY with address 0x0 is conected to port 4, autopolling is broken. This patch make autopolling correct when port number and phy address are different. Signed-off-by: Pawel Dembicki <paweldembicki@gmail.com>
ramips: handle mdio address and switch port seperate The phy handling code forces a phy mdio address and the switch port to which a phy is attached to be the same. Albeit such a configuration is used for most boards, it isn't for all. Pass the switch port number to the ethernet phy connect functions, to ensure the correct list entry is edited and not the list entry that matches th phys mdio address. Use the mdio address with mdiobus_get_phy instead of the port number, to make sure the expected ethernet phy gets connected. Signed-off-by: Mathias Kresin <dev@kresin.me>
ramips: ignore already handled ethernet phys The whole logic in fe_phy_connect() is based on the asumption that mdio address and switch port id are equal. Albeit it is true for most boards, it doesn't is for all. It isn't yet clear which subtargets/boards require the devicetree less ethernet phy handling. Hence change the code in a way that it doesn't touch ethernet phys which were early attached and are already handled. Signed-off-by: Mathias Kresin <dev@kresin.me>
ramips: add support for Edimax EW-7476RPC / EW-7478AC SoC: MediaTek MT7620a @ 580MHz RAM: 64M (Winbond W9751G6KB-25) FLASH: 8MB (Macronix) WiFi: SoC-integrated: MediaTek MT7620a bgn WiFi: MediaTek MT7612EN nac GbE: 1x (RTL8211E) BTN: WPS - RFKILL/RF 50%/RF 100% toggle LED: - Wifi 5g (blue) - Wifi 2g (blue) - Crossband (green) - Power (green) - WPS (green) - LAN (Green) UART: UART is present as Pads with throughholes on the PCB. They are located next to the switch for the wifi configuration 3.3V - RX - GND - TX / 57600-8N1 3.3V is the square pad Installation ------------ Update the factory image via the web-interfaces (by default: 192.168.9.2/24). http://192.168.9.2/index.asp ramips: add Edimax EW-7478AC SoC: MediaTek MT7620a @ 580MHz RAM: 64M (Winbond W9751G6KB-25) FLASH: 8MB (Macronix) WiFi: SoC-integrated: MediaTek MT7620a bgn WiFi: MediaTek MT7612EN nac GbE: 1x (RTL8211E) BTN: WPS - RFKILL/RF 50%/RF 100% toggle LED: - Wifi 5g (blue) - Wifi 2g (blue) - Crossband (green) - Power (green) - WPS (green) - LAN (Green) UART: UART is present as Pads with throughholes on the PCB. They are located next to the switch for the wifi configuration 3.3V - RX - GND - TX / 57600-8N1 3.3V is the square pad Installation ------------ Update the factory image via the web-interfaces (by default: http://edimaxext.setup) Or push wpa button on power on and send firmware via tftp to 192.168.1.6 The EW-7478AC is identical to the EW-7476RPC, except instead of 2 internal antennas it has 2 external ones. Signed-off-by: Birger Koblitz <mail@birger-koblitz.de> [merge conflict in 01_leds] Signed-off-by: Petr Štetiar <ynezz@true.cz>
ramips: ethernet: remove unused SIOCETHTOOL ioctl handling This ioctl is currently routed through generic interface code. dev_ioctl dev_ethtool __ethtool_get_link_ksettings phy_ethtool_ioctl Cc: Felix Fietkau <nbd@nbd.name> Cc: John Crispin <john@phrozen.org> Signed-off-by: Petr Štetiar <ynezz@true.cz>
ramips: implement vlan rx offload on MT7621 Avoids the overhead of software VLAN untagging in the network stack Signed-off-by: Felix Fietkau <nbd@nbd.name>
ramips: fix two-way hash and auto ageout on MT7621 Current code directly writes the FOE entry to hash_val+1 position when hash collision occurs. However, it is found that this behavior will cause the cache and the hardware FOE table to be inconsistent. For example, there are three flows, and their hashed values are all equal to 100. The first flow is written to the position of 100. The second flow is written to the position of 100+1. Then, the logic of the current code will also write the third flow to 100+1. At this time, the cache has flow 1 and 2; and the hardware FOE table has flow 1 and 3, where these two parts store different contents. So it is necessary to check whether the hash_val+1 is also occupied before writing. If hash_val+1 is also occupied, we won’t bind th third flow to the FOE table. Addition to that, we also cancel the processing of foe_entry removal because the hardware has auto age-out ability. The hardware will periodically iterate through the FOE table to find out the time-out entry and set it as INVALID. Signed-off-by: HsiuWen Yen <y.hsiuwen@gmail.com>