ee02c34722a7514d56d950f502a508f57c10cdfd
[openwrt/staging/mkresin.git] / openwrt / target / linux / aruba-2.6 / patches / 000-aruba.patch
1 diff -Nur linux-2.6.16/arch/mips/aruba/Makefile linux-2.6.16-owrt/arch/mips/aruba/Makefile
2 --- linux-2.6.16/arch/mips/aruba/Makefile 1970-01-01 01:00:00.000000000 +0100
3 +++ linux-2.6.16-owrt/arch/mips/aruba/Makefile 2006-03-20 14:25:10.000000000 +0100
4 @@ -0,0 +1,49 @@
5 +###############################################################################
6 +#
7 +# BRIEF MODULE DESCRIPTION
8 +# Makefile for IDT EB434 BSP
9 +#
10 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
11 +#
12 +# This program is free software; you can redistribute it and/or modify it
13 +# under the terms of the GNU General Public License as published by the
14 +# Free Software Foundation; either version 2 of the License, or (at your
15 +# option) any later version.
16 +#
17 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 +#
28 +# You should have received a copy of the GNU General Public License along
29 +# with this program; if not, write to the Free Software Foundation, Inc.,
30 +# 675 Mass Ave, Cambridge, MA 02139, USA.
31 +#
32 +#
33 +###############################################################################
34 +# May 2004 rkt, neb
35 +#
36 +# Initial Release
37 +#
38 +#
39 +#
40 +###############################################################################
41 +
42 +
43 +# .S.s:
44 +# $(CPP) $(CFLAGS) $< -o $*.s
45 +# .S.o:
46 +# $(CC) $(CFLAGS) -c $< -o $*.o
47 +
48 +obj-y := prom.o setup.o idtIRQ.o irq.o time.o flash_lock.o
49 +obj-$(CONFIG_SERIAL_8250) += serial.o
50 +
51 +subdir-y += nvram
52 +obj-y += nvram/built-in.o
53 +
54 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/Makefile linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile
55 --- linux-2.6.16/arch/mips/aruba/nvram/Makefile 1970-01-01 01:00:00.000000000 +0100
56 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/Makefile 2006-03-20 14:25:10.000000000 +0100
57 @@ -0,0 +1,46 @@
58 +###############################################################################
59 +#
60 +# BRIEF MODULE DESCRIPTION
61 +# Makefile for IDT EB434 nvram access routines
62 +#
63 +# Copyright 2004 IDT Inc. (rischelp@idt.com)
64 +#
65 +# This program is free software; you can redistribute it and/or modify it
66 +# under the terms of the GNU General Public License as published by the
67 +# Free Software Foundation; either version 2 of the License, or (at your
68 +# option) any later version.
69 +#
70 +# THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
71 +# WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
72 +# MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
73 +# NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
74 +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
75 +# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
76 +# USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
77 +# ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
78 +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
79 +# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
80 +#
81 +# You should have received a copy of the GNU General Public License along
82 +# with this program; if not, write to the Free Software Foundation, Inc.,
83 +# 675 Mass Ave, Cambridge, MA 02139, USA.
84 +#
85 +#
86 +###############################################################################
87 +# May 2004 rkt, neb
88 +#
89 +# Initial Release
90 +#
91 +#
92 +#
93 +###############################################################################
94 +
95 +obj-y := nvram434.o
96 +obj-m := $(O_TARGET)
97 +
98 +
99 +
100 +
101 +
102 +
103 +
104 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.c linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c
105 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.c 1970-01-01 01:00:00.000000000 +0100
106 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.c 2006-03-20 14:25:10.000000000 +0100
107 @@ -0,0 +1,392 @@
108 +/**************************************************************************
109 + *
110 + * BRIEF MODULE DESCRIPTION
111 + * nvram interface routines.
112 + *
113 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
114 + *
115 + * This program is free software; you can redistribute it and/or modify it
116 + * under the terms of the GNU General Public License as published by the
117 + * Free Software Foundation; either version 2 of the License, or (at your
118 + * option) any later version.
119 + *
120 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
121 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
122 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
123 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
124 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
125 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
126 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
127 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
128 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
129 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
130 + *
131 + * You should have received a copy of the GNU General Public License along
132 + * with this program; if not, write to the Free Software Foundation, Inc.,
133 + * 675 Mass Ave, Cambridge, MA 02139, USA.
134 + *
135 + *
136 + **************************************************************************
137 + * May 2004 rkt, neb
138 + *
139 + * Initial Release
140 + *
141 + *
142 + *
143 + **************************************************************************
144 + */
145 +
146 +#include <linux/ctype.h>
147 +#include <linux/string.h>
148 +
149 +//#include <asm/ds1553rtc.h>
150 +#include "nvram434.h"
151 +#define NVRAM_BASE 0xbfff8000
152 +
153 +extern void setenv (char *e, char *v, int rewrite);
154 +extern void unsetenv (char *e);
155 +extern void mapenv (int (*func)(char *, char *));
156 +extern char *getenv (char *s);
157 +extern void purgeenv(void);
158 +
159 +static void nvram_initenv(void);
160 +
161 +static unsigned char
162 +nvram_getbyte(int offs)
163 +{
164 + return(*((unsigned char*)(NVRAM_BASE + offs)));
165 +}
166 +
167 +static void
168 +nvram_setbyte(int offs, unsigned char val)
169 +{
170 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE + offs);
171 +
172 + *nvramDataPointer = val;
173 +}
174 +
175 +/*
176 + * BigEndian!
177 + */
178 +static unsigned short
179 +nvram_getshort(int offs)
180 +{
181 + return((nvram_getbyte(offs) << 8) | nvram_getbyte(offs + 1));
182 +}
183 +
184 +static void
185 +nvram_setshort(int offs, unsigned short val)
186 +{
187 + nvram_setbyte(offs, (unsigned char)((val >> 8) & 0xff));
188 + nvram_setbyte(offs + 1, (unsigned char)(val & 0xff));
189 +}
190 +#if 0
191 +static unsigned int
192 +nvram_getint(int offs)
193 +{
194 + unsigned int val;
195 + val = nvram_getbyte(offs) << 24;
196 + val |= nvram_getbyte(offs + 1) << 16;
197 + val |= nvram_getbyte(offs + 2) << 8;
198 + val |= nvram_getbyte(offs + 3);
199 + return(val);
200 +}
201 +
202 +static void
203 +nvram_setint(int offs, unsigned int val)
204 +{
205 + nvram_setbyte(offs, val >> 24);
206 + nvram_setbyte(offs + 1, val >> 16);
207 + nvram_setbyte(offs + 2, val >> 8);
208 + nvram_setbyte(offs + 3, val);
209 +}
210 +#endif
211 +/*
212 + * calculate NVRAM checksum
213 + */
214 +static unsigned short
215 +nvram_calcsum(void)
216 +{
217 + unsigned short sum = NV_MAGIC;
218 + int i;
219 +
220 + for (i = ENV_BASE; i < ENV_TOP; i += 2)
221 + sum += nvram_getshort(i);
222 + return(sum);
223 +}
224 +
225 +/*
226 + * update the nvram checksum
227 + */
228 +static void
229 +nvram_updatesum (void)
230 +{
231 + nvram_setshort(NVOFF_CSUM, nvram_calcsum());
232 +}
233 +
234 +/*
235 + * test validity of nvram by checksumming it
236 + */
237 +static int
238 +nvram_isvalid(void)
239 +{
240 + static int is_valid;
241 +
242 + if (is_valid)
243 + return(1);
244 +
245 + if (nvram_getshort(NVOFF_MAGIC) != NV_MAGIC) {
246 + printk("nvram_isvalid FAILED\n");
247 + //nvram_initenv();
248 + }
249 + is_valid = 1;
250 + return(1);
251 +}
252 +
253 +/* return nvram address of environment string */
254 +static int
255 +nvram_matchenv(char *s)
256 +{
257 + int envsize, envp, n, i, varsize;
258 + char *var;
259 +
260 + envsize = nvram_getshort(NVOFF_ENVSIZE);
261 +
262 + if (envsize > ENV_AVAIL)
263 + return(0); /* sanity */
264 +
265 + envp = ENV_BASE;
266 +
267 + if ((n = strlen (s)) > 255)
268 + return(0);
269 +
270 + while (envsize > 0) {
271 + varsize = nvram_getbyte(envp);
272 + if (varsize == 0 || (envp + varsize) > ENV_TOP)
273 + return(0); /* sanity */
274 + for (i = envp + 1, var = s; i <= envp + n; i++, var++) {
275 + char c1 = nvram_getbyte(i);
276 + char c2 = *var;
277 + if (islower(c1))
278 + c1 = toupper(c1);
279 + if (islower(c2))
280 + c2 = toupper(c2);
281 + if (c1 != c2)
282 + break;
283 + }
284 + if (i > envp + n) { /* match so far */
285 + if (n == varsize - 1) /* match on boolean */
286 + return(envp);
287 + if (nvram_getbyte(i) == '=') /* exact match on variable */
288 + return(envp);
289 + }
290 + envsize -= varsize;
291 + envp += varsize;
292 + }
293 + return(0);
294 +}
295 +
296 +static void nvram_initenv(void)
297 +{
298 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
299 + nvram_setshort(NVOFF_ENVSIZE, 0);
300 +
301 + nvram_updatesum();
302 +}
303 +
304 +static void
305 +nvram_delenv(char *s)
306 +{
307 + int nenvp, envp, envsize, nbytes;
308 +
309 + envp = nvram_matchenv(s);
310 + if (envp == 0)
311 + return;
312 +
313 + nenvp = envp + nvram_getbyte(envp);
314 + envsize = nvram_getshort(NVOFF_ENVSIZE);
315 + nbytes = envsize - (nenvp - ENV_BASE);
316 + nvram_setshort(NVOFF_ENVSIZE, envsize - (nenvp - envp));
317 + while (nbytes--) {
318 + nvram_setbyte(envp, nvram_getbyte(nenvp));
319 + envp++;
320 + nenvp++;
321 + }
322 + nvram_updatesum();
323 +}
324 +
325 +static int
326 +nvram_setenv(char *s, char *v)
327 +{
328 + int ns, nv, total;
329 + int envp;
330 +
331 + if (!nvram_isvalid())
332 + return(-1);
333 +
334 + nvram_delenv(s);
335 + ns = strlen(s);
336 + if (ns == 0)
337 + return (-1);
338 + if (v && *v) {
339 + nv = strlen(v);
340 + total = ns + nv + 2;
341 + }
342 + else {
343 + nv = 0;
344 + total = ns + 1;
345 + }
346 + if (total > 255 || total > ENV_AVAIL - nvram_getshort(NVOFF_ENVSIZE))
347 + return(-1);
348 +
349 + envp = ENV_BASE + nvram_getshort(NVOFF_ENVSIZE);
350 +
351 + nvram_setbyte(envp, (unsigned char) total);
352 + envp++;
353 +
354 + while (ns--) {
355 + nvram_setbyte(envp, *s);
356 + envp++;
357 + s++;
358 + }
359 +
360 + if (nv) {
361 + nvram_setbyte(envp, '=');
362 + envp++;
363 + while (nv--) {
364 + nvram_setbyte(envp, *v);
365 + envp++;
366 + v++;
367 + }
368 + }
369 + nvram_setshort(NVOFF_ENVSIZE, envp-ENV_BASE);
370 + nvram_updatesum();
371 + return 0;
372 +}
373 +
374 +static char *
375 +nvram_getenv(char *s)
376 +{
377 + static char buf[256]; /* FIXME: this cannot be static */
378 + int envp, ns, nbytes, i;
379 +
380 + if (!nvram_isvalid())
381 + return "INVALID NVRAM"; //((char *)0);
382 +
383 + envp = nvram_matchenv(s);
384 + if (envp == 0)
385 + return "NOT FOUND"; //((char *)0);
386 + ns = strlen(s);
387 + if (nvram_getbyte(envp) == ns + 1) /* boolean */
388 + buf[0] = '\0';
389 + else {
390 + nbytes = nvram_getbyte(envp) - (ns + 2);
391 + envp += ns + 2;
392 + for (i = 0; i < nbytes; i++)
393 + buf[i] = nvram_getbyte(envp++);
394 + buf[i] = '\0';
395 + }
396 + return(buf);
397 +}
398 +
399 +static void
400 +nvram_unsetenv(char *s)
401 +{
402 + if (!nvram_isvalid())
403 + return;
404 +
405 + nvram_delenv(s);
406 +}
407 +
408 +/*
409 + * apply func to each string in environment
410 + */
411 +static void
412 +nvram_mapenv(int (*func)(char *, char *))
413 +{
414 + int envsize, envp, n, i, seeneql;
415 + char name[256], value[256];
416 + char c, *s;
417 +
418 + if (!nvram_isvalid())
419 + return;
420 +
421 + envsize = nvram_getshort(NVOFF_ENVSIZE);
422 + envp = ENV_BASE;
423 +
424 + while (envsize > 0) {
425 + value[0] = '\0';
426 + seeneql = 0;
427 + s = name;
428 + n = nvram_getbyte(envp);
429 + for (i = envp + 1; i < envp + n; i++) {
430 + c = nvram_getbyte(i);
431 + if ((c == '=') && !seeneql) {
432 + *s = '\0';
433 + s = value;
434 + seeneql = 1;
435 + continue;
436 + }
437 + *s++ = c;
438 + }
439 + *s = '\0';
440 + (*func)(name, value);
441 + envsize -= n;
442 + envp += n;
443 + }
444 +}
445 +#if 0
446 +static unsigned int
447 +digit(char c)
448 +{
449 + if ('0' <= c && c <= '9')
450 + return (c - '0');
451 + if ('A' <= c && c <= 'Z')
452 + return (10 + c - 'A');
453 + if ('a' <= c && c <= 'z')
454 + return (10 + c - 'a');
455 + return (~0);
456 +}
457 +#endif
458 +/*
459 + * Wrappers to allow 'special' environment variables to get processed
460 + */
461 +void
462 +setenv(char *e, char *v, int rewrite)
463 +{
464 + if (nvram_getenv(e) && !rewrite)
465 + return;
466 +
467 + nvram_setenv(e, v);
468 +}
469 +
470 +char *
471 +getenv(char *e)
472 +{
473 + return(nvram_getenv(e));
474 +}
475 +
476 +void
477 +unsetenv(char *e)
478 +{
479 + nvram_unsetenv(e);
480 +}
481 +
482 +void
483 +purgeenv()
484 +{
485 + int i;
486 + unsigned char* nvramDataPointer = (unsigned char*)(NVRAM_BASE);
487 +
488 + for (i = ENV_BASE; i < ENV_TOP; i++)
489 + *nvramDataPointer++ = 0;
490 + nvram_setshort(NVOFF_MAGIC, NV_MAGIC);
491 + nvram_setshort(NVOFF_ENVSIZE, 0);
492 + nvram_setshort(NVOFF_CSUM, NV_MAGIC);
493 +}
494 +
495 +void
496 +mapenv(int (*func)(char *, char *))
497 +{
498 + nvram_mapenv(func);
499 +}
500 diff -Nur linux-2.6.16/arch/mips/aruba/nvram/nvram434.h linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h
501 --- linux-2.6.16/arch/mips/aruba/nvram/nvram434.h 1970-01-01 01:00:00.000000000 +0100
502 +++ linux-2.6.16-owrt/arch/mips/aruba/nvram/nvram434.h 2006-03-20 14:25:10.000000000 +0100
503 @@ -0,0 +1,66 @@
504 +/**************************************************************************
505 + *
506 + * BRIEF MODULE DESCRIPTION
507 + * nvram definitions.
508 + *
509 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
510 + *
511 + * This program is free software; you can redistribute it and/or modify it
512 + * under the terms of the GNU General Public License as published by the
513 + * Free Software Foundation; either version 2 of the License, or (at your
514 + * option) any later version.
515 + *
516 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
517 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
518 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
519 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
520 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
521 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
522 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
523 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
524 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
525 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
526 + *
527 + * You should have received a copy of the GNU General Public License along
528 + * with this program; if not, write to the Free Software Foundation, Inc.,
529 + * 675 Mass Ave, Cambridge, MA 02139, USA.
530 + *
531 + *
532 + **************************************************************************
533 + * May 2004 rkt, neb
534 + *
535 + * Initial Release
536 + *
537 + *
538 + *
539 + **************************************************************************
540 + */
541 +
542 +
543 +#ifndef _NVRAM_
544 +#define _NVRAM_
545 +#define NVOFFSET 0 /* use all of NVRAM */
546 +
547 +/* Offsets to reserved locations */
548 + /* size description */
549 +#define NVOFF_MAGIC (NVOFFSET + 0) /* 2 magic value */
550 +#define NVOFF_CSUM (NVOFFSET + 2) /* 2 NVRAM environment checksum */
551 +#define NVOFF_ENVSIZE (NVOFFSET + 4) /* 2 size of 'environment' */
552 +#define NVOFF_TEST (NVOFFSET + 5) /* 1 cold start test byte */
553 +#define NVOFF_ETHADDR (NVOFFSET + 6) /* 6 decoded ethernet address */
554 +#define NVOFF_UNUSED (NVOFFSET + 12) /* 0 current end of table */
555 +
556 +#define NV_MAGIC 0xdeaf /* nvram magic number */
557 +#define NV_RESERVED 6 /* number of reserved bytes */
558 +
559 +#undef NVOFF_ETHADDR
560 +#define NVOFF_ETHADDR (NVOFFSET + NV_RESERVED - 6)
561 +
562 +/* number of bytes available for environment */
563 +#define ENV_BASE (NVOFFSET + NV_RESERVED)
564 +#define ENV_TOP 0x2000
565 +#define ENV_AVAIL (ENV_TOP - ENV_BASE)
566 +
567 +#endif /* _NVRAM_ */
568 +
569 +
570 diff -Nur linux-2.6.16/arch/mips/aruba/prom.c linux-2.6.16-owrt/arch/mips/aruba/prom.c
571 --- linux-2.6.16/arch/mips/aruba/prom.c 1970-01-01 01:00:00.000000000 +0100
572 +++ linux-2.6.16-owrt/arch/mips/aruba/prom.c 2006-03-20 14:25:10.000000000 +0100
573 @@ -0,0 +1,111 @@
574 +/**************************************************************************
575 + *
576 + * BRIEF MODULE DESCRIPTION
577 + * prom interface routines
578 + *
579 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
580 + *
581 + * This program is free software; you can redistribute it and/or modify it
582 + * under the terms of the GNU General Public License as published by the
583 + * Free Software Foundation; either version 2 of the License, or (at your
584 + * option) any later version.
585 + *
586 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
587 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
588 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
589 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
590 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
591 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
592 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
593 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
594 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
595 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
596 + *
597 + * You should have received a copy of the GNU General Public License along
598 + * with this program; if not, write to the Free Software Foundation, Inc.,
599 + * 675 Mass Ave, Cambridge, MA 02139, USA.
600 + *
601 + *
602 + **************************************************************************
603 + * May 2004 rkt, neb
604 + *
605 + * Initial Release
606 + *
607 + *
608 + *
609 + **************************************************************************
610 + */
611 +
612 +#include <linux/config.h>
613 +#include <linux/init.h>
614 +#include <linux/mm.h>
615 +#include <linux/module.h>
616 +#include <linux/string.h>
617 +#include <linux/console.h>
618 +#include <asm/bootinfo.h>
619 +#include <linux/bootmem.h>
620 +#include <linux/ioport.h>
621 +#include <linux/serial.h>
622 +#include <linux/serialP.h>
623 +#include <asm/serial.h>
624 +#include <linux/ioport.h>
625 +
626 +unsigned int idt_cpu_freq;
627 +EXPORT_SYMBOL(idt_cpu_freq);
628 +
629 +unsigned int arch_has_pci=0;
630 +
631 +/* Kernel Boot parameters */
632 +static unsigned char bootparm[] = "console=ttyS0,9600 root=/dev/mtdblock1 rootfstype=jffs2";
633 +
634 +extern unsigned long mips_machgroup;
635 +extern unsigned long mips_machtype;
636 +
637 +extern void setup_serial_port(void);
638 +extern char * getenv(char *e);
639 +
640 +/* IDT 79EB434 memory map -- we really should be auto sizing it */
641 +#define RAM_SIZE 32*1024*1024
642 +
643 +char *__init prom_getcmdline(void)
644 +{
645 + return &(arcs_cmdline[0]);
646 +}
647 +
648 +void __init prom_init(void)
649 +{
650 + char *boardname;
651 + sprintf(arcs_cmdline, "%s", bootparm);
652 +
653 + /* set our arch type */
654 + mips_machgroup = MACH_GROUP_ARUBA;
655 + mips_machtype = MACH_ARUBA_UNKNOWN;
656 +
657 + boardname=getenv("boardname");
658 +
659 + if (!strcmp(boardname,"Muscat")) {
660 + mips_machtype = MACH_ARUBA_AP70;
661 + idt_cpu_freq = 133000000;
662 + arch_has_pci=1;
663 + } else if (!strcmp(boardname,"Mataro")) {
664 + mips_machtype = MACH_ARUBA_AP65;
665 + idt_cpu_freq = 110000000;
666 + } else if (!strcmp(boardname,"Merlot")) {
667 + mips_machtype = MACH_ARUBA_AP60;
668 + idt_cpu_freq = 90000000;
669 + }
670 +
671 + /* turn on the console */
672 + setup_serial_port();
673 +
674 + /*
675 + * give all RAM to boot allocator,
676 + * except where the kernel was loaded
677 + */
678 + add_memory_region(0,RAM_SIZE,BOOT_MEM_RAM);
679 +}
680 +
681 +void prom_free_prom_memory(void)
682 +{
683 + printk("stubbed prom_free_prom_memory()\n");
684 +}
685 diff -Nur linux-2.6.16/arch/mips/aruba/serial.c linux-2.6.16-owrt/arch/mips/aruba/serial.c
686 --- linux-2.6.16/arch/mips/aruba/serial.c 1970-01-01 01:00:00.000000000 +0100
687 +++ linux-2.6.16-owrt/arch/mips/aruba/serial.c 2006-03-20 14:25:10.000000000 +0100
688 @@ -0,0 +1,94 @@
689 +/**************************************************************************
690 + *
691 + * BRIEF MODULE DESCRIPTION
692 + * Serial port initialisation.
693 + *
694 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
695 + *
696 + * This program is free software; you can redistribute it and/or modify it
697 + * under the terms of the GNU General Public License as published by the
698 + * Free Software Foundation; either version 2 of the License, or (at your
699 + * option) any later version.
700 + *
701 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
702 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
703 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
704 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
705 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
706 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
707 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
708 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
709 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
710 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
711 + *
712 + * You should have received a copy of the GNU General Public License along
713 + * with this program; if not, write to the Free Software Foundation, Inc.,
714 + * 675 Mass Ave, Cambridge, MA 02139, USA.
715 + *
716 + *
717 + **************************************************************************
718 + * May 2004 rkt, neb
719 + *
720 + * Initial Release
721 + *
722 + *
723 + *
724 + **************************************************************************
725 + */
726 +
727 +
728 +#include <linux/config.h>
729 +#include <linux/init.h>
730 +#include <linux/sched.h>
731 +#include <linux/pci.h>
732 +#include <linux/interrupt.h>
733 +#include <linux/tty.h>
734 +#include <linux/serial.h>
735 +#include <linux/serial_core.h>
736 +
737 +#include <asm/time.h>
738 +#include <asm/cpu.h>
739 +#include <asm/bootinfo.h>
740 +#include <asm/irq.h>
741 +#include <asm/serial.h>
742 +
743 +#include <asm/idt-boards/rc32434/rc32434.h>
744 +
745 +extern int __init early_serial_setup(struct uart_port *port);
746 +
747 +#define BASE_BAUD (1843200 / 16)
748 +
749 +extern unsigned int idt_cpu_freq;
750 +
751 +extern int __init setup_serial_port(void)
752 +{
753 + static struct uart_port serial_req[2];
754 +
755 + memset(serial_req, 0, sizeof(serial_req));
756 + serial_req[0].type = PORT_16550A;
757 + serial_req[0].line = 0;
758 + serial_req[0].flags = STD_COM_FLAGS;
759 + serial_req[0].iotype = SERIAL_IO_MEM;
760 + serial_req[0].regshift = 2;
761 +
762 + switch (mips_machtype) {
763 + case MACH_ARUBA_AP70:
764 + serial_req[0].irq = 104;
765 + serial_req[0].mapbase = KSEG1ADDR(0x18058003);
766 + serial_req[0].membase = (char *) KSEG1ADDR(0x18058003);
767 + serial_req[0].uartclk = idt_cpu_freq;
768 + break;
769 + case MACH_ARUBA_AP65:
770 + case MACH_ARUBA_AP60:
771 + default:
772 + serial_req[0].irq = 12;
773 + serial_req[0].mapbase = KSEG1ADDR(0xbc000003);
774 + serial_req[0].membase = (char *) KSEG1ADDR(0xbc000003);
775 + serial_req[0].uartclk = idt_cpu_freq / 2;
776 + break;
777 + }
778 +
779 + early_serial_setup(&serial_req[0]);
780 +
781 + return(0);
782 +}
783 diff -Nur linux-2.6.16/arch/mips/aruba/setup.c linux-2.6.16-owrt/arch/mips/aruba/setup.c
784 --- linux-2.6.16/arch/mips/aruba/setup.c 1970-01-01 01:00:00.000000000 +0100
785 +++ linux-2.6.16-owrt/arch/mips/aruba/setup.c 2006-03-20 14:30:00.000000000 +0100
786 @@ -0,0 +1,125 @@
787 +/**************************************************************************
788 + *
789 + * BRIEF MODULE DESCRIPTION
790 + * setup routines for IDT EB434 boards
791 + *
792 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
793 + *
794 + * This program is free software; you can redistribute it and/or modify it
795 + * under the terms of the GNU General Public License as published by the
796 + * Free Software Foundation; either version 2 of the License, or (at your
797 + * option) any later version.
798 + *
799 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
800 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
801 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
802 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
803 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
804 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
805 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
806 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
807 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
808 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
809 + *
810 + * You should have received a copy of the GNU General Public License along
811 + * with this program; if not, write to the Free Software Foundation, Inc.,
812 + * 675 Mass Ave, Cambridge, MA 02139, USA.
813 + *
814 + *
815 + **************************************************************************
816 + * May 2004 rkt, neb
817 + *
818 + * Initial Release
819 + *
820 + *
821 + *
822 + **************************************************************************
823 + */
824 +
825 +#include <linux/init.h>
826 +#include <linux/module.h>
827 +#include <linux/mm.h>
828 +#include <linux/sched.h>
829 +#include <linux/irq.h>
830 +#include <asm/bootinfo.h>
831 +#include <asm/io.h>
832 +#include <linux/ioport.h>
833 +#include <asm/mipsregs.h>
834 +#include <asm/pgtable.h>
835 +#include <asm/reboot.h>
836 +#include <asm/addrspace.h> /* for KSEG1ADDR() */
837 +#include <asm/idt-boards/rc32434/rc32434.h>
838 +#include <linux/pm.h>
839 +
840 +extern char *__init prom_getcmdline(void);
841 +
842 +extern void (*board_time_init) (void);
843 +extern void (*board_timer_setup) (struct irqaction * irq);
844 +extern void aruba_time_init(void);
845 +extern void aruba_timer_setup(struct irqaction *irq);
846 +extern void aruba_reset(void);
847 +
848 +#define epldMask ((volatile unsigned char *)0xB900000d)
849 +
850 +static void aruba_machine_restart(char *command)
851 +{
852 + switch (mips_machtype) {
853 + case MACH_ARUBA_AP70:
854 + *(volatile u32 *)KSEG1ADDR(0x18008000) = 0x80000001;
855 + break;
856 + case MACH_ARUBA_AP65:
857 + case MACH_ARUBA_AP60:
858 + default:
859 + /* Reset*/
860 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x00080350; // reset everything in sight
861 + udelay(100);
862 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0; // reset everything in sight
863 + udelay(100);
864 + *((volatile u32 *)KSEG1ADDR(0x1c003020)) = 0x3; // cold reset the cpu & system
865 + break;
866 + }
867 +}
868 +
869 +static void aruba_machine_halt(void)
870 +{
871 + for (;;) continue;
872 +}
873 +
874 +extern char * getenv(char *e);
875 +extern void unlock_ap60_70_flash(void);
876 +
877 +void __init plat_setup(void)
878 +{
879 + board_time_init = aruba_time_init;
880 +
881 + board_timer_setup = aruba_timer_setup;
882 +
883 + _machine_restart = aruba_machine_restart;
884 + _machine_halt = aruba_machine_halt;
885 + pm_power_off = aruba_machine_halt;
886 +
887 + set_io_port_base(KSEG1);
888 +
889 + /* Enable PCI interrupts in EPLD Mask register */
890 + *epldMask = 0x0;
891 + *(epldMask + 1) = 0x0;
892 +
893 + write_c0_wired(0);
894 + unlock_ap60_70_flash();
895 +
896 + printk("BOARD - %s\n",getenv("boardname"));
897 +
898 + return 0;
899 +}
900 +
901 +int page_is_ram(unsigned long pagenr)
902 +{
903 + return 1;
904 +}
905 +
906 +const char *get_system_type(void)
907 +{
908 + return "MIPS IDT32434 - ARUBA";
909 +}
910 +
911 +EXPORT_SYMBOL(get_system_type);
912 diff -Nur linux-2.6.16/arch/mips/aruba/time.c linux-2.6.16-owrt/arch/mips/aruba/time.c
913 --- linux-2.6.16/arch/mips/aruba/time.c 1970-01-01 01:00:00.000000000 +0100
914 +++ linux-2.6.16-owrt/arch/mips/aruba/time.c 2006-03-20 14:25:10.000000000 +0100
915 @@ -0,0 +1,108 @@
916 +/**************************************************************************
917 + *
918 + * BRIEF MODULE DESCRIPTION
919 + * timer routines for IDT EB434 boards
920 + *
921 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
922 + *
923 + * This program is free software; you can redistribute it and/or modify it
924 + * under the terms of the GNU General Public License as published by the
925 + * Free Software Foundation; either version 2 of the License, or (at your
926 + * option) any later version.
927 + *
928 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
929 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
930 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
931 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
932 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
933 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
934 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
935 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
936 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
937 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
938 + *
939 + * You should have received a copy of the GNU General Public License along
940 + * with this program; if not, write to the Free Software Foundation, Inc.,
941 + * 675 Mass Ave, Cambridge, MA 02139, USA.
942 + *
943 + *
944 + **************************************************************************
945 + * May 2004 rkt, neb
946 + *
947 + * Initial Release
948 + *
949 + *
950 + *
951 + **************************************************************************
952 + */
953 +
954 +#include <linux/config.h>
955 +#include <linux/init.h>
956 +#include <linux/kernel_stat.h>
957 +#include <linux/sched.h>
958 +#include <linux/spinlock.h>
959 +#include <linux/mc146818rtc.h>
960 +#include <linux/irq.h>
961 +#include <linux/timex.h>
962 +
963 +#include <linux/param.h>
964 +#include <asm/mipsregs.h>
965 +#include <asm/ptrace.h>
966 +#include <asm/time.h>
967 +#include <asm/hardirq.h>
968 +
969 +#include <asm/mipsregs.h>
970 +#include <asm/ptrace.h>
971 +#include <asm/debug.h>
972 +#include <asm/time.h>
973 +
974 +#include <asm/idt-boards/rc32434/rc32434.h>
975 +
976 +static unsigned long r4k_offset; /* Amount to incr compare reg each time */
977 +static unsigned long r4k_cur; /* What counter should be at next timer irq */
978 +
979 +extern unsigned int idt_cpu_freq;
980 +
981 +static unsigned long __init cal_r4koff(void)
982 +{
983 + mips_hpt_frequency = idt_cpu_freq * IDT_CLOCK_MULT / 2;
984 + return (mips_hpt_frequency / HZ);
985 +}
986 +
987 +void __init aruba_time_init(void)
988 +{
989 + unsigned int est_freq, flags;
990 + local_irq_save(flags);
991 +
992 + printk("calculating r4koff... ");
993 + r4k_offset = cal_r4koff();
994 + printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
995 +
996 + est_freq = 2 * r4k_offset * HZ;
997 + est_freq += 5000; /* round */
998 + est_freq -= est_freq % 10000;
999 + printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
1000 + (est_freq % 1000000) * 100 / 1000000);
1001 + local_irq_restore(flags);
1002 +
1003 +}
1004 +
1005 +void __init aruba_timer_setup(struct irqaction *irq)
1006 +{
1007 + /* we are using the cpu counter for timer interrupts */
1008 + setup_irq(MIPS_CPU_TIMER_IRQ, irq);
1009 +
1010 + /* to generate the first timer interrupt */
1011 + r4k_cur = (read_c0_count() + r4k_offset);
1012 + write_c0_compare(r4k_cur);
1013 +
1014 +}
1015 +
1016 +asmlinkage void aruba_timer_interrupt(int irq, struct pt_regs *regs)
1017 +{
1018 + irq_enter();
1019 + kstat_this_cpu.irqs[irq]++;
1020 +
1021 + timer_interrupt(irq, NULL, regs);
1022 + irq_exit();
1023 +}
1024 diff -Nur linux-2.6.16/arch/mips/Kconfig linux-2.6.16-owrt/arch/mips/Kconfig
1025 --- linux-2.6.16/arch/mips/Kconfig 2006-03-20 06:53:29.000000000 +0100
1026 +++ linux-2.6.16-owrt/arch/mips/Kconfig 2006-03-20 14:25:10.000000000 +0100
1027 @@ -227,6 +227,17 @@
1028 either a NEC Vr5432 or QED RM5231. Say Y here if you wish to build
1029 a kernel for this platform.
1030
1031 +config MACH_ARUBA
1032 + bool "Support for the ARUBA product line"
1033 + select DMA_NONCOHERENT
1034 + select CPU_HAS_PREFETCH
1035 + select HW_HAS_PCI
1036 + select SWAP_IO_SPACE
1037 + select SYS_SUPPORTS_32BIT_KERNEL
1038 + select SYS_HAS_CPU_MIPS32_R1
1039 + select SYS_SUPPORTS_BIG_ENDIAN
1040 +
1041 +
1042 config MACH_JAZZ
1043 bool "Support for the Jazz family of machines"
1044 select ARC
1045 diff -Nur linux-2.6.16/arch/mips/Makefile linux-2.6.16-owrt/arch/mips/Makefile
1046 --- linux-2.6.16/arch/mips/Makefile 2006-03-20 06:53:29.000000000 +0100
1047 +++ linux-2.6.16-owrt/arch/mips/Makefile 2006-03-20 14:25:10.000000000 +0100
1048 @@ -279,6 +279,14 @@
1049 #
1050
1051 #
1052 +# Aruba
1053 +#
1054 +
1055 +core-$(CONFIG_MACH_ARUBA) += arch/mips/aruba/
1056 +cflags-$(CONFIG_MACH_ARUBA) += -Iinclude/asm-mips/aruba
1057 +load-$(CONFIG_MACH_ARUBA) += 0x80100000
1058 +
1059 +#
1060 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
1061 #
1062 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
1063 diff -Nur linux-2.6.16/arch/mips/mm/tlbex.c linux-2.6.16-owrt/arch/mips/mm/tlbex.c
1064 --- linux-2.6.16/arch/mips/mm/tlbex.c 2006-03-20 06:53:29.000000000 +0100
1065 +++ linux-2.6.16-owrt/arch/mips/mm/tlbex.c 2006-03-20 14:25:10.000000000 +0100
1066 @@ -852,7 +852,6 @@
1067
1068 case CPU_R10000:
1069 case CPU_R12000:
1070 - case CPU_4KC:
1071 case CPU_SB1:
1072 case CPU_SB1A:
1073 case CPU_4KSC:
1074 @@ -880,6 +879,7 @@
1075 tlbw(p);
1076 break;
1077
1078 + case CPU_4KC:
1079 case CPU_4KEC:
1080 case CPU_24K:
1081 case CPU_34K:
1082 diff -Nur linux-2.6.16/drivers/net/Kconfig linux-2.6.16-owrt/drivers/net/Kconfig
1083 --- linux-2.6.16/drivers/net/Kconfig 2006-03-20 06:53:29.000000000 +0100
1084 +++ linux-2.6.16-owrt/drivers/net/Kconfig 2006-03-20 14:25:10.000000000 +0100
1085 @@ -187,6 +187,13 @@
1086
1087 source "drivers/net/arm/Kconfig"
1088
1089 +config IDT_RC32434_ETH
1090 + tristate "IDT RC32434 Local Ethernet support"
1091 + depends on NET_ETHERNET
1092 + help
1093 + IDT RC32434 has one local ethernet port. Say Y here to enable it.
1094 + To compile this driver as a module, choose M here.
1095 +
1096 config MACE
1097 tristate "MACE (Power Mac ethernet) support"
1098 depends on NET_ETHERNET && PPC_PMAC && PPC32
1099 diff -Nur linux-2.6.16/drivers/net/Makefile linux-2.6.16-owrt/drivers/net/Makefile
1100 --- linux-2.6.16/drivers/net/Makefile 2006-03-20 06:53:29.000000000 +0100
1101 +++ linux-2.6.16-owrt/drivers/net/Makefile 2006-03-20 14:25:10.000000000 +0100
1102 @@ -38,6 +38,7 @@
1103
1104 obj-$(CONFIG_OAKNET) += oaknet.o 8390.o
1105
1106 +obj-$(CONFIG_IDT_RC32434_ETH) += rc32434_eth.o
1107 obj-$(CONFIG_DGRS) += dgrs.o
1108 obj-$(CONFIG_VORTEX) += 3c59x.o
1109 obj-$(CONFIG_TYPHOON) += typhoon.o
1110 diff -Nur linux-2.6.16/drivers/net/natsemi.c linux-2.6.16-owrt/drivers/net/natsemi.c
1111 --- linux-2.6.16/drivers/net/natsemi.c 2006-03-20 06:53:29.000000000 +0100
1112 +++ linux-2.6.16-owrt/drivers/net/natsemi.c 2006-03-20 14:25:10.000000000 +0100
1113 @@ -771,6 +771,49 @@
1114 static int netdev_get_eeprom(struct net_device *dev, u8 *buf);
1115 static struct ethtool_ops ethtool_ops;
1116
1117 +#ifdef CONFIG_MACH_ARUBA
1118 +
1119 +#include <linux/ctype.h>
1120 +
1121 +#ifndef ERR
1122 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
1123 +#endif
1124 +
1125 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1126 +{
1127 + int i, j;
1128 + unsigned char result, value;
1129 +
1130 + for (i=0; i<6; i++) {
1131 + result = 0;
1132 + if (i != 5 && *(macstr+2) != ':') {
1133 + ERR("invalid mac address format: %d %c\n",
1134 + i, *(macstr+2));
1135 + return -EINVAL;
1136 + }
1137 + for (j=0; j<2; j++) {
1138 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1139 + toupper(*macstr)-'A'+10) < 16) {
1140 + result = result*16 + value;
1141 + macstr++;
1142 + }
1143 + else {
1144 + ERR("invalid mac address "
1145 + "character: %c\n", *macstr);
1146 + return -EINVAL;
1147 + }
1148 + }
1149 +
1150 + macstr++;
1151 + dev->dev_addr[i] = result;
1152 + }
1153 +
1154 + dev->dev_addr[5]++;
1155 + return 0;
1156 +}
1157 +
1158 +#endif
1159 +
1160 static inline void __iomem *ns_ioaddr(struct net_device *dev)
1161 {
1162 return (void __iomem *) dev->base_addr;
1163 @@ -859,6 +902,7 @@
1164 goto err_ioremap;
1165 }
1166
1167 +#ifndef CONFIG_MACH_ARUBA
1168 /* Work around the dropped serial bit. */
1169 prev_eedata = eeprom_read(ioaddr, 6);
1170 for (i = 0; i < 3; i++) {
1171 @@ -867,6 +911,19 @@
1172 dev->dev_addr[i*2+1] = eedata >> 7;
1173 prev_eedata = eedata;
1174 }
1175 +#else
1176 + {
1177 + char mac[32];
1178 + unsigned char def_mac[6] = {00, 0x0b, 0x86, 0xba, 0xdb, 0xad};
1179 + extern char *getenv(char *e);
1180 + memset(mac, 0, 32);
1181 + memcpy(mac, getenv("ethaddr"), 17);
1182 + if (parse_mac_addr(dev, mac)){
1183 + printk("%s: MAC address not found\n", __func__);
1184 + memcpy(dev->dev_addr, def_mac, 6);
1185 + }
1186 + }
1187 +#endif
1188
1189 dev->base_addr = (unsigned long __force) ioaddr;
1190 dev->irq = irq;
1191 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.c linux-2.6.16-owrt/drivers/net/rc32434_eth.c
1192 --- linux-2.6.16/drivers/net/rc32434_eth.c 1970-01-01 01:00:00.000000000 +0100
1193 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.c 2006-03-20 14:25:10.000000000 +0100
1194 @@ -0,0 +1,1268 @@
1195 +/**************************************************************************
1196 + *
1197 + * BRIEF MODULE DESCRIPTION
1198 + * Driver for the IDT RC32434 on-chip ethernet controller.
1199 + *
1200 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
1201 + *
1202 + * This program is free software; you can redistribute it and/or modify it
1203 + * under the terms of the GNU General Public License as published by the
1204 + * Free Software Foundation; either version 2 of the License, or (at your
1205 + * option) any later version.
1206 + *
1207 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1208 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1209 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1210 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1211 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1212 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1213 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1214 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1215 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1216 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1217 + *
1218 + * You should have received a copy of the GNU General Public License along
1219 + * with this program; if not, write to the Free Software Foundation, Inc.,
1220 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1221 + *
1222 + *
1223 + **************************************************************************
1224 + * May 2004 rkt, neb
1225 + *
1226 + * Based on the driver developed by B. Maruthanayakam, H. Kou and others.
1227 + *
1228 + * Aug 2004 Sadik
1229 + *
1230 + * Added NAPI
1231 + *
1232 + **************************************************************************
1233 + */
1234 +
1235 +#include <linux/config.h>
1236 +#include <linux/module.h>
1237 +#include <linux/kernel.h>
1238 +#include <linux/moduleparam.h>
1239 +#include <linux/sched.h>
1240 +#include <linux/ctype.h>
1241 +#include <linux/types.h>
1242 +#include <linux/fcntl.h>
1243 +#include <linux/interrupt.h>
1244 +#include <linux/ptrace.h>
1245 +#include <linux/init.h>
1246 +#include <linux/ioport.h>
1247 +#include <linux/proc_fs.h>
1248 +#include <linux/in.h>
1249 +#include <linux/slab.h>
1250 +#include <linux/string.h>
1251 +#include <linux/delay.h>
1252 +#include <linux/netdevice.h>
1253 +#include <linux/etherdevice.h>
1254 +#include <linux/skbuff.h>
1255 +#include <linux/errno.h>
1256 +#include <asm/bootinfo.h>
1257 +#include <asm/system.h>
1258 +#include <asm/bitops.h>
1259 +#include <asm/pgtable.h>
1260 +#include <asm/segment.h>
1261 +#include <asm/io.h>
1262 +#include <asm/dma.h>
1263 +
1264 +#include "rc32434_eth.h"
1265 +
1266 +#define DRIVER_VERSION "(mar2904)"
1267 +
1268 +#define DRIVER_NAME "rc32434 Ethernet driver. " DRIVER_VERSION
1269 +
1270 +
1271 +#define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
1272 + ((dev)->dev_addr[1]))
1273 +#define STATION_ADDRESS_LOW(dev) (((dev)->dev_addr[2] << 24) | \
1274 + ((dev)->dev_addr[3] << 16) | \
1275 + ((dev)->dev_addr[4] << 8) | \
1276 + ((dev)->dev_addr[5]))
1277 +
1278 +#define MII_CLOCK 1250000 /* no more than 2.5MHz */
1279 +static char mac0[18] = "08:00:06:05:40:01";
1280 +
1281 +MODULE_PARM(mac0, "c18");
1282 +MODULE_PARM_DESC(mac0, "MAC address for RC32434 ethernet0");
1283 +
1284 +static struct rc32434_if_t {
1285 + char *name;
1286 + struct net_device *dev;
1287 + char* mac_str;
1288 + int weight;
1289 + u32 iobase;
1290 + u32 rxdmabase;
1291 + u32 txdmabase;
1292 + int rx_dma_irq;
1293 + int tx_dma_irq;
1294 + int rx_ovr_irq;
1295 + int tx_und_irq;
1296 +} rc32434_iflist[] =
1297 +{
1298 + {
1299 + "rc32434_eth0", NULL, mac0,
1300 + 64,
1301 + ETH0_PhysicalAddress,
1302 + ETH0_RX_DMA_ADDR,
1303 + ETH0_TX_DMA_ADDR,
1304 + ETH0_DMA_RX_IRQ,
1305 + ETH0_DMA_TX_IRQ,
1306 + ETH0_RX_OVR_IRQ,
1307 + ETH0_TX_UND_IRQ
1308 + }
1309 +};
1310 +
1311 +
1312 +static int parse_mac_addr(struct net_device *dev, char* macstr)
1313 +{
1314 + int i, j;
1315 + unsigned char result, value;
1316 +
1317 + for (i=0; i<6; i++) {
1318 + result = 0;
1319 + if (i != 5 && *(macstr+2) != ':') {
1320 + ERR("invalid mac address format: %d %c\n",
1321 + i, *(macstr+2));
1322 + return -EINVAL;
1323 + }
1324 + for (j=0; j<2; j++) {
1325 + if (isxdigit(*macstr) && (value = isdigit(*macstr) ? *macstr-'0' :
1326 + toupper(*macstr)-'A'+10) < 16) {
1327 + result = result*16 + value;
1328 + macstr++;
1329 + }
1330 + else {
1331 + ERR("invalid mac address "
1332 + "character: %c\n", *macstr);
1333 + return -EINVAL;
1334 + }
1335 + }
1336 +
1337 + macstr++;
1338 + dev->dev_addr[i] = result;
1339 + }
1340 +
1341 + return 0;
1342 +}
1343 +
1344 +
1345 +
1346 +static inline void rc32434_abort_tx(struct net_device *dev)
1347 +{
1348 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1349 + rc32434_abort_dma(dev, lp->tx_dma_regs);
1350 +
1351 +}
1352 +
1353 +static inline void rc32434_abort_rx(struct net_device *dev)
1354 +{
1355 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1356 + rc32434_abort_dma(dev, lp->rx_dma_regs);
1357 +
1358 +}
1359 +
1360 +static inline void rc32434_start_tx(struct rc32434_local *lp, volatile DMAD_t td)
1361 +{
1362 + rc32434_start_dma(lp->tx_dma_regs, CPHYSADDR(td));
1363 +}
1364 +
1365 +static inline void rc32434_start_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1366 +{
1367 + rc32434_start_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1368 +}
1369 +
1370 +static inline void rc32434_chain_tx(struct rc32434_local *lp, volatile DMAD_t td)
1371 +{
1372 + rc32434_chain_dma(lp->tx_dma_regs, CPHYSADDR(td));
1373 +}
1374 +
1375 +static inline void rc32434_chain_rx(struct rc32434_local *lp, volatile DMAD_t rd)
1376 +{
1377 + rc32434_chain_dma(lp->rx_dma_regs, CPHYSADDR(rd));
1378 +}
1379 +
1380 +#ifdef RC32434_PROC_DEBUG
1381 +static int rc32434_read_proc(char *buf, char **start, off_t fpos,
1382 + int length, int *eof, void *data)
1383 +{
1384 + struct net_device *dev = (struct net_device *)data;
1385 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1386 + int len = 0;
1387 +
1388 + /* print out header */
1389 + len += sprintf(buf + len, "\n\tRC32434 Ethernet Debug\n\n");
1390 + len += sprintf (buf + len,
1391 + "DMA halt count = %10d, DMA run count = %10d\n",
1392 + lp->dma_halt_cnt, lp->dma_run_cnt);
1393 +
1394 + if (fpos >= len) {
1395 + *start = buf;
1396 + *eof = 1;
1397 + return 0;
1398 + }
1399 + *start = buf + fpos;
1400 +
1401 + if ((len -= fpos) > length)
1402 + return length;
1403 + *eof = 1;
1404 +
1405 + return len;
1406 +
1407 +}
1408 +#endif
1409 +
1410 +
1411 +/*
1412 + * Restart the RC32434 ethernet controller.
1413 + */
1414 +static int rc32434_restart(struct net_device *dev)
1415 +{
1416 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1417 +
1418 + /*
1419 + * Disable interrupts
1420 + */
1421 + disable_irq(lp->rx_irq);
1422 + disable_irq(lp->tx_irq);
1423 +#ifdef RC32434_REVISION
1424 + disable_irq(lp->ovr_irq);
1425 +#endif
1426 + disable_irq(lp->und_irq);
1427 +
1428 + /* Mask F E bit in Tx DMA */
1429 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) | DMASM_f_m | DMASM_e_m, &lp->tx_dma_regs->dmasm);
1430 + /* Mask D H E bit in Rx DMA */
1431 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) | DMASM_d_m | DMASM_h_m | DMASM_e_m, &lp->rx_dma_regs->dmasm);
1432 +
1433 + rc32434_init(dev);
1434 + rc32434_multicast_list(dev);
1435 +
1436 + enable_irq(lp->und_irq);
1437 +#ifdef RC32434_REVISION
1438 + enable_irq(lp->ovr_irq);
1439 +#endif
1440 + enable_irq(lp->tx_irq);
1441 + enable_irq(lp->rx_irq);
1442 +
1443 + return 0;
1444 +}
1445 +
1446 +int rc32434_init_module(void)
1447 +{
1448 +#ifdef CONFIG_MACH_ARUBA
1449 + if (mips_machtype != MACH_ARUBA_AP70)
1450 + return 1;
1451 +#endif
1452 +
1453 + printk(KERN_INFO DRIVER_NAME " \n");
1454 + return rc32434_probe(0);
1455 +}
1456 +
1457 +static int rc32434_probe(int port_num)
1458 +{
1459 + struct rc32434_if_t *bif = &rc32434_iflist[port_num];
1460 + struct rc32434_local *lp = NULL;
1461 + struct net_device *dev = NULL;
1462 + int i, retval,err;
1463 +
1464 + dev = alloc_etherdev(sizeof(struct rc32434_local));
1465 + if(!dev) {
1466 + ERR("rc32434_eth: alloc_etherdev failed\n");
1467 + return -1;
1468 + }
1469 +
1470 + SET_MODULE_OWNER(dev);
1471 + bif->dev = dev;
1472 +
1473 +#ifdef CONFIG_MACH_ARUBA
1474 + {
1475 + extern char * getenv(char *e);
1476 + memcpy(bif->mac_str, getenv("ethaddr"), 17);
1477 + }
1478 +#endif
1479 +
1480 + printk("mac: %s\n", bif->mac_str);
1481 + if ((retval = parse_mac_addr(dev, bif->mac_str))) {
1482 + ERR("MAC address parse failed\n");
1483 + free_netdev(dev);
1484 + return -1;
1485 + }
1486 +
1487 +
1488 + /* Initialize the device structure. */
1489 + if (dev->priv == NULL) {
1490 + lp = (struct rc32434_local *)kmalloc(sizeof(*lp), GFP_KERNEL);
1491 + memset(lp, 0, sizeof(struct rc32434_local));
1492 + }
1493 + else {
1494 + lp = (struct rc32434_local *)dev->priv;
1495 + }
1496 +
1497 + lp->rx_irq = bif->rx_dma_irq;
1498 + lp->tx_irq = bif->tx_dma_irq;
1499 + lp->ovr_irq = bif->rx_ovr_irq;
1500 + lp->und_irq = bif->tx_und_irq;
1501 +
1502 + lp->eth_regs = ioremap_nocache(bif->iobase, sizeof(*lp->eth_regs));
1503 +
1504 + if (!lp->eth_regs) {
1505 + ERR("Can't remap eth registers\n");
1506 + retval = -ENXIO;
1507 + goto probe_err_out;
1508 + }
1509 +
1510 + lp->rx_dma_regs = ioremap_nocache(bif->rxdmabase, sizeof(struct DMA_Chan_s));
1511 +
1512 + if (!lp->rx_dma_regs) {
1513 + ERR("Can't remap Rx DMA registers\n");
1514 + retval = -ENXIO;
1515 + goto probe_err_out;
1516 + }
1517 + lp->tx_dma_regs = ioremap_nocache(bif->txdmabase,sizeof(struct DMA_Chan_s));
1518 +
1519 + if (!lp->tx_dma_regs) {
1520 + ERR("Can't remap Tx DMA registers\n");
1521 + retval = -ENXIO;
1522 + goto probe_err_out;
1523 + }
1524 +
1525 +#ifdef RC32434_PROC_DEBUG
1526 + lp->ps = create_proc_read_entry (bif->name, 0, proc_net,
1527 + rc32434_read_proc, dev);
1528 +#endif
1529 +
1530 + lp->td_ring = (DMAD_t)kmalloc(TD_RING_SIZE + RD_RING_SIZE, GFP_KERNEL);
1531 + if (!lp->td_ring) {
1532 + ERR("Can't allocate descriptors\n");
1533 + retval = -ENOMEM;
1534 + goto probe_err_out;
1535 + }
1536 +
1537 + dma_cache_inv((unsigned long)(lp->td_ring), TD_RING_SIZE + RD_RING_SIZE);
1538 +
1539 + /* now convert TD_RING pointer to KSEG1 */
1540 + lp->td_ring = (DMAD_t )KSEG1ADDR(lp->td_ring);
1541 + lp->rd_ring = &lp->td_ring[RC32434_NUM_TDS];
1542 +
1543 +
1544 + spin_lock_init(&lp->lock);
1545 +
1546 + dev->base_addr = bif->iobase;
1547 + /* just use the rx dma irq */
1548 + dev->irq = bif->rx_dma_irq;
1549 +
1550 + dev->priv = lp;
1551 +
1552 + dev->open = rc32434_open;
1553 + dev->stop = rc32434_close;
1554 + dev->hard_start_xmit = rc32434_send_packet;
1555 + dev->get_stats = rc32434_get_stats;
1556 + dev->set_multicast_list = &rc32434_multicast_list;
1557 + dev->tx_timeout = rc32434_tx_timeout;
1558 + dev->watchdog_timeo = RC32434_TX_TIMEOUT;
1559 +
1560 +#ifdef CONFIG_IDT_USE_NAPI
1561 + dev->poll = rc32434_poll;
1562 + dev->weight = bif->weight;
1563 + printk("Using NAPI with weight %d\n",dev->weight);
1564 +#else
1565 + lp->rx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1566 + tasklet_init(lp->rx_tasklet, rc32434_rx_tasklet, (unsigned long)dev);
1567 +#endif
1568 + lp->tx_tasklet = kmalloc(sizeof(struct tasklet_struct), GFP_KERNEL);
1569 + tasklet_init(lp->tx_tasklet, rc32434_tx_tasklet, (unsigned long)dev);
1570 +
1571 + if ((err = register_netdev(dev))) {
1572 + printk(KERN_ERR "rc32434 ethernet. Cannot register net device %d\n", err);
1573 + free_netdev(dev);
1574 + retval = -EINVAL;
1575 + goto probe_err_out;
1576 + }
1577 +
1578 + INFO("Rx IRQ %d, Tx IRQ %d, ", bif->rx_dma_irq, bif->tx_dma_irq);
1579 + for (i = 0; i < 6; i++) {
1580 + printk("%2.2x", dev->dev_addr[i]);
1581 + if (i<5)
1582 + printk(":");
1583 + }
1584 + printk("\n");
1585 +
1586 + return 0;
1587 +
1588 + probe_err_out:
1589 + rc32434_cleanup_module();
1590 + ERR(" failed. Returns %d\n", retval);
1591 + return retval;
1592 +
1593 +}
1594 +
1595 +
1596 +static void rc32434_cleanup_module(void)
1597 +{
1598 + int i;
1599 +
1600 + for (i = 0; rc32434_iflist[i].iobase; i++) {
1601 + struct rc32434_if_t * bif = &rc32434_iflist[i];
1602 + if (bif->dev != NULL) {
1603 + struct rc32434_local *lp = (struct rc32434_local *)bif->dev->priv;
1604 + if (lp != NULL) {
1605 + if (lp->eth_regs)
1606 + iounmap((void*)lp->eth_regs);
1607 + if (lp->rx_dma_regs)
1608 + iounmap((void*)lp->rx_dma_regs);
1609 + if (lp->tx_dma_regs)
1610 + iounmap((void*)lp->tx_dma_regs);
1611 + if (lp->td_ring)
1612 + kfree((void*)KSEG0ADDR(lp->td_ring));
1613 +
1614 +#ifdef RC32434_PROC_DEBUG
1615 + if (lp->ps) {
1616 + remove_proc_entry(bif->name, proc_net);
1617 + }
1618 +#endif
1619 + kfree(lp);
1620 + }
1621 +
1622 + unregister_netdev(bif->dev);
1623 + free_netdev(bif->dev);
1624 + kfree(bif->dev);
1625 + }
1626 + }
1627 +}
1628 +
1629 +
1630 +
1631 +static int rc32434_open(struct net_device *dev)
1632 +{
1633 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1634 +
1635 + /* Initialize */
1636 + if (rc32434_init(dev)) {
1637 + ERR("Error: cannot open the Ethernet device\n");
1638 + return -EAGAIN;
1639 + }
1640 +
1641 + /* Install the interrupt handler that handles the Done Finished Ovr and Und Events */
1642 + if (request_irq(lp->rx_irq, &rc32434_rx_dma_interrupt,
1643 + SA_SHIRQ | SA_INTERRUPT,
1644 + "rc32434 ethernet Rx", dev)) {
1645 + ERR(": unable to get Rx DMA IRQ %d\n",
1646 + lp->rx_irq);
1647 + return -EAGAIN;
1648 + }
1649 + if (request_irq(lp->tx_irq, &rc32434_tx_dma_interrupt,
1650 + SA_SHIRQ | SA_INTERRUPT,
1651 + "rc32434 ethernet Tx", dev)) {
1652 + ERR(": unable to get Tx DMA IRQ %d\n",
1653 + lp->tx_irq);
1654 + free_irq(lp->rx_irq, dev);
1655 + return -EAGAIN;
1656 + }
1657 +
1658 +#ifdef RC32434_REVISION
1659 + /* Install handler for overrun error. */
1660 + if (request_irq(lp->ovr_irq, &rc32434_ovr_interrupt,
1661 + SA_SHIRQ | SA_INTERRUPT,
1662 + "Ethernet Overflow", dev)) {
1663 + ERR(": unable to get OVR IRQ %d\n",
1664 + lp->ovr_irq);
1665 + free_irq(lp->rx_irq, dev);
1666 + free_irq(lp->tx_irq, dev);
1667 + return -EAGAIN;
1668 + }
1669 +#endif
1670 +
1671 + /* Install handler for underflow error. */
1672 + if (request_irq(lp->und_irq, &rc32434_und_interrupt,
1673 + SA_SHIRQ | SA_INTERRUPT,
1674 + "Ethernet Underflow", dev)) {
1675 + ERR(": unable to get UND IRQ %d\n",
1676 + lp->und_irq);
1677 + free_irq(lp->rx_irq, dev);
1678 + free_irq(lp->tx_irq, dev);
1679 +#ifdef RC32434_REVISION
1680 + free_irq(lp->ovr_irq, dev);
1681 +#endif
1682 + return -EAGAIN;
1683 + }
1684 +
1685 +
1686 + return 0;
1687 +}
1688 +
1689 +
1690 +
1691 +
1692 +static int rc32434_close(struct net_device *dev)
1693 +{
1694 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1695 + u32 tmp;
1696 +
1697 + /* Disable interrupts */
1698 + disable_irq(lp->rx_irq);
1699 + disable_irq(lp->tx_irq);
1700 +#ifdef RC32434_REVISION
1701 + disable_irq(lp->ovr_irq);
1702 +#endif
1703 + disable_irq(lp->und_irq);
1704 +
1705 + tmp = rc32434_readl(&lp->tx_dma_regs->dmasm);
1706 + tmp = tmp | DMASM_f_m | DMASM_e_m;
1707 + rc32434_writel(tmp, &lp->tx_dma_regs->dmasm);
1708 +
1709 + tmp = rc32434_readl(&lp->rx_dma_regs->dmasm);
1710 + tmp = tmp | DMASM_d_m | DMASM_h_m | DMASM_e_m;
1711 + rc32434_writel(tmp, &lp->rx_dma_regs->dmasm);
1712 +
1713 + free_irq(lp->rx_irq, dev);
1714 + free_irq(lp->tx_irq, dev);
1715 +#ifdef RC32434_REVISION
1716 + free_irq(lp->ovr_irq, dev);
1717 +#endif
1718 + free_irq(lp->und_irq, dev);
1719 + return 0;
1720 +}
1721 +
1722 +
1723 +/* transmit packet */
1724 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev)
1725 +{
1726 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1727 + unsigned long flags;
1728 + u32 length;
1729 + DMAD_t td;
1730 +
1731 +
1732 + spin_lock_irqsave(&lp->lock, flags);
1733 +
1734 + td = &lp->td_ring[lp->tx_chain_tail];
1735 +
1736 + /* stop queue when full, drop pkts if queue already full */
1737 + if(lp->tx_count >= (RC32434_NUM_TDS - 2)) {
1738 + lp->tx_full = 1;
1739 +
1740 + if(lp->tx_count == (RC32434_NUM_TDS - 2)) {
1741 + netif_stop_queue(dev);
1742 + }
1743 + else {
1744 + lp->stats.tx_dropped++;
1745 + dev_kfree_skb_any(skb);
1746 + spin_unlock_irqrestore(&lp->lock, flags);
1747 + return 1;
1748 + }
1749 + }
1750 +
1751 + lp->tx_count ++;
1752 +
1753 + lp->tx_skb[lp->tx_chain_tail] = skb;
1754 +
1755 + length = skb->len;
1756 +
1757 + /* Setup the transmit descriptor. */
1758 + td->ca = CPHYSADDR(skb->data);
1759 +
1760 + if(rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
1761 + if( lp->tx_chain_status == empty ) {
1762 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1763 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1764 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1765 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1766 + }
1767 + else {
1768 + td->control = DMA_COUNT(length) |DMAD_cof_m|DMAD_iof_m; /* Update tail */
1769 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1770 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1771 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1772 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr)); /* Write to NDPTR */
1773 + lp->tx_chain_head = lp->tx_chain_tail; /* Move head to tail */
1774 + lp->tx_chain_status = empty;
1775 + }
1776 + }
1777 + else {
1778 + if( lp->tx_chain_status == empty ) {
1779 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1780 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1781 + lp->tx_chain_status = filled;
1782 + }
1783 + else {
1784 + td->control = DMA_COUNT(length) |DMAD_cof_m |DMAD_iof_m; /* Update tail */
1785 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].control &= ~(DMAD_cof_m); /* Link to prev */
1786 + lp->td_ring[(lp->tx_chain_tail-1)& RC32434_TDS_MASK].link = CPHYSADDR(td); /* Link to prev */
1787 + lp->tx_chain_tail = (lp->tx_chain_tail + 1) & RC32434_TDS_MASK; /* Move tail */
1788 + }
1789 + }
1790 +
1791 + dev->trans_start = jiffies;
1792 +
1793 + spin_unlock_irqrestore(&lp->lock, flags);
1794 +
1795 + return 0;
1796 +}
1797 +
1798 +
1799 +/* Ethernet MII-PHY Handler */
1800 +static void rc32434_mii_handler(unsigned long data)
1801 +{
1802 + struct net_device *dev = (struct net_device *)data;
1803 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
1804 + unsigned long flags;
1805 + unsigned long duplex_status;
1806 + int port_addr = (lp->rx_irq == 0x2c? 1:0) << 8;
1807 +
1808 + spin_lock_irqsave(&lp->lock, flags);
1809 +
1810 + /* Two ports are using the same MII, the difference is the PHY address */
1811 + rc32434_writel(0, &rc32434_eth0_regs->miimcfg);
1812 + rc32434_writel(0, &rc32434_eth0_regs->miimcmd);
1813 + rc32434_writel(port_addr |0x05, &rc32434_eth0_regs->miimaddr);
1814 + rc32434_writel(MIIMCMD_scn_m, &rc32434_eth0_regs->miimcmd);
1815 + while(rc32434_readl(&rc32434_eth0_regs->miimind) & MIIMIND_nv_m);
1816 +
1817 + ERR("irq:%x port_addr:%x RDD:%x\n",
1818 + lp->rx_irq, port_addr, rc32434_readl(&rc32434_eth0_regs->miimrdd));
1819 + duplex_status = (rc32434_readl(&rc32434_eth0_regs->miimrdd) & 0x140)? ETHMAC2_fd_m: 0;
1820 + if(duplex_status != lp->duplex_mode) {
1821 + ERR("The MII-PHY is Auto-negotiated to %s-Duplex mode for Eth-%x\n", duplex_status? "Full":"Half", lp->rx_irq == 0x2c? 1:0);
1822 + lp->duplex_mode = duplex_status;
1823 + rc32434_restart(dev);
1824 + }
1825 +
1826 + lp->mii_phy_timer.expires = jiffies + 10 * HZ;
1827 + add_timer(&lp->mii_phy_timer);
1828 +
1829 + spin_unlock_irqrestore(&lp->lock, flags);
1830 +
1831 +}
1832 +
1833 +#ifdef RC32434_REVISION
1834 +/* Ethernet Rx Overflow interrupt */
1835 +static irqreturn_t
1836 +rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1837 +{
1838 + struct net_device *dev = (struct net_device *)dev_id;
1839 + struct rc32434_local *lp;
1840 + unsigned int ovr;
1841 + irqreturn_t retval = IRQ_NONE;
1842 +
1843 + ASSERT(dev != NULL);
1844 +
1845 + lp = (struct rc32434_local *)dev->priv;
1846 + spin_lock(&lp->lock);
1847 + ovr = rc32434_readl(&lp->eth_regs->ethintfc);
1848 +
1849 + if(ovr & ETHINTFC_ovr_m) {
1850 + netif_stop_queue(dev);
1851 +
1852 + /* clear OVR bit */
1853 + rc32434_writel((ovr & ~ETHINTFC_ovr_m), &lp->eth_regs->ethintfc);
1854 +
1855 + /* Restart interface */
1856 + rc32434_restart(dev);
1857 + retval = IRQ_HANDLED;
1858 + }
1859 + spin_unlock(&lp->lock);
1860 +
1861 + return retval;
1862 +}
1863 +
1864 +#endif
1865 +
1866 +
1867 +/* Ethernet Tx Underflow interrupt */
1868 +static irqreturn_t
1869 +rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1870 +{
1871 + struct net_device *dev = (struct net_device *)dev_id;
1872 + struct rc32434_local *lp;
1873 + unsigned int und;
1874 + irqreturn_t retval = IRQ_NONE;
1875 +
1876 + ASSERT(dev != NULL);
1877 +
1878 + lp = (struct rc32434_local *)dev->priv;
1879 +
1880 + spin_lock(&lp->lock);
1881 +
1882 + und = rc32434_readl(&lp->eth_regs->ethintfc);
1883 +
1884 + if(und & ETHINTFC_und_m) {
1885 + netif_stop_queue(dev);
1886 +
1887 + rc32434_writel((und & ~ETHINTFC_und_m), &lp->eth_regs->ethintfc);
1888 +
1889 + /* Restart interface */
1890 + rc32434_restart(dev);
1891 + retval = IRQ_HANDLED;
1892 + }
1893 +
1894 + spin_unlock(&lp->lock);
1895 +
1896 + return retval;
1897 +}
1898 +
1899 +
1900 +/* Ethernet Rx DMA interrupt */
1901 +static irqreturn_t
1902 +rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1903 +{
1904 + struct net_device *dev = (struct net_device *)dev_id;
1905 + struct rc32434_local* lp;
1906 + volatile u32 dmas,dmasm;
1907 + irqreturn_t retval;
1908 +
1909 + ASSERT(dev != NULL);
1910 +
1911 + lp = (struct rc32434_local *)dev->priv;
1912 +
1913 + spin_lock(&lp->lock);
1914 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
1915 + if(dmas & (DMAS_d_m|DMAS_h_m|DMAS_e_m)) {
1916 + /* Mask D H E bit in Rx DMA */
1917 + dmasm = rc32434_readl(&lp->rx_dma_regs->dmasm);
1918 + rc32434_writel(dmasm | (DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
1919 +#ifdef CONFIG_IDT_USE_NAPI
1920 + if(netif_rx_schedule_prep(dev))
1921 + __netif_rx_schedule(dev);
1922 +#else
1923 + tasklet_hi_schedule(lp->rx_tasklet);
1924 +#endif
1925 +
1926 + if (dmas & DMAS_e_m)
1927 + ERR(": DMA error\n");
1928 +
1929 + retval = IRQ_HANDLED;
1930 + }
1931 + else
1932 + retval = IRQ_NONE;
1933 +
1934 + spin_unlock(&lp->lock);
1935 + return retval;
1936 +}
1937 +
1938 +#ifdef CONFIG_IDT_USE_NAPI
1939 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget)
1940 +#else
1941 +static void rc32434_rx_tasklet(unsigned long rx_data_dev)
1942 +#endif
1943 +{
1944 + struct net_device *dev = (struct net_device *)rx_data_dev;
1945 + struct rc32434_local* lp = netdev_priv(dev);
1946 + volatile DMAD_t rd = &lp->rd_ring[lp->rx_next_done];
1947 + struct sk_buff *skb, *skb_new;
1948 + u8* pkt_buf;
1949 + u32 devcs, count, pkt_len, pktuncrc_len;
1950 + volatile u32 dmas;
1951 +#ifdef CONFIG_IDT_USE_NAPI
1952 + u32 received = 0;
1953 + int rx_work_limit = min(*budget,dev->quota);
1954 +#else
1955 + unsigned long flags;
1956 + spin_lock_irqsave(&lp->lock, flags);
1957 +#endif
1958 +
1959 + while ( (count = RC32434_RBSIZE - (u32)DMA_COUNT(rd->control)) != 0) {
1960 +#ifdef CONFIG_IDT_USE_NAPI
1961 + if(--rx_work_limit <0)
1962 + {
1963 + break;
1964 + }
1965 +#endif
1966 + /* init the var. used for the later operations within the while loop */
1967 + skb_new = NULL;
1968 + devcs = rd->devcs;
1969 + pkt_len = RCVPKT_LENGTH(devcs);
1970 + skb = lp->rx_skb[lp->rx_next_done];
1971 +
1972 + if (count < 64) {
1973 + lp->stats.rx_errors++;
1974 + lp->stats.rx_dropped++;
1975 + }
1976 + else if ((devcs & ( ETHRX_ld_m)) != ETHRX_ld_m) {
1977 + /* check that this is a whole packet */
1978 + /* WARNING: DMA_FD bit incorrectly set in Rc32434 (errata ref #077) */
1979 + lp->stats.rx_errors++;
1980 + lp->stats.rx_dropped++;
1981 + }
1982 + else if ( (devcs & ETHRX_rok_m) ) {
1983 +
1984 + {
1985 + /* must be the (first and) last descriptor then */
1986 + pkt_buf = (u8*)lp->rx_skb[lp->rx_next_done]->data;
1987 +
1988 + pktuncrc_len = pkt_len - 4;
1989 + /* invalidate the cache */
1990 + dma_cache_inv((unsigned long)pkt_buf, pktuncrc_len);
1991 +
1992 + /* Malloc up new buffer. */
1993 + skb_new = dev_alloc_skb(RC32434_RBSIZE + 2);
1994 +
1995 + if (skb_new != NULL){
1996 + /* Make room */
1997 + skb_put(skb, pktuncrc_len);
1998 +
1999 + skb->protocol = eth_type_trans(skb, dev);
2000 +
2001 + /* pass the packet to upper layers */
2002 +#ifdef CONFIG_IDT_USE_NAPI
2003 + netif_receive_skb(skb);
2004 +#else
2005 + netif_rx(skb);
2006 +#endif
2007 +
2008 + dev->last_rx = jiffies;
2009 + lp->stats.rx_packets++;
2010 + lp->stats.rx_bytes += pktuncrc_len;
2011 +
2012 + if (IS_RCV_MP(devcs))
2013 + lp->stats.multicast++;
2014 +
2015 + /* 16 bit align */
2016 + skb_reserve(skb_new, 2);
2017 +
2018 + skb_new->dev = dev;
2019 + lp->rx_skb[lp->rx_next_done] = skb_new;
2020 + }
2021 + else {
2022 + ERR("no memory, dropping rx packet.\n");
2023 + lp->stats.rx_errors++;
2024 + lp->stats.rx_dropped++;
2025 + }
2026 + }
2027 +
2028 + }
2029 + else {
2030 + /* This should only happen if we enable accepting broken packets */
2031 + lp->stats.rx_errors++;
2032 + lp->stats.rx_dropped++;
2033 +
2034 + /* add statistics counters */
2035 + if (IS_RCV_CRC_ERR(devcs)) {
2036 + DBG(2, "RX CRC error\n");
2037 + lp->stats.rx_crc_errors++;
2038 + }
2039 + else if (IS_RCV_LOR_ERR(devcs)) {
2040 + DBG(2, "RX LOR error\n");
2041 + lp->stats.rx_length_errors++;
2042 + }
2043 + else if (IS_RCV_LE_ERR(devcs)) {
2044 + DBG(2, "RX LE error\n");
2045 + lp->stats.rx_length_errors++;
2046 + }
2047 + else if (IS_RCV_OVR_ERR(devcs)) {
2048 + lp->stats.rx_over_errors++;
2049 + }
2050 + else if (IS_RCV_CV_ERR(devcs)) {
2051 + /* code violation */
2052 + DBG(2, "RX CV error\n");
2053 + lp->stats.rx_frame_errors++;
2054 + }
2055 + else if (IS_RCV_CES_ERR(devcs)) {
2056 + DBG(2, "RX Preamble error\n");
2057 + }
2058 + }
2059 +
2060 + rd->devcs = 0;
2061 +
2062 + /* restore descriptor's curr_addr */
2063 + if(skb_new)
2064 + rd->ca = CPHYSADDR(skb_new->data);
2065 + else
2066 + rd->ca = CPHYSADDR(skb->data);
2067 +
2068 + rd->control = DMA_COUNT(RC32434_RBSIZE) |DMAD_cod_m |DMAD_iod_m;
2069 + lp->rd_ring[(lp->rx_next_done-1)& RC32434_RDS_MASK].control &= ~(DMAD_cod_m);
2070 +
2071 + lp->rx_next_done = (lp->rx_next_done + 1) & RC32434_RDS_MASK;
2072 + rd = &lp->rd_ring[lp->rx_next_done];
2073 + rc32434_writel( ~DMAS_d_m, &lp->rx_dma_regs->dmas);
2074 + }
2075 +#ifdef CONFIG_IDT_USE_NAPI
2076 + dev->quota -= received;
2077 + *budget =- received;
2078 + if(rx_work_limit < 0)
2079 + goto not_done;
2080 +#endif
2081 +
2082 + dmas = rc32434_readl(&lp->rx_dma_regs->dmas);
2083 +
2084 + if(dmas & DMAS_h_m) {
2085 + rc32434_writel( ~(DMAS_h_m | DMAS_e_m), &lp->rx_dma_regs->dmas);
2086 +#ifdef RC32434_PROC_DEBUG
2087 + lp->dma_halt_cnt++;
2088 +#endif
2089 + rd->devcs = 0;
2090 + skb = lp->rx_skb[lp->rx_next_done];
2091 + rd->ca = CPHYSADDR(skb->data);
2092 + rc32434_chain_rx(lp,rd);
2093 + }
2094 +
2095 +#ifdef CONFIG_IDT_USE_NAPI
2096 + netif_rx_complete(dev);
2097 +#endif
2098 + /* Enable D H E bit in Rx DMA */
2099 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m |DMASM_e_m), &lp->rx_dma_regs->dmasm);
2100 +#ifdef CONFIG_IDT_USE_NAPI
2101 + return 0;
2102 + not_done:
2103 + return 1;
2104 +#else
2105 + spin_unlock_irqrestore(&lp->lock, flags);
2106 + return;
2107 +#endif
2108 +
2109 +
2110 +}
2111 +
2112 +
2113 +
2114 +/* Ethernet Tx DMA interrupt */
2115 +static irqreturn_t
2116 +rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs)
2117 +{
2118 + struct net_device *dev = (struct net_device *)dev_id;
2119 + struct rc32434_local *lp;
2120 + volatile u32 dmas,dmasm;
2121 + irqreturn_t retval;
2122 +
2123 + ASSERT(dev != NULL);
2124 +
2125 + lp = (struct rc32434_local *)dev->priv;
2126 +
2127 + spin_lock(&lp->lock);
2128 +
2129 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2130 +
2131 + if (dmas & (DMAS_f_m | DMAS_e_m)) {
2132 + dmasm = rc32434_readl(&lp->tx_dma_regs->dmasm);
2133 + /* Mask F E bit in Tx DMA */
2134 + rc32434_writel(dmasm | (DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2135 +
2136 + tasklet_hi_schedule(lp->tx_tasklet);
2137 +
2138 + if(lp->tx_chain_status == filled && (rc32434_readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
2139 + rc32434_writel(CPHYSADDR(&lp->td_ring[lp->tx_chain_head]), &(lp->tx_dma_regs->dmandptr));
2140 + lp->tx_chain_status = empty;
2141 + lp->tx_chain_head = lp->tx_chain_tail;
2142 + dev->trans_start = jiffies;
2143 + }
2144 +
2145 + if (dmas & DMAS_e_m)
2146 + ERR(": DMA error\n");
2147 +
2148 + retval = IRQ_HANDLED;
2149 + }
2150 + else
2151 + retval = IRQ_NONE;
2152 +
2153 + spin_unlock(&lp->lock);
2154 +
2155 + return retval;
2156 +}
2157 +
2158 +
2159 +static void rc32434_tx_tasklet(unsigned long tx_data_dev)
2160 +{
2161 + struct net_device *dev = (struct net_device *)tx_data_dev;
2162 + struct rc32434_local* lp = (struct rc32434_local *)dev->priv;
2163 + volatile DMAD_t td = &lp->td_ring[lp->tx_next_done];
2164 + u32 devcs;
2165 + unsigned long flags;
2166 + volatile u32 dmas;
2167 +
2168 + spin_lock_irqsave(&lp->lock, flags);
2169 +
2170 + /* process all desc that are done */
2171 + while(IS_DMA_FINISHED(td->control)) {
2172 + if(lp->tx_full == 1) {
2173 + netif_wake_queue(dev);
2174 + lp->tx_full = 0;
2175 + }
2176 +
2177 + devcs = lp->td_ring[lp->tx_next_done].devcs;
2178 + if ((devcs & (ETHTX_fd_m | ETHTX_ld_m)) != (ETHTX_fd_m | ETHTX_ld_m)) {
2179 + lp->stats.tx_errors++;
2180 + lp->stats.tx_dropped++;
2181 +
2182 + /* should never happen */
2183 + DBG(1, __FUNCTION__ ": split tx ignored\n");
2184 + }
2185 + else if (IS_TX_TOK(devcs)) {
2186 + lp->stats.tx_packets++;
2187 + }
2188 + else {
2189 + lp->stats.tx_errors++;
2190 + lp->stats.tx_dropped++;
2191 +
2192 + /* underflow */
2193 + if (IS_TX_UND_ERR(devcs))
2194 + lp->stats.tx_fifo_errors++;
2195 +
2196 + /* oversized frame */
2197 + if (IS_TX_OF_ERR(devcs))
2198 + lp->stats.tx_aborted_errors++;
2199 +
2200 + /* excessive deferrals */
2201 + if (IS_TX_ED_ERR(devcs))
2202 + lp->stats.tx_carrier_errors++;
2203 +
2204 + /* collisions: medium busy */
2205 + if (IS_TX_EC_ERR(devcs))
2206 + lp->stats.collisions++;
2207 +
2208 + /* late collision */
2209 + if (IS_TX_LC_ERR(devcs))
2210 + lp->stats.tx_window_errors++;
2211 +
2212 + }
2213 +
2214 + /* We must always free the original skb */
2215 + if (lp->tx_skb[lp->tx_next_done] != NULL) {
2216 + dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
2217 + lp->tx_skb[lp->tx_next_done] = NULL;
2218 + }
2219 +
2220 + lp->td_ring[lp->tx_next_done].control = DMAD_iof_m;
2221 + lp->td_ring[lp->tx_next_done].devcs = ETHTX_fd_m | ETHTX_ld_m;
2222 + lp->td_ring[lp->tx_next_done].link = 0;
2223 + lp->td_ring[lp->tx_next_done].ca = 0;
2224 + lp->tx_count --;
2225 +
2226 + /* go on to next transmission */
2227 + lp->tx_next_done = (lp->tx_next_done + 1) & RC32434_TDS_MASK;
2228 + td = &lp->td_ring[lp->tx_next_done];
2229 +
2230 + }
2231 +
2232 + dmas = rc32434_readl(&lp->tx_dma_regs->dmas);
2233 + rc32434_writel( ~dmas, &lp->tx_dma_regs->dmas);
2234 +
2235 + /* Enable F E bit in Tx DMA */
2236 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2237 + spin_unlock_irqrestore(&lp->lock, flags);
2238 +
2239 +}
2240 +
2241 +
2242 +static struct net_device_stats * rc32434_get_stats(struct net_device *dev)
2243 +{
2244 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2245 + return &lp->stats;
2246 +}
2247 +
2248 +
2249 +/*
2250 + * Set or clear the multicast filter for this adaptor.
2251 + */
2252 +static void rc32434_multicast_list(struct net_device *dev)
2253 +{
2254 + /* listen to broadcasts always and to treat */
2255 + /* IFF bits independantly */
2256 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2257 + unsigned long flags;
2258 + u32 recognise = ETHARC_ab_m; /* always accept broadcasts */
2259 +
2260 + if (dev->flags & IFF_PROMISC) /* set promiscuous mode */
2261 + recognise |= ETHARC_pro_m;
2262 +
2263 + if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 15))
2264 + recognise |= ETHARC_am_m; /* all multicast & bcast */
2265 + else if (dev->mc_count > 0) {
2266 + DBG(2, __FUNCTION__ ": mc_count %d\n", dev->mc_count);
2267 + recognise |= ETHARC_am_m; /* for the time being */
2268 + }
2269 +
2270 + spin_lock_irqsave(&lp->lock, flags);
2271 + rc32434_writel(recognise, &lp->eth_regs->etharc);
2272 + spin_unlock_irqrestore(&lp->lock, flags);
2273 +}
2274 +
2275 +
2276 +static void rc32434_tx_timeout(struct net_device *dev)
2277 +{
2278 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2279 + unsigned long flags;
2280 +
2281 + spin_lock_irqsave(&lp->lock, flags);
2282 + rc32434_restart(dev);
2283 + spin_unlock_irqrestore(&lp->lock, flags);
2284 +
2285 +}
2286 +
2287 +
2288 +/*
2289 + * Initialize the RC32434 ethernet controller.
2290 + */
2291 +static int rc32434_init(struct net_device *dev)
2292 +{
2293 + struct rc32434_local *lp = (struct rc32434_local *)dev->priv;
2294 + int i, j;
2295 +
2296 + /* Disable DMA */
2297 + rc32434_abort_tx(dev);
2298 + rc32434_abort_rx(dev);
2299 +
2300 + /* reset ethernet logic */
2301 + rc32434_writel(0, &lp->eth_regs->ethintfc);
2302 + while((rc32434_readl(&lp->eth_regs->ethintfc) & ETHINTFC_rip_m))
2303 + dev->trans_start = jiffies;
2304 +
2305 + /* Enable Ethernet Interface */
2306 + rc32434_writel(ETHINTFC_en_m, &lp->eth_regs->ethintfc);
2307 +
2308 +#ifndef CONFIG_IDT_USE_NAPI
2309 + tasklet_disable(lp->rx_tasklet);
2310 +#endif
2311 + tasklet_disable(lp->tx_tasklet);
2312 +
2313 + /* Initialize the transmit Descriptors */
2314 + for (i = 0; i < RC32434_NUM_TDS; i++) {
2315 + lp->td_ring[i].control = DMAD_iof_m;
2316 + lp->td_ring[i].devcs = ETHTX_fd_m | ETHTX_ld_m;
2317 + lp->td_ring[i].ca = 0;
2318 + lp->td_ring[i].link = 0;
2319 + if (lp->tx_skb[i] != NULL) {
2320 + dev_kfree_skb_any(lp->tx_skb[i]);
2321 + lp->tx_skb[i] = NULL;
2322 + }
2323 + }
2324 + lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail = lp->tx_full = lp->tx_count = 0;
2325 + lp-> tx_chain_status = empty;
2326 +
2327 + /*
2328 + * Initialize the receive descriptors so that they
2329 + * become a circular linked list, ie. let the last
2330 + * descriptor point to the first again.
2331 + */
2332 + for (i=0; i<RC32434_NUM_RDS; i++) {
2333 + struct sk_buff *skb = lp->rx_skb[i];
2334 +
2335 + if (lp->rx_skb[i] == NULL) {
2336 + skb = dev_alloc_skb(RC32434_RBSIZE + 2);
2337 + if (skb == NULL) {
2338 + ERR("No memory in the system\n");
2339 + for (j = 0; j < RC32434_NUM_RDS; j ++)
2340 + if (lp->rx_skb[j] != NULL)
2341 + dev_kfree_skb_any(lp->rx_skb[j]);
2342 +
2343 + return 1;
2344 + }
2345 + else {
2346 + skb->dev = dev;
2347 + skb_reserve(skb, 2);
2348 + lp->rx_skb[i] = skb;
2349 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2350 +
2351 + }
2352 + }
2353 + lp->rd_ring[i].control = DMAD_iod_m | DMA_COUNT(RC32434_RBSIZE);
2354 + lp->rd_ring[i].devcs = 0;
2355 + lp->rd_ring[i].ca = CPHYSADDR(skb->data);
2356 + lp->rd_ring[i].link = CPHYSADDR(&lp->rd_ring[i+1]);
2357 +
2358 + }
2359 + /* loop back */
2360 + lp->rd_ring[RC32434_NUM_RDS-1].link = CPHYSADDR(&lp->rd_ring[0]);
2361 + lp->rx_next_done = 0;
2362 +
2363 + lp->rd_ring[RC32434_NUM_RDS-1].control |= DMAD_cod_m;
2364 + lp->rx_chain_head = 0;
2365 + lp->rx_chain_tail = 0;
2366 + lp->rx_chain_status = empty;
2367 +
2368 + rc32434_writel(0, &lp->rx_dma_regs->dmas);
2369 + /* Start Rx DMA */
2370 + rc32434_start_rx(lp, &lp->rd_ring[0]);
2371 +
2372 + /* Enable F E bit in Tx DMA */
2373 + rc32434_writel(rc32434_readl(&lp->tx_dma_regs->dmasm) & ~(DMASM_f_m | DMASM_e_m), &lp->tx_dma_regs->dmasm);
2374 + /* Enable D H E bit in Rx DMA */
2375 + rc32434_writel(rc32434_readl(&lp->rx_dma_regs->dmasm) & ~(DMASM_d_m | DMASM_h_m | DMASM_e_m), &lp->rx_dma_regs->dmasm);
2376 +
2377 + /* Accept only packets destined for this Ethernet device address */
2378 + rc32434_writel(ETHARC_ab_m, &lp->eth_regs->etharc);
2379 +
2380 + /* Set all Ether station address registers to their initial values */
2381 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
2382 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
2383 +
2384 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
2385 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
2386 +
2387 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
2388 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
2389 +
2390 + rc32434_writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
2391 + rc32434_writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
2392 +
2393 +
2394 + /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
2395 + rc32434_writel(ETHMAC2_pe_m | ETHMAC2_cen_m | ETHMAC2_fd_m, &lp->eth_regs->ethmac2);
2396 + //ETHMAC2_flc_m ETHMAC2_fd_m lp->duplex_mode
2397 +
2398 + /* Back to back inter-packet-gap */
2399 + rc32434_writel(0x15, &lp->eth_regs->ethipgt);
2400 + /* Non - Back to back inter-packet-gap */
2401 + rc32434_writel(0x12, &lp->eth_regs->ethipgr);
2402 +
2403 + /* Management Clock Prescaler Divisor */
2404 + /* Clock independent setting */
2405 + rc32434_writel(((idt_cpu_freq)/MII_CLOCK+1) & ~1,
2406 + &lp->eth_regs->ethmcp);
2407 +
2408 + /* don't transmit until fifo contains 48b */
2409 + rc32434_writel(48, &lp->eth_regs->ethfifott);
2410 +
2411 + rc32434_writel(ETHMAC1_re_m, &lp->eth_regs->ethmac1);
2412 +
2413 +#ifndef CONFIG_IDT_USE_NAPI
2414 + tasklet_enable(lp->rx_tasklet);
2415 +#endif
2416 + tasklet_enable(lp->tx_tasklet);
2417 +
2418 + netif_start_queue(dev);
2419 +
2420 +
2421 + return 0;
2422 +
2423 +}
2424 +
2425 +
2426 +#ifndef MODULE
2427 +
2428 +static int __init rc32434_setup(char *options)
2429 +{
2430 + /* no options yet */
2431 + return 1;
2432 +}
2433 +
2434 +static int __init rc32434_setup_ethaddr0(char *options)
2435 +{
2436 + memcpy(mac0, options, 17);
2437 + mac0[17]= '\0';
2438 + return 1;
2439 +}
2440 +
2441 +__setup("rc32434eth=", rc32434_setup);
2442 +__setup("ethaddr0=", rc32434_setup_ethaddr0);
2443 +
2444 +
2445 +#endif /* MODULE */
2446 +
2447 +module_init(rc32434_init_module);
2448 +module_exit(rc32434_cleanup_module);
2449 +
2450 +
2451 +
2452 +
2453 +
2454 +
2455 +
2456 +
2457 +
2458 +
2459 +
2460 +
2461 +
2462 +
2463 diff -Nur linux-2.6.16/drivers/net/rc32434_eth.h linux-2.6.16-owrt/drivers/net/rc32434_eth.h
2464 --- linux-2.6.16/drivers/net/rc32434_eth.h 1970-01-01 01:00:00.000000000 +0100
2465 +++ linux-2.6.16-owrt/drivers/net/rc32434_eth.h 2006-03-20 14:25:10.000000000 +0100
2466 @@ -0,0 +1,187 @@
2467 +/**************************************************************************
2468 + *
2469 + * BRIEF MODULE DESCRIPTION
2470 + * Definitions for IDT RC32434 on-chip ethernet controller.
2471 + *
2472 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2473 + *
2474 + * This program is free software; you can redistribute it and/or modify it
2475 + * under the terms of the GNU General Public License as published by the
2476 + * Free Software Foundation; either version 2 of the License, or (at your
2477 + * option) any later version.
2478 + *
2479 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2480 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2481 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2482 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2483 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2484 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2485 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2486 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2487 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2488 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2489 + *
2490 + * You should have received a copy of the GNU General Public License along
2491 + * with this program; if not, write to the Free Software Foundation, Inc.,
2492 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2493 + *
2494 + *
2495 + **************************************************************************
2496 + * May 2004 rkt, neb
2497 + *
2498 + * Initial Release
2499 + *
2500 + * Aug 2004
2501 + *
2502 + * Added NAPI
2503 + *
2504 + **************************************************************************
2505 + */
2506 +
2507 +
2508 +#include <asm/idt-boards/rc32434/rc32434.h>
2509 +#include <asm/idt-boards/rc32434/rc32434_dma_v.h>
2510 +#include <asm/idt-boards/rc32434/rc32434_eth_v.h>
2511 +
2512 +#define RC32434_DEBUG 2
2513 +//#define RC32434_PROC_DEBUG
2514 +#undef RC32434_DEBUG
2515 +
2516 +#ifdef RC32434_DEBUG
2517 +
2518 +/* use 0 for production, 1 for verification, >2 for debug */
2519 +static int rc32434_debug = RC32434_DEBUG;
2520 +#define ASSERT(expr) \
2521 + if(!(expr)) { \
2522 + printk( "Assertion failed! %s,%s,%s,line=%d\n", \
2523 + #expr,__FILE__,__FUNCTION__,__LINE__); }
2524 +#define DBG(lvl, format, arg...) if (rc32434_debug > lvl) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2525 +#else
2526 +#define ASSERT(expr) do {} while (0)
2527 +#define DBG(lvl, format, arg...) do {} while (0)
2528 +#endif
2529 +
2530 +#define INFO(format, arg...) printk(KERN_INFO "%s: " format, dev->name , ## arg)
2531 +#define ERR(format, arg...) printk(KERN_ERR "%s: " format, dev->name , ## arg)
2532 +#define WARN(format, arg...) printk(KERN_WARNING "%s: " format, dev->name , ## arg)
2533 +
2534 +#define ETH0_DMA_RX_IRQ GROUP1_IRQ_BASE + 0
2535 +#define ETH0_DMA_TX_IRQ GROUP1_IRQ_BASE + 1
2536 +#define ETH0_RX_OVR_IRQ GROUP3_IRQ_BASE + 9
2537 +#define ETH0_TX_UND_IRQ GROUP3_IRQ_BASE + 10
2538 +
2539 +#define ETH0_RX_DMA_ADDR (DMA0_PhysicalAddress + 0*DMA_CHAN_OFFSET)
2540 +#define ETH0_TX_DMA_ADDR (DMA0_PhysicalAddress + 1*DMA_CHAN_OFFSET)
2541 +
2542 +/* the following must be powers of two */
2543 +#ifdef CONFIG_IDT_USE_NAPI
2544 +#define RC32434_NUM_RDS 64 /* number of receive descriptors */
2545 +#define RC32434_NUM_TDS 64 /* number of transmit descriptors */
2546 +#else
2547 +#define RC32434_NUM_RDS 128 /* number of receive descriptors */
2548 +#define RC32434_NUM_TDS 128 /* number of transmit descriptors */
2549 +#endif
2550 +
2551 +#define RC32434_RBSIZE 1536 /* size of one resource buffer = Ether MTU */
2552 +#define RC32434_RDS_MASK (RC32434_NUM_RDS-1)
2553 +#define RC32434_TDS_MASK (RC32434_NUM_TDS-1)
2554 +#define RD_RING_SIZE (RC32434_NUM_RDS * sizeof(struct DMAD_s))
2555 +#define TD_RING_SIZE (RC32434_NUM_TDS * sizeof(struct DMAD_s))
2556 +
2557 +#define RC32434_TX_TIMEOUT HZ * 100
2558 +
2559 +#define rc32434_eth0_regs ((ETH_t)(ETH0_VirtualAddress))
2560 +#define rc32434_eth1_regs ((ETH_t)(ETH1_VirtualAddress))
2561 +
2562 +enum status { filled, empty};
2563 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
2564 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
2565 +
2566 +
2567 +/* Information that need to be kept for each board. */
2568 +struct rc32434_local {
2569 + ETH_t eth_regs;
2570 + DMA_Chan_t rx_dma_regs;
2571 + DMA_Chan_t tx_dma_regs;
2572 + volatile DMAD_t td_ring; /* transmit descriptor ring */
2573 + volatile DMAD_t rd_ring; /* receive descriptor ring */
2574 +
2575 + struct sk_buff* tx_skb[RC32434_NUM_TDS]; /* skbuffs for pkt to trans */
2576 + struct sk_buff* rx_skb[RC32434_NUM_RDS]; /* skbuffs for pkt to trans */
2577 +
2578 +#ifndef CONFIG_IDT_USE_NAPI
2579 + struct tasklet_struct * rx_tasklet;
2580 +#endif
2581 + struct tasklet_struct * tx_tasklet;
2582 +
2583 + int rx_next_done;
2584 + int rx_chain_head;
2585 + int rx_chain_tail;
2586 + enum status rx_chain_status;
2587 +
2588 + int tx_next_done;
2589 + int tx_chain_head;
2590 + int tx_chain_tail;
2591 + enum status tx_chain_status;
2592 + int tx_count;
2593 + int tx_full;
2594 +
2595 + struct timer_list mii_phy_timer;
2596 + unsigned long duplex_mode;
2597 +
2598 + int rx_irq;
2599 + int tx_irq;
2600 + int ovr_irq;
2601 + int und_irq;
2602 +
2603 + struct net_device_stats stats;
2604 + spinlock_t lock;
2605 +
2606 + /* debug /proc entry */
2607 + struct proc_dir_entry *ps;
2608 + int dma_halt_cnt; int dma_run_cnt;
2609 +};
2610 +
2611 +extern unsigned int idt_cpu_freq;
2612 +
2613 +/* Index to functions, as function prototypes. */
2614 +static int rc32434_open(struct net_device *dev);
2615 +static int rc32434_send_packet(struct sk_buff *skb, struct net_device *dev);
2616 +static void rc32434_mii_handler(unsigned long data);
2617 +static irqreturn_t rc32434_und_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2618 +static irqreturn_t rc32434_rx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2619 +static irqreturn_t rc32434_tx_dma_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2620 +#ifdef RC32434_REVISION
2621 +static irqreturn_t rc32434_ovr_interrupt(int irq, void *dev_id, struct pt_regs * regs);
2622 +#endif
2623 +static int rc32434_close(struct net_device *dev);
2624 +static struct net_device_stats *rc32434_get_stats(struct net_device *dev);
2625 +static void rc32434_multicast_list(struct net_device *dev);
2626 +static int rc32434_init(struct net_device *dev);
2627 +static void rc32434_tx_timeout(struct net_device *dev);
2628 +
2629 +static void rc32434_tx_tasklet(unsigned long tx_data_dev);
2630 +#ifdef CONFIG_IDT_USE_NAPI
2631 +static int rc32434_poll(struct net_device *rx_data_dev, int *budget);
2632 +#else
2633 +static void rc32434_rx_tasklet(unsigned long rx_data_dev);
2634 +#endif
2635 +static void rc32434_cleanup_module(void);
2636 +static int rc32434_probe(int port_num);
2637 +int rc32434_init_module(void);
2638 +
2639 +
2640 +static inline void rc32434_abort_dma(struct net_device *dev, DMA_Chan_t ch)
2641 +{
2642 + if (rc32434_readl(&ch->dmac) & DMAC_run_m) {
2643 + rc32434_writel(0x10, &ch->dmac);
2644 +
2645 + while (!(rc32434_readl(&ch->dmas) & DMAS_h_m))
2646 + dev->trans_start = jiffies;
2647 +
2648 + rc32434_writel(0, &ch->dmas);
2649 + }
2650 +
2651 + rc32434_writel(0, &ch->dmadptr);
2652 + rc32434_writel(0, &ch->dmandptr);
2653 +}
2654 diff -Nur linux-2.6.16/include/asm-mips/bootinfo.h linux-2.6.16-owrt/include/asm-mips/bootinfo.h
2655 --- linux-2.6.16/include/asm-mips/bootinfo.h 2006-03-20 06:53:29.000000000 +0100
2656 +++ linux-2.6.16-owrt/include/asm-mips/bootinfo.h 2006-03-20 14:25:10.000000000 +0100
2657 @@ -218,6 +218,17 @@
2658 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
2659 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
2660
2661 +
2662 +/*
2663 + * Valid machtype for group ARUBA
2664 + */
2665 +#define MACH_GROUP_ARUBA 23
2666 +#define MACH_ARUBA_UNKNOWN 0
2667 +#define MACH_ARUBA_AP60 1
2668 +#define MACH_ARUBA_AP65 2
2669 +#define MACH_ARUBA_AP70 3
2670 +#define MACH_ARUBA_AP40 4
2671 +
2672 #define CL_SIZE COMMAND_LINE_SIZE
2673
2674 const char *get_system_type(void);
2675 diff -Nur linux-2.6.16/include/asm-mips/cpu.h linux-2.6.16-owrt/include/asm-mips/cpu.h
2676 --- linux-2.6.16/include/asm-mips/cpu.h 2006-03-20 06:53:29.000000000 +0100
2677 +++ linux-2.6.16-owrt/include/asm-mips/cpu.h 2006-03-20 14:25:10.000000000 +0100
2678 @@ -53,6 +53,9 @@
2679 #define PRID_IMP_R12000 0x0e00
2680 #define PRID_IMP_R8000 0x1000
2681 #define PRID_IMP_PR4450 0x1200
2682 +#define PRID_IMP_RC32334 0x1800
2683 +#define PRID_IMP_RC32355 0x1900
2684 +#define PRID_IMP_RC32365 0x1900
2685 #define PRID_IMP_R4600 0x2000
2686 #define PRID_IMP_R4700 0x2100
2687 #define PRID_IMP_TX39 0x2200
2688 @@ -196,7 +199,8 @@
2689 #define CPU_34K 60
2690 #define CPU_PR4450 61
2691 #define CPU_SB1A 62
2692 -#define CPU_LAST 62
2693 +#define CPU_RC32300 63
2694 +#define CPU_LAST 63
2695
2696 /*
2697 * ISA Level encodings
2698 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h
2699 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32300.h 1970-01-01 01:00:00.000000000 +0100
2700 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32300.h 2006-03-20 14:25:10.000000000 +0100
2701 @@ -0,0 +1,142 @@
2702 +/**************************************************************************
2703 + *
2704 + * BRIEF MODULE DESCRIPTION
2705 + * RC32300 helper routines
2706 + *
2707 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2708 + *
2709 + * This program is free software; you can redistribute it and/or modify it
2710 + * under the terms of the GNU General Public License as published by the
2711 + * Free Software Foundation; either version 2 of the License, or (at your
2712 + * option) any later version.
2713 + *
2714 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2715 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2716 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2717 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2718 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2719 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2720 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2721 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2722 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2723 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2724 + *
2725 + * You should have received a copy of the GNU General Public License along
2726 + * with this program; if not, write to the Free Software Foundation, Inc.,
2727 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2728 + *
2729 + *
2730 + **************************************************************************
2731 + * May 2004 P. Sadik.
2732 + *
2733 + * Initial Release
2734 + *
2735 + *
2736 + *
2737 + **************************************************************************
2738 + */
2739 +
2740 +#ifndef __IDT_RC32300_H__
2741 +#define __IDT_RC32300_H__
2742 +
2743 +#include <linux/delay.h>
2744 +#include <asm/io.h>
2745 +
2746 +
2747 +/* cpu pipeline flush */
2748 +static inline void rc32300_sync(void)
2749 +{
2750 + __asm__ volatile ("sync");
2751 +}
2752 +
2753 +static inline void rc32300_sync_udelay(int us)
2754 +{
2755 + __asm__ volatile ("sync");
2756 + udelay(us);
2757 +}
2758 +
2759 +static inline void rc32300_sync_delay(int ms)
2760 +{
2761 + __asm__ volatile ("sync");
2762 + mdelay(ms);
2763 +}
2764 +
2765 +/*
2766 + * Macros to access internal RC32300 registers. No byte
2767 + * swapping should be done when accessing the internal
2768 + * registers.
2769 + */
2770 +
2771 +static inline u8 rc32300_readb(unsigned long pa)
2772 +{
2773 + return *((volatile u8 *)KSEG1ADDR(pa));
2774 +}
2775 +static inline u16 rc32300_readw(unsigned long pa)
2776 +{
2777 + return *((volatile u16 *)KSEG1ADDR(pa));
2778 +}
2779 +static inline u32 rc32300_readl(unsigned long pa)
2780 +{
2781 + return *((volatile u32 *)KSEG1ADDR(pa));
2782 +}
2783 +static inline void rc32300_writeb(u8 val, unsigned long pa)
2784 +{
2785 + *((volatile u8 *)KSEG1ADDR(pa)) = val;
2786 +}
2787 +static inline void rc32300_writew(u16 val, unsigned long pa)
2788 +{
2789 + *((volatile u16 *)KSEG1ADDR(pa)) = val;
2790 +}
2791 +static inline void rc32300_writel(u32 val, unsigned long pa)
2792 +{
2793 + *((volatile u32 *)KSEG1ADDR(pa)) = val;
2794 +}
2795 +
2796 +
2797 +#define local_readb __raw_readb
2798 +#define local_readw __raw_readw
2799 +#define local_readl __raw_readl
2800 +
2801 +#define local_writeb __raw_writeb
2802 +#define local_writew __raw_writew
2803 +#define local_writel __raw_writel
2804 +
2805 +
2806 +/*
2807 + * C access to CLZ and CLO instructions
2808 + * (count leading zeroes/ones).
2809 + */
2810 +static inline int rc32300_clz(unsigned long val)
2811 +{
2812 + int ret;
2813 + __asm__ volatile (
2814 + ".set\tnoreorder\n\t"
2815 + ".set\tnoat\n\t"
2816 + ".set\tmips32\n\t"
2817 + "clz\t%0,%1\n\t"
2818 + ".set\tmips0\n\t"
2819 + ".set\tat\n\t"
2820 + ".set\treorder"
2821 + : "=r" (ret)
2822 + : "r" (val));
2823 +
2824 + return ret;
2825 +}
2826 +static inline int rc32300_clo(unsigned long val)
2827 +{
2828 + int ret;
2829 + __asm__ volatile (
2830 + ".set\tnoreorder\n\t"
2831 + ".set\tnoat\n\t"
2832 + ".set\tmips32\n\t"
2833 + "clo\t%0,%1\n\t"
2834 + ".set\tmips0\n\t"
2835 + ".set\tat\n\t"
2836 + ".set\treorder"
2837 + : "=r" (ret)
2838 + : "r" (val));
2839 +
2840 + return ret;
2841 +}
2842 +
2843 +#endif // __IDT_RC32300_H__
2844 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h
2845 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32334.h 1970-01-01 01:00:00.000000000 +0100
2846 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32334.h 2006-03-20 14:25:10.000000000 +0100
2847 @@ -0,0 +1,207 @@
2848 +/**************************************************************************
2849 + *
2850 + * BRIEF MODULE DESCRIPTION
2851 + * Definitions for IDT RC32334 CPU.
2852 + *
2853 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
2854 + *
2855 + * This program is free software; you can redistribute it and/or modify it
2856 + * under the terms of the GNU General Public License as published by the
2857 + * Free Software Foundation; either version 2 of the License, or (at your
2858 + * option) any later version.
2859 + *
2860 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2861 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2862 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2863 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2864 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2865 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2866 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2867 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2868 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2869 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2870 + *
2871 + * You should have received a copy of the GNU General Public License along
2872 + * with this program; if not, write to the Free Software Foundation, Inc.,
2873 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2874 + *
2875 + *
2876 + **************************************************************************
2877 + * May 2004 P. Sadik.
2878 + *
2879 + * Initial Release
2880 + *
2881 + *
2882 + *
2883 + **************************************************************************
2884 + */
2885 +
2886 +
2887 +#ifndef __IDT_RC32334_H__
2888 +#define __IDT_RC32334_H__
2889 +
2890 +#include <linux/delay.h>
2891 +#include <asm/io.h>
2892 +
2893 +/* Base address of internal registers */
2894 +#define RC32334_REG_BASE 0x18000000
2895 +
2896 +/* CPU and IP Bus Control */
2897 +#define CPU_PORT_WIDTH 0xffffe200 // virtual!
2898 +#define CPU_BTA 0xffffe204 // virtual!
2899 +#define CPU_BUSERR_ADDR 0xffffe208 // virtual!
2900 +#define CPU_IP_BTA (RC32334_REG_BASE + 0x0000)
2901 +#define CPU_IP_ADDR_LATCH (RC32334_REG_BASE + 0x0004)
2902 +#define CPU_IP_ARBITRATION (RC32334_REG_BASE + 0x0008)
2903 +#define CPU_IP_BUSERR_CNTL (RC32334_REG_BASE + 0x0010)
2904 +#define CPU_IP_BUSERR_ADDR (RC32334_REG_BASE + 0x0014)
2905 +#define CPU_IP_SYSID (RC32334_REG_BASE + 0x0018)
2906 +
2907 +/* Memory Controller */
2908 +#define MEM_BASE_BANK0 (RC32334_REG_BASE + 0x0080)
2909 +#define MEM_MASK_BANK0 (RC32334_REG_BASE + 0x0084)
2910 +#define MEM_CNTL_BANK0 (RC32334_REG_BASE + 0x0200)
2911 +#define MEM_BASE_BANK1 (RC32334_REG_BASE + 0x0088)
2912 +#define MEM_MASK_BANK1 (RC32334_REG_BASE + 0x008c)
2913 +#define MEM_CNTL_BANK1 (RC32334_REG_BASE + 0x0204)
2914 +#define MEM_CNTL_BANK2 (RC32334_REG_BASE + 0x0208)
2915 +#define MEM_CNTL_BANK3 (RC32334_REG_BASE + 0x020c)
2916 +#define MEM_CNTL_BANK4 (RC32334_REG_BASE + 0x0210)
2917 +#define MEM_CNTL_BANK5 (RC32334_REG_BASE + 0x0214)
2918 +
2919 +/* PCI Controller */
2920 +#define PCI_INTR_PEND (RC32334_REG_BASE + 0x05b0)
2921 +#define PCI_INTR_MASK (RC32334_REG_BASE + 0x05b4)
2922 +#define PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05b8)
2923 +#define CPU2PCI_INTR_PEND (RC32334_REG_BASE + 0x05c0)
2924 +#define CPU2PCI_INTR_MASK (RC32334_REG_BASE + 0x05c4)
2925 +#define CPU2PCI_INTR_CLEAR (RC32334_REG_BASE + 0x05c8)
2926 +#define PCI2CPU_INTR_PEND (RC32334_REG_BASE + 0x05d0)
2927 +#define PCI2CPU_INTR_MASK (RC32334_REG_BASE + 0x05d4)
2928 +#define PCI2CPU_INTR_CLEAR (RC32334_REG_BASE + 0x05d8)
2929 +#define PCI_MEM1_BASE (RC32334_REG_BASE + 0x20b0)
2930 +#define PCI_MEM2_BASE (RC32334_REG_BASE + 0x20b8)
2931 +#define PCI_MEM3_BASE (RC32334_REG_BASE + 0x20c0)
2932 +#define PCI_IO1_BASE (RC32334_REG_BASE + 0x20c8)
2933 +#define PCI_ARBITRATION (RC32334_REG_BASE + 0x20e0)
2934 +#define PCI_CPU_MEM1_BASE (RC32334_REG_BASE + 0x20e8)
2935 +#define PCI_CPU_IO_BASE (RC32334_REG_BASE + 0x2100)
2936 +#define PCI_CFG_CNTL (RC32334_REG_BASE + 0x2cf8)
2937 +#define PCI_CFG_DATA (RC32334_REG_BASE + 0x2cfc)
2938 +
2939 +/* Timers */
2940 +#define TIMER0_CNTL (RC32334_REG_BASE + 0x0700)
2941 +#define TIMER0_COUNT (RC32334_REG_BASE + 0x0704)
2942 +#define TIMER0_COMPARE (RC32334_REG_BASE + 0x0708)
2943 +#define TIMER_REG_OFFSET 0x10
2944 +
2945 +/* Programmable I/O */
2946 +#define PIO_DATA0 (RC32334_REG_BASE + 0x0600)
2947 +#define PIO_DATA1 (RC32334_REG_BASE + 0x0610)
2948 +
2949 +/*
2950 + * DMA
2951 + *
2952 + * NOTE: DMA_IO is a trick for non linear RC32300_IO_DMA stuff
2953 + *
2954 + * DMA0: 18001400
2955 + * DMA1: 18001440
2956 + * DMA2: 18001900
2957 + * DMA3: 18001940
2958 + * NB: dma number must be immediate value or variable.
2959 + * It MUST NOT be a function since it would get called twice!
2960 + */
2961 +#define DMA_IO(n) (((n)>1?0x500:0)+((n)&1?0x40:0))
2962 +
2963 +#define RC32300_IO_DMA(n) (RC32334_REG_BASE + 0x1400 + DMA_IO(n))
2964 +#define RC32300_DMA_CONFREG(n) RC32300_IO_DMA(n)
2965 +#define RC32300_DMA_BASEREG(n) (RC32300_IO_DMA(n)+0x4)
2966 +
2967 +#define RC32300_DMA_CURRREG(n) (RC32300_IO_DMA(n)+0x8)
2968 +#define RC32300_DMA_STATREG(n) (RC32300_IO_DMA(n)+0x10)
2969 +#define RC32300_DMA_SRCREG(n) (RC32300_IO_DMA(n)+0x14)
2970 +#define RC32300_DMA_DSTREG(n) (RC32300_IO_DMA(n)+0x18)
2971 +#define RC32300_DMA_NEXTREG(n) (RC32300_IO_DMA(n)+0x1c)
2972 +
2973 +#define RC32300_DMA_IRQ(n) (GROUP7_IRQ_BASE+5*(n))
2974 +
2975 +/* Expansion Interrupt Controller */
2976 +#define IC_GROUP0_PEND (RC32334_REG_BASE + 0x0500)
2977 +#define IC_GROUP0_MASK (RC32334_REG_BASE + 0x0504)
2978 +#define IC_GROUP0_CLEAR (RC32334_REG_BASE + 0x0508)
2979 +#define IC_GROUP_OFFSET 0x10
2980 +
2981 +#define NUM_INTR_GROUPS 15
2982 +/*
2983 + * The IRQ mapping is as follows:
2984 + *
2985 + * IRQ Mapped To
2986 + * --- -------------------
2987 + * 0 SW0 (IP0) SW0 intr
2988 + * 1 SW1 (IP1) SW1 intr
2989 + * 2 Int0 (IP2) board-specific
2990 + * 3 Int1 (IP3) board-specific
2991 + * 4 Int2 (IP4) board-specific
2992 + * - Int3 (IP5) not used, mapped to IRQ's 8 and up
2993 + * 6 Int4 (IP6) board-specific
2994 + * 7 Int5 (IP7) CP0 Timer
2995 + *
2996 + * IRQ's 8 and up are all mapped to Int3 (IP5), which
2997 + * internally on the RC32334 is routed to the Expansion
2998 + * Interrupt Controller.
2999 + */
3000 +#define MIPS_CPU_TIMER_IRQ 7
3001 +
3002 +#define GROUP1_IRQ_BASE 8 // bus error
3003 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 1) // PIO active low
3004 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 12) // PIO active high
3005 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 8) // Timer Rollovers
3006 +#define GROUP5_IRQ_BASE (GROUP4_IRQ_BASE + 8) // UART0
3007 +#define GROUP6_IRQ_BASE (GROUP5_IRQ_BASE + 3) // UART1
3008 +#define GROUP7_IRQ_BASE (GROUP6_IRQ_BASE + 3) // DMA Ch0
3009 +#define GROUP8_IRQ_BASE (GROUP7_IRQ_BASE + 5) // DMA Ch1
3010 +#define GROUP9_IRQ_BASE (GROUP8_IRQ_BASE + 5) // DMA Ch2
3011 +#define GROUP10_IRQ_BASE (GROUP9_IRQ_BASE + 5) // DMA Ch3
3012 +#define GROUP11_IRQ_BASE (GROUP10_IRQ_BASE + 5) // PCI Ctlr errors
3013 +#define GROUP12_IRQ_BASE (GROUP11_IRQ_BASE + 4) // PCI Satellite Mode
3014 +#define GROUP13_IRQ_BASE (GROUP12_IRQ_BASE + 16) // PCI to CPU Mailbox
3015 +#define GROUP14_IRQ_BASE (GROUP13_IRQ_BASE + 4) // SPI
3016 +
3017 +#define RC32334_NR_IRQS (GROUP14_IRQ_BASE + 1)
3018 +
3019 +/* 16550 UARTs */
3020 +#ifdef __MIPSEB__
3021 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0803)
3022 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0823)
3023 +#else
3024 +#define RC32300_UART0_BASE (RC32334_REG_BASE + 0x0800)
3025 +#define RC32300_UART1_BASE (RC32334_REG_BASE + 0x0820)
3026 +#endif
3027 +
3028 +#define RC32300_UART0_IRQ GROUP5_IRQ_BASE
3029 +#define RC32300_UART1_IRQ GROUP6_IRQ_BASE
3030 +
3031 +#define IDT_CLOCK_MULT 2
3032 +
3033 +/* NVRAM */
3034 +#define NVRAM_BASE 0x12000000
3035 +#define NVRAM_ENVSIZE_OFF 4
3036 +#define NVRAM_ENVSTART_OFF 0x40
3037 +
3038 +/* LCD 4-digit display */
3039 +#define LCD_CLEAR 0x14000400
3040 +#define LCD_DIGIT0 0x1400000f
3041 +#define LCD_DIGIT1 0x14000008
3042 +#define LCD_DIGIT2 0x14000007
3043 +#define LCD_DIGIT3 0x14000003
3044 +
3045 +/* Interrupts routed on 79S334A board (see rc32334.h) */
3046 +#define RC32334_SCC8530_IRQ 2
3047 +#define RC32334_PCI_INTA_IRQ 3
3048 +#define RC32334_PCI_INTB_IRQ 4
3049 +#define RC32334_PCI_INTC_IRQ 6
3050 +#define RC32334_PCI_INTD_IRQ 7
3051 +
3052 +#define RAM_SIZE (32*1024*1024)
3053 +
3054 +#endif // __IDT_RC32334_H__
3055 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h
3056 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 1970-01-01 01:00:00.000000000 +0100
3057 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_dma.h 2006-03-20 14:25:10.000000000 +0100
3058 @@ -0,0 +1,206 @@
3059 +/**************************************************************************
3060 + *
3061 + * BRIEF MODULE DESCRIPTION
3062 + * DMA controller defines on IDT RC32355
3063 + *
3064 + * Copyright 2004 IDT Inc.
3065 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3066 + *
3067 + *
3068 + * This program is free software; you can redistribute it and/or modify it
3069 + * under the terms of the GNU General Public License as published by the
3070 + * Free Software Foundation; either version 2 of the License, or (at your
3071 + * option) any later version.
3072 + *
3073 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3074 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3075 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3076 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3077 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3078 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3079 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3080 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3081 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3082 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3083 + *
3084 + * You should have received a copy of the GNU General Public License along
3085 + * with this program; if not, write to the Free Software Foundation, Inc.,
3086 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3087 + *
3088 + *
3089 + * May 2004 rkt
3090 + * Initial Release
3091 + *
3092 + **************************************************************************
3093 + */
3094 +
3095 +#ifndef BANYAN_DMA_H
3096 +#define BANYAN_DMA_H
3097 +#include <asm/idt-boards/rc32300/rc32300.h>
3098 +
3099 +/*
3100 + * An image of one RC32355 dma channel registers
3101 + */
3102 +typedef struct {
3103 + u32 dmac;
3104 + u32 dmas;
3105 + u32 dmasm;
3106 + u32 dmadptr;
3107 + u32 dmandptr;
3108 +} rc32355_dma_ch_t;
3109 +
3110 +/*
3111 + * An image of all RC32355 dma channel registers
3112 + */
3113 +typedef struct {
3114 + rc32355_dma_ch_t ch[16];
3115 +} rc32355_dma_regs_t;
3116 +
3117 +
3118 +#define rc32355_dma_regs ((rc32355_dma_regs_t*)KSEG1ADDR(RC32355_DMA_BASE))
3119 +
3120 +
3121 +/* DMAC register layout */
3122 +
3123 +#define DMAC_RUN 0x1 /* Halts processing when cleared */
3124 +#define DMAC_DM 0x2 /* Done Mask, ignore DMA events */
3125 +#define DMAC_MODE_MASK 0xC /* DMA operating mode */
3126 +
3127 +#define DMAC_MODE_AUTO 0x0 /* DMA Auto Request Mode */
3128 +#define DMAC_MODE_BURST 0x4 /* DMA Burst Request Mode */
3129 +#define DMAC_MODE_TFER 0x8 /* DMA Transfer Request Mode */
3130 +
3131 +/* DMAS and DMASM register layout */
3132 +
3133 +#define DMAS_F 0x01 /* Finished */
3134 +#define DMAS_D 0x02 /* Done */
3135 +#define DMAS_C 0x04 /* Chain */
3136 +#define DMAS_E 0x08 /* Error */
3137 +#define DMAS_H 0x10 /* Halt */
3138 +
3139 +/* Polling count for DMAS_H bit in DMAS register after halting DMA */
3140 +#define DMA_HALT_TIMEOUT 500
3141 +
3142 +
3143 +static inline int rc32355_halt_dma(rc32355_dma_ch_t* ch)
3144 +{
3145 + int timeout=1;
3146 +
3147 + if (local_readl(&ch->dmac) & DMAC_RUN) {
3148 + local_writel(0, &ch->dmac);
3149 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
3150 + if (local_readl(&ch->dmas) & DMAS_H) {
3151 + local_writel(0, &ch->dmas);
3152 + break;
3153 + }
3154 + }
3155 + }
3156 +
3157 + return timeout ? 0 : 1;
3158 +}
3159 +
3160 +static inline void rc32355_start_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3161 +{
3162 + local_writel(0, &ch->dmandptr);
3163 + local_writel(dma_addr, &ch->dmadptr);
3164 +}
3165 +
3166 +static inline void rc32355_chain_dma(rc32355_dma_ch_t* ch, u32 dma_addr)
3167 +{
3168 + local_writel(dma_addr, &ch->dmandptr);
3169 +}
3170 +
3171 +
3172 +/* The following can be used to describe DMA channels 0 to 15, and the */
3173 +/* sub device's needed to select them in the DMADESC_DS_MASK field */
3174 +
3175 +#define DMA_CHAN_ATM01 0 /* ATM interface 0,1 chan */
3176 +
3177 +#define DMA_CHAN_ATM0IN 0 /* ATM interface 0 input */
3178 +#define DMA_DEV_ATM0IN 0 /* ATM interface 0 input */
3179 +
3180 +#define DMA_CHAN_ATM1IN 0 /* ATM interface 1 input */
3181 +#define DMA_DEV_ATM1IN 1 /* ATM interface 1 input */
3182 +
3183 +#define DMA_CHAN_ATM0OUT 0 /* ATM interface 0 output */
3184 +#define DMA_DEV_ATM0OUT 2 /* ATM interface 0 output */
3185 +
3186 +#define DMA_CHAN_ATM1OUT 0 /* ATM interface 1 output */
3187 +#define DMA_DEV_ATM1OUT 3 /* ATM interface 1 output */
3188 +
3189 +/* for entry in {0,1,2,3,4,5,6,7} - note 5,6,7 share with those below */
3190 +#define DMA_CHAN_ATMVCC(entry) ((entry)+1) /* ATM VC cache entry */
3191 +#define DMA_DEV_ATMVCC(entry) 0
3192 +
3193 +#define DMA_CHAN_MEMTOMEM 6 /* Memory to memory DMA */
3194 +#define DMA_DEV_MEMTOMEM 1 /* Memory to memory DMA */
3195 +
3196 +#define DMA_CHAN_ATMFMB0 7 /* ATM Frame Mode Buffer 0 */
3197 +#define DMA_DEV_ATMFMB0 1 /* ATM Frame Mode Buffer 0 */
3198 +
3199 +#define DMA_CHAN_ATMFMB1 8 /* ATM Frame Mode Buffer 1 */
3200 +#define DMA_DEV_ATMFMB1 1 /* ATM Frame Mode Buffer 1 */
3201 +
3202 +#define DMA_CHAN_ETHERIN 9 /* Ethernet input */
3203 +#define DMA_DEV_ETHERIN 0 /* Ethernet input */
3204 +
3205 +#define DMA_CHAN_ETHEROUT 10 /* Ethernet output */
3206 +#define DMA_DEV_ETHEROUT 0 /* Ethernet output */
3207 +
3208 +#define DMA_CHAN_TDMIN 11 /* TDM Bus input */
3209 +#define DMA_DEV_TDMIN 0 /* TDM Bus input */
3210 +
3211 +#define DMA_CHAN_TDMOUT 12 /* TDM Bus output */
3212 +#define DMA_DEV_TDMOUT 0 /* TDM Bus output */
3213 +
3214 +#define DMA_CHAN_USBIN 13 /* USB input */
3215 +#define DMA_DEV_USBIN 0 /* USB input */
3216 +
3217 +#define DMA_CHAN_USBOUT 14 /* USB output */
3218 +#define DMA_DEV_USBOUT 0 /* USB output */
3219 +
3220 +#define DMA_CHAN_EXTERN 15 /* External DMA */
3221 +#define DMA_DEV_EXTERN 0 /* External DMA */
3222 +
3223 +/*
3224 + * An RC32355 dma descriptor in system memory
3225 + */
3226 +typedef struct {
3227 + u32 cmdstat; /* control and status */
3228 + u32 curr_addr; /* current address of data */
3229 + u32 devcs; /* peripheral-specific control and status */
3230 + u32 link; /* link to next descriptor */
3231 +} rc32355_dma_desc_t;
3232 +
3233 +/* Values for the descriptor cmdstat word */
3234 +
3235 +#define DMADESC_F 0x80000000u /* Finished bit */
3236 +#define DMADESC_D 0x40000000u /* Done bit */
3237 +#define DMADESC_T 0x20000000u /* Terminated bit */
3238 +#define DMADESC_IOD 0x10000000u /* Interrupt On Done */
3239 +#define DMADESC_IOF 0x08000000u /* Interrupt On Finished */
3240 +#define DMADESC_COD 0x04000000u /* Chain On Done */
3241 +#define DMADESC_COF 0x02000000u /* Chain On Finished */
3242 +
3243 +#define DMADESC_DEVCMD_MASK 0x01C00000u /* Device Command mask */
3244 +#define DMADESC_DEVCMD_SHIFT 22 /* Device Command shift */
3245 +
3246 +#define DMADESC_DS_MASK 0x00300000u /* Device Select mask */
3247 +#define DMADESC_DS_SHIFT 20 /* Device Select shift */
3248 +
3249 +#define DMADESC_COUNT_MASK 0x0003FFFFu /* Byte Count mask */
3250 +#define DMADESC_COUNT_SHIFT 0 /* Byte Count shift */
3251 +
3252 +#define IS_DMA_FINISHED(X) ( ( (X) & DMADESC_F ) >> 31) /* F Bit */
3253 +#define IS_DMA_DONE(X) ( ( (X) & DMADESC_D ) >> 30) /* D Bit */
3254 +#define IS_DMA_TERMINATED(X) ( ( (X) & DMADESC_T ) >> 29) /* T Bit */
3255 +#define IS_DMA_USED(X) (((X) & (DMADESC_F | DMADESC_D | DMADESC_T)) != 0)
3256 +
3257 +#define DMA_DEVCMD(devcmd) \
3258 + (((devcmd) << DMADESC_DEVCMD_SHIFT) & DMADESC_DS_MASK)
3259 +#define DMA_DS(ds) \
3260 + (((ds) << DMADESC_DS_SHIFT) & DMADESC_DS_MASK)
3261 +#define DMA_COUNT(count) \
3262 + ((count) & DMADESC_COUNT_MASK)
3263 +
3264 +#endif /* RC32355_DMA_H */
3265 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h
3266 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 1970-01-01 01:00:00.000000000 +0100
3267 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355_eth.h 2006-03-20 14:25:10.000000000 +0100
3268 @@ -0,0 +1,442 @@
3269 +/**************************************************************************
3270 + *
3271 + * BRIEF MODULE DESCRIPTION
3272 + * Ethernet registers on IDT RC32355
3273 + *
3274 + * Copyright 2004 IDT Inc.
3275 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3276 + *
3277 + *
3278 + * This program is free software; you can redistribute it and/or modify it
3279 + * under the terms of the GNU General Public License as published by the
3280 + * Free Software Foundation; either version 2 of the License, or (at your
3281 + * option) any later version.
3282 + *
3283 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3284 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3285 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3286 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3287 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3288 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3289 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3290 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3291 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3292 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3293 + *
3294 + * You should have received a copy of the GNU General Public License along
3295 + * with this program; if not, write to the Free Software Foundation, Inc.,
3296 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3297 + *
3298 + *
3299 + * May 2004 rkt
3300 + * Initial Release
3301 + *
3302 + **************************************************************************
3303 + */
3304 +
3305 +
3306 +#ifndef RC32355_ETHER_H
3307 +#define RC32355_ETHER_H
3308 +
3309 +#include <asm/idt-boards/rc32300/rc32355_dma.h>
3310 +
3311 +/*
3312 + * A partial image of the RC32355 ethernet registers
3313 + */
3314 +typedef struct {
3315 + u32 ethintfc;
3316 + u32 ethfifott;
3317 + u32 etharc;
3318 + u32 ethhash0;
3319 + u32 ethhash1;
3320 + u32 ethfifost;
3321 + u32 ethfifos;
3322 + u32 ethodeops;
3323 + u32 ethis;
3324 + u32 ethos;
3325 + u32 ethmcp;
3326 + u32 _u1;
3327 + u32 ethid;
3328 + u32 _u2;
3329 + u32 _u3;
3330 + u32 _u4;
3331 + u32 ethod;
3332 + u32 _u5;
3333 + u32 _u6;
3334 + u32 _u7;
3335 + u32 ethodeop;
3336 + u32 _u8[43];
3337 + u32 ethsal0;
3338 + u32 ethsah0;
3339 + u32 ethsal1;
3340 + u32 ethsah1;
3341 + u32 ethsal2;
3342 + u32 ethsah2;
3343 + u32 ethsal3;
3344 + u32 ethsah3;
3345 + u32 ethrbc;
3346 + u32 ethrpc;
3347 + u32 ethrupc;
3348 + u32 ethrfc;
3349 + u32 ethtbc;
3350 + u32 ethgpf;
3351 + u32 _u9[50];
3352 + u32 ethmac1;
3353 + u32 ethmac2;
3354 + u32 ethipgt;
3355 + u32 ethipgr;
3356 + u32 ethclrt;
3357 + u32 ethmaxf;
3358 + u32 _u10;
3359 + u32 ethmtest;
3360 + u32 miimcfg;
3361 + u32 miimcmd;
3362 + u32 miimaddr;
3363 + u32 miimwtd;
3364 + u32 miimrdd;
3365 + u32 miimind;
3366 + u32 _u11;
3367 + u32 _u12;
3368 + u32 ethcfsa0;
3369 + u32 ethcfsa1;
3370 + u32 ethcfsa2;
3371 +} rc32355_eth_regs_t;
3372 +
3373 +#define rc32355_eth_regs ((rc32355_eth_regs_t*)KSEG1ADDR(RC32355_ETH_BASE))
3374 +
3375 +#define ETH_INTFC (RC32355_ETH_BASE + 0x000) /* INTerFace Control */
3376 +#define ETH_FIFOTT (RC32355_ETH_BASE + 0x004) /* FIFO Transmit Threshold */
3377 +#define ETH_ARC (RC32355_ETH_BASE + 0x008) /* Address Recognition Ctrl */
3378 +#define ETH_HASH0 (RC32355_ETH_BASE + 0x00C) /* 32 multicast Hash bits */
3379 +#define ETH_HASH1 (RC32355_ETH_BASE + 0x010) /* another 32 Hash bits */
3380 +#define ETH_FIFOST (RC32355_ETH_BASE + 0x014) /* FIFO Status Threshold */
3381 +#define ETH_FIFOS (RC32355_ETH_BASE + 0x018) /* FIFO Status Register */
3382 +#define ETH_ODEOPS (RC32355_ETH_BASE + 0x01C) /* Out Data End-Of-Pkt Size */
3383 +#define ETH_IS (RC32355_ETH_BASE + 0x020) /* Input Status */
3384 +#define ETH_OS (RC32355_ETH_BASE + 0x024) /* Output Status */
3385 +#define ETH_MCP (RC32355_ETH_BASE + 0x028) /* Managemt Clock Prescaler */
3386 +#define ETH_ID (RC32355_ETH_BASE + 0x030) /* Input Data register */
3387 +#define ETH_OD (RC32355_ETH_BASE + 0x040) /* Output Data register */
3388 +#define ETH_ODEOP (RC32355_ETH_BASE + 0x050) /* OD End-Of-Packet Size */
3389 +
3390 +/* for n in { 0, 1, 2, 3 } */
3391 +#define ETH_SAL(n) (RC32355_ETH_BASE + 0x100 + (n * 8)) /* Stn Address 2-5 */
3392 +#define ETH_SAH(n) (RC32355_ETH_BASE + 0x104 + (n * 8)) /* Stn Address 0-1 */
3393 +
3394 +#define ETH_RBC (RC32355_ETH_BASE + 0x120) /* Receive Byte Count */
3395 +#define ETH_RPC (RC32355_ETH_BASE + 0x124) /* Receive Packet Count */
3396 +#define ETH_RUPC (RC32355_ETH_BASE + 0x128) /* Rx Undersized Pkt count */
3397 +#define ETH_RFC (RC32355_ETH_BASE + 0x12C) /* Receive Fragment Count */
3398 +#define ETH_TBC (RC32355_ETH_BASE + 0x130) /* Transmit Byte Count */
3399 +#define ETH_GPF (RC32355_ETH_BASE + 0x134) /* Generate Pause Frame */
3400 +#define ETH_MAC1 (RC32355_ETH_BASE + 0x200) /* Medium Access Control 1 */
3401 +#define ETH_MAC2 (RC32355_ETH_BASE + 0x204) /* Medium Access Control 2 */
3402 +#define ETH_IPGT (RC32355_ETH_BASE + 0x208) /* Back-to-back InterPkt Gap */
3403 +#define ETH_IPGR (RC32355_ETH_BASE + 0x20C) /* Non " InterPkt Gap */
3404 +#define ETH_CLRT (RC32355_ETH_BASE + 0x210) /* Collis'n Window and Retry */
3405 +#define ETH_MAXF (RC32355_ETH_BASE + 0x214) /* Maximum Frame Length */
3406 +#define ETH_MTEST (RC32355_ETH_BASE + 0x21C) /* MAC Test */
3407 +
3408 +#define ETHMIIM_CFG (RC32355_ETH_BASE + 0x220) /* MII Mgmt Configuration */
3409 +#define ETHMIIM_CMD (RC32355_ETH_BASE + 0x224) /* MII Mgmt Command */
3410 +#define ETHMIIM_ADDR (RC32355_ETH_BASE + 0x228) /* MII Mgmt Address */
3411 +#define ETHMIIM_WTD (RC32355_ETH_BASE + 0x22C) /* MII Mgmt Write Data */
3412 +#define ETHMIIM_RDD (RC32355_ETH_BASE + 0x230) /* MII Mgmt Read Data */
3413 +#define ETHMIIM_IND (RC32355_ETH_BASE + 0x234) /* MII Mgmt Indicators */
3414 +
3415 +/* for n in { 0, 1, 2 } */
3416 +#define ETH_CFSA(n) (RC32355_ETH_BASE + 0x240 + ((n) * 4)) /* Station Addr */
3417 +
3418 +
3419 +/*
3420 + * Register Interpretations follow
3421 + */
3422 +
3423 +/******************************************************************************
3424 + * ETHINTFC register
3425 + *****************************************************************************/
3426 +
3427 +#define ETHERINTFC_EN (1<<0)
3428 +#define ETHERINTFC_ITS (1<<1)
3429 +#define ETHERINTFC_RES (1<<2)
3430 +#define ETHERINTFC_RIP (1<<2)
3431 +#define ETHERINTFC_JAM (1<<3)
3432 +
3433 +/******************************************************************************
3434 + * ETHFIFOTT register
3435 + *****************************************************************************/
3436 +
3437 +#define ETHERFIFOTT_TTH(v) (((v)&0x3f)<<0)
3438 +
3439 +/******************************************************************************
3440 + * ETHARC register
3441 + *****************************************************************************/
3442 +
3443 +#define ETHERARC_PRO (1<<0)
3444 +#define ETHERARC_AM (1<<1)
3445 +#define ETHERARC_AFM (1<<2)
3446 +#define ETHERARC_AB (1<<3)
3447 +
3448 +/******************************************************************************
3449 + * ETHHASH registers
3450 + *****************************************************************************/
3451 +
3452 +#define ETHERHASH0(v) (((v)&0xffff)<<0)
3453 +#define ETHERHASH1(v) (((v)&0xffff)<<0)
3454 +
3455 +/******************************************************************************
3456 + * ETHSA registers
3457 + *****************************************************************************/
3458 +
3459 +#define ETHERSAL0(v) (((v)&0xffff)<<0)
3460 +#define ETHERSAL1(v) (((v)&0xffff)<<0)
3461 +#define ETHERSAL2(v) (((v)&0xffff)<<0)
3462 +#define ETHERSAL3(v) (((v)&0xffff)<<0)
3463 +#define ETHERSAH0(v) (((v)&0xff)<<0)
3464 +#define ETHERSAH1(v) (((v)&0xff)<<0)
3465 +#define ETHERSAH2(v) (((v)&0xff)<<0)
3466 +#define ETHERSAH3(v) (((v)&0xff)<<0)
3467 +
3468 +/******************************************************************************
3469 + * ETHFIFOST register
3470 + *****************************************************************************/
3471 +
3472 +#define ETHERFIFOST_IRTH(v) (((v)&0x3f)<<0)
3473 +#define ETHERFIFOST_ORTH(v) (((v)&0x3f)<<16)
3474 +
3475 +/******************************************************************************
3476 + * ETHFIFOS register
3477 + *****************************************************************************/
3478 +
3479 +#define ETHERFIFOS_IR (1<<0)
3480 +#define ETHERFIFOS_OR (1<<1)
3481 +#define ETHERFIFOS_OVR (1<<2)
3482 +#define ETHERFIFOS_UND (1<<3)
3483 +
3484 +/******************************************************************************
3485 + * DATA registers
3486 + *****************************************************************************/
3487 +
3488 +#define ETHERID(v) (((v)&0xffff)<<0)
3489 +#define ETHEROD(v) (((v)&0xffff)<<0)
3490 +
3491 +/******************************************************************************
3492 + * ETHODEOPS register
3493 + *****************************************************************************/
3494 +
3495 +#define ETHERODEOPS_SIZE(v) (((v)&0x3)<<0)
3496 +
3497 +/******************************************************************************
3498 + * ETHODEOP register
3499 + *****************************************************************************/
3500 +
3501 +#define ETHERODEOP(v) (((v)&0xffff)<<0)
3502 +
3503 +/******************************************************************************
3504 + * ETHIS register
3505 + *****************************************************************************/
3506 +
3507 +#define ETHERIS_EOP (1<<0)
3508 +#define ETHERIS_ROK (1<<2)
3509 +#define ETHERIS_FM (1<<3)
3510 +#define ETHERIS_MP (1<<4)
3511 +#define ETHERIS_BP (1<<5)
3512 +#define ETHERIS_VLT (1<<6)
3513 +#define ETHERIS_CF (1<<7)
3514 +#define ETHERIS_OVR (1<<8)
3515 +#define ETHERIS_CRC (1<<9)
3516 +#define ETHERIS_CV (1<<10)
3517 +#define ETHERIS_DB (1<<11)
3518 +#define ETHERIS_LE (1<<12)
3519 +#define ETHERIS_LOR (1<<13)
3520 +#define ETHERIS_SIZE(v) (((v)&0x3)<<14)
3521 +#define ETHERIS_LENGTH(v) (((v)&0xff)<<16)
3522 +
3523 +/******************************************************************************
3524 + * ETHOS register
3525 + *****************************************************************************/
3526 +
3527 +#define ETHEROS_T (1<<0)
3528 +#define ETHEROS_TOK (1<<6)
3529 +#define ETHEROS_MP (1<<7)
3530 +#define ETHEROS_BP (1<<8)
3531 +#define ETHEROS_UND (1<<9)
3532 +#define ETHEROS_OF (1<<10)
3533 +#define ETHEROS_ED (1<<11)
3534 +#define ETHEROS_EC (1<<12)
3535 +#define ETHEROS_LC (1<<13)
3536 +#define ETHEROS_TD (1<<14)
3537 +#define ETHEROS_CRC (1<<15)
3538 +#define ETHEROS_LE (1<<16)
3539 +#define ETHEROS_CC(v) (((v)&0xf)<<17)
3540 +#define ETHEROS_PFD (1<<21)
3541 +
3542 +/******************************************************************************
3543 + * Statistics registers
3544 + *****************************************************************************/
3545 +
3546 +#define ETHERRBC(v) (((v)&0xffff)<<0)
3547 +#define ETHERRPC(v) (((v)&0xffff)<<0)
3548 +#define ETHERRUPC(v) (((v)&0xffff)<<0)
3549 +#define ETHERRFC(v) (((v)&0xffff)<<0)
3550 +#define ETHERTBC(v) (((v)&0xffff)<<0)
3551 +
3552 +/******************************************************************************
3553 + * ETHGPF register
3554 + *****************************************************************************/
3555 +
3556 +#define ETHERGPF_PTV(v) (((v)&0xff)<<0)
3557 +
3558 +/******************************************************************************
3559 + * MAC registers
3560 + *****************************************************************************/
3561 +//ETHMAC1
3562 +#define ETHERMAC1_RE (1<<0)
3563 +#define ETHERMAC1_PAF (1<<1)
3564 +#define ETHERMAC1_RFC (1<<2)
3565 +#define ETHERMAC1_TFC (1<<3)
3566 +#define ETHERMAC1_LB (1<<4)
3567 +#define ETHERMAC1_MR (1<<15)
3568 +
3569 +//ETHMAC2
3570 +#define ETHERMAC2_FD (1<<0)
3571 +#define ETHERMAC2_FLC (1<<1)
3572 +#define ETHERMAC2_HFE (1<<2)
3573 +#define ETHERMAC2_DC (1<<3)
3574 +#define ETHERMAC2_CEN (1<<4)
3575 +#define ETHERMAC2_PE (1<<5)
3576 +#define ETHERMAC2_VPE (1<<6)
3577 +#define ETHERMAC2_APE (1<<7)
3578 +#define ETHERMAC2_PPE (1<<8)
3579 +#define ETHERMAC2_LPE (1<<9)
3580 +#define ETHERMAC2_NB (1<<12)
3581 +#define ETHERMAC2_BP (1<<13)
3582 +#define ETHERMAC2_ED (1<<14)
3583 +
3584 +//ETHIPGT
3585 +#define ETHERIPGT(v) (((v)&0x3f)<<0)
3586 +
3587 +//ETHIPGR
3588 +#define ETHERIPGR_IPGR1(v) (((v)&0x3f)<<0)
3589 +#define ETHERIPGR_IPGR2(v) (((v)&0x3f)<<8)
3590 +
3591 +//ETHCLRT
3592 +#define ETHERCLRT_MAXRET(v) (((v)&0x3f)<<0)
3593 +#define ETHERCLRT_COLWIN(v) (((v)&0x3f)<<8)
3594 +
3595 +//ETHMAXF
3596 +#define ETHERMAXF(v) (((v)&0x3f)<<0)
3597 +
3598 +//ETHMTEST
3599 +#define ETHERMTEST_TB (1<<2)
3600 +
3601 +//ETHMCP
3602 +#define ETHERMCP_DIV(v) (((v)&0xff)<<0)
3603 +
3604 +//MIIMCFG
3605 +#define ETHERMIIMCFG_CS(v) (((v)&0x3)<<2)
3606 +#define ETHERMIIMCFG_R (1<<15)
3607 +
3608 +//MIIMCMD
3609 +#define ETHERMIIMCMD_RD (1<<0)
3610 +#define ETHERMIIMCMD_SCN (1<<1)
3611 +
3612 +//MIIMADDR
3613 +#define ETHERMIIMADDR_REGADDR(v) (((v)&0x1f)<<0)
3614 +#define ETHERMIIMADDR_PHYADDR(v) (((v)&0x1f)<<8)
3615 +
3616 +//MIIMWTD
3617 +#define ETHERMIIMWTD(v) (((v)&0xff)<<0)
3618 +
3619 +//MIIMRDD
3620 +#define ETHERMIIMRDD(v) (((v)&0xff)<<0)
3621 +
3622 +//MIIMIND
3623 +#define ETHERMIIMIND_BSY (1<<0)
3624 +#define ETHERMIIMIND_SCN (1<<1)
3625 +#define ETHERMIIMIND_NV (1<<2)
3626 +
3627 +//DMA DEVCS IN
3628 +#define ETHERDMA_IN_LENGTH(v) (((v)&0xffff)<<16)
3629 +#define ETHERDMA_IN_CES (1<<14)
3630 +#define ETHERDMA_IN_LOR (1<<13)
3631 +#define ETHERDMA_IN_LE (1<<12)
3632 +#define ETHERDMA_IN_DB (1<<11)
3633 +#define ETHERDMA_IN_CV (1<<10)
3634 +#define ETHERDMA_IN_CRC (1<<9)
3635 +#define ETHERDMA_IN_OVR (1<<8)
3636 +#define ETHERDMA_IN_CF (1<<7)
3637 +#define ETHERDMA_IN_VLT (1<<6)
3638 +#define ETHERDMA_IN_BP (1<<5)
3639 +#define ETHERDMA_IN_MP (1<<4)
3640 +#define ETHERDMA_IN_FM (1<<3)
3641 +#define ETHERDMA_IN_ROK (1<<2)
3642 +#define ETHERDMA_IN_LD (1<<1)
3643 +#define ETHERDMA_IN_FD (1<<0)
3644 +
3645 +//DMA DEVCS OUT
3646 +#define ETHERDMA_OUT_CC(v) (((v)&0xf)<<17)
3647 +#define ETHERDMA_OUT_CNT 0x001e0000
3648 +#define ETHERDMA_OUT_SHFT 17
3649 +#define ETHERDMA_OUT_LE (1<<16)
3650 +
3651 +#define ETHERDMA_OUT_CRC (1<<15)
3652 +#define ETHERDMA_OUT_TD (1<<14)
3653 +#define ETHERDMA_OUT_LC (1<<13)
3654 +#define ETHERDMA_OUT_EC (1<<12)
3655 +#define ETHERDMA_OUT_ED (1<<11)
3656 +#define ETHERDMA_OUT_OF (1<<10)
3657 +#define ETHERDMA_OUT_UND (1<<9)
3658 +#define ETHERDMA_OUT_BP (1<<8)
3659 +#define ETHERDMA_OUT_MP (1<<7)
3660 +#define ETHERDMA_OUT_TOK (1<<6)
3661 +#define ETHERDMA_OUT_HEN (1<<5)
3662 +#define ETHERDMA_OUT_CEN (1<<4)
3663 +#define ETHERDMA_OUT_PEN (1<<3)
3664 +#define ETHERDMA_OUT_OEN (1<<2)
3665 +#define ETHERDMA_OUT_LD (1<<1)
3666 +#define ETHERDMA_OUT_FD (1<<0)
3667 +
3668 +#define RCV_ERRS \
3669 + (ETHERDMA_IN_OVR | ETHERDMA_IN_CRC | ETHERDMA_IN_CV | ETHERDMA_IN_LE)
3670 +#define TX_ERRS \
3671 + (ETHERDMA_OUT_LC | ETHERDMA_OUT_EC | ETHERDMA_OUT_ED | \
3672 + ETHERDMA_OUT_OF | ETHERDMA_OUT_UND)
3673 +
3674 +#define IS_RCV_ROK(X) (((X) & (1<<2)) >> 2) /* Receive Okay */
3675 +#define IS_RCV_FM(X) (((X) & (1<<3)) >> 3) /* Is Filter Match */
3676 +#define IS_RCV_MP(X) (((X) & (1<<4)) >> 4) /* Is it MP */
3677 +#define IS_RCV_BP(X) (((X) & (1<<5)) >> 5) /* Is it BP */
3678 +#define IS_RCV_VLT(X) (((X) & (1<<6)) >> 6) /* VLAN Tag Detect */
3679 +#define IS_RCV_CF(X) (((X) & (1<<7)) >> 7) /* Control Frame */
3680 +#define IS_RCV_OVR_ERR(X) (((X) & (1<<8)) >> 8) /* Receive Overflow */
3681 +#define IS_RCV_CRC_ERR(X) (((X) & (1<<9)) >> 9) /* CRC Error */
3682 +#define IS_RCV_CV_ERR(X) (((X) & (1<<10))>>10) /* Code Violation */
3683 +#define IS_RCV_DB_ERR(X) (((X) & (1<<11))>>11) /* Dribble Bits */
3684 +#define IS_RCV_LE_ERR(X) (((X) & (1<<12))>>12) /* Length error */
3685 +#define IS_RCV_LOR_ERR(X) (((X) & (1<<13))>>13) /* Length Out of
3686 + Range */
3687 +#define IS_RCV_CES_ERR(X) (((X) & (1<<14))>>14) /* Preamble error */
3688 +#define RCVPKT_LENGTH(X) (((X) & 0xFFFF0000)>>16) /* Length of the
3689 + received packet */
3690 +
3691 +#define IS_TX_TOK(X) (((X) & (1<<6) ) >> 6 ) /* Transmit Okay */
3692 +#define IS_TX_MP(X) (((X) & (1<<7) ) >> 7 ) /* Multicast */
3693 +
3694 +#define IS_TX_BP(X) (((X) & (1<<8) ) >> 8 ) /* Broadcast */
3695 +#define IS_TX_UND_ERR(X) (((X) & (1<<9) ) >> 9 ) /* Transmit FIFO
3696 + Underflow */
3697 +#define IS_TX_OF_ERR(X) (((X) & (1<<10)) >>10 ) /* Oversized frame */
3698 +#define IS_TX_ED_ERR(X) (((X) & (1<<11)) >>11 ) /* Excessive
3699 + deferral */
3700 +#define IS_TX_EC_ERR(X) (((X) & (1<<12)) >>12 ) /* Excessive
3701 + collisions */
3702 +#define IS_TX_LC_ERR(X) (((X) & (1<<13)) >>13 ) /* Late Collision */
3703 +#define IS_TX_TD_ERR(X) (((X) & (1<<14)) >>14 ) /* Transmit deferred*/
3704 +#define IS_TX_CRC_ERR(X) (((X) & (1<<15)) >>15 ) /* CRC Error */
3705 +#define IS_TX_LE_ERR(X) (((X) & (1<<16)) >>16 ) /* Length Error */
3706 +
3707 +#define TX_COLLISION_COUNT(X) (((X) & 0x001E0000u)>>17) /* Collision Count */
3708 +
3709 +#endif /* RC32355_ETHER_H */
3710 +
3711 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h
3712 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32355.h 1970-01-01 01:00:00.000000000 +0100
3713 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32355.h 2006-03-20 14:25:10.000000000 +0100
3714 @@ -0,0 +1,177 @@
3715 +/**************************************************************************
3716 + *
3717 + * BRIEF MODULE DESCRIPTION
3718 + * Definitions for IDT RC32355 CPU.
3719 + *
3720 + * Copyright 2004 IDT Inc.
3721 + * Author: Integrated Device Technology Inc. rischelp@idt.com
3722 + *
3723 + *
3724 + * This program is free software; you can redistribute it and/or modify it
3725 + * under the terms of the GNU General Public License as published by the
3726 + * Free Software Foundation; either version 2 of the License, or (at your
3727 + * option) any later version.
3728 + *
3729 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3730 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3731 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3732 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3733 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3734 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3735 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3736 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3737 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3738 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3739 + *
3740 + * You should have received a copy of the GNU General Public License along
3741 + * with this program; if not, write to the Free Software Foundation, Inc.,
3742 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3743 + *
3744 + *
3745 + * May 2004 rkt
3746 + * Initial Release
3747 + *
3748 + **************************************************************************
3749 + */
3750 +
3751 +
3752 +#ifndef _RC32355_H_
3753 +#define _RC32355_H_
3754 +
3755 +#include <linux/delay.h>
3756 +#include <asm/io.h>
3757 +
3758 +/* Base address of internal registers */
3759 +#define RC32355_REG_BASE 0x18000000
3760 +
3761 +/* System ID Registers */
3762 +#define CPU_SYSID (RC32355_REG_BASE + 0x00018)
3763 +#define CPU_BTADDR (RC32355_REG_BASE + 0x0001c)
3764 +#define CPU_REV (RC32355_REG_BASE + 0x0002c)
3765 +
3766 +/* Reset Controller */
3767 +#define RESET_CNTL (RC32355_REG_BASE + 0x08000)
3768 +
3769 +/* Device Controller */
3770 +#define DEV0_BASE (RC32355_REG_BASE + 0x10000)
3771 +#define DEV0_MASK (RC32355_REG_BASE + 0x10004)
3772 +#define DEV0_CNTL (RC32355_REG_BASE + 0x10008)
3773 +#define DEV0_TIMING (RC32355_REG_BASE + 0x1000c)
3774 +#define DEV_REG_OFFSET 0x10
3775 +
3776 +/* SDRAM Controller */
3777 +#define SDRAM0_BASE (RC32355_REG_BASE + 0x18000)
3778 +#define SDRAM0_MASK (RC32355_REG_BASE + 0x18004)
3779 +#define SDRAM1_BASE (RC32355_REG_BASE + 0x18008)
3780 +#define SDRAM1_MASK (RC32355_REG_BASE + 0x1800c)
3781 +#define SDRAM_CNTL (RC32355_REG_BASE + 0x18010)
3782 +
3783 +/* Bus Arbiter */
3784 +#define BUS_ARB_CNTL0 (RC32355_REG_BASE + 0x20000)
3785 +#define BUS_ARB_CNTL1 (RC32355_REG_BASE + 0x20004)
3786 +
3787 +/* Counters/Timers */
3788 +#define TIMER0_COUNT (RC32355_REG_BASE + 0x28000)
3789 +#define TIMER0_COMPARE (RC32355_REG_BASE + 0x28004)
3790 +#define TIMER0_CNTL (RC32355_REG_BASE + 0x28008)
3791 +#define TIMER_REG_OFFSET 0x0C
3792 +
3793 +/* System Integrity */
3794 +
3795 +/* Interrupt Controller */
3796 +#define IC_GROUP0_PEND (RC32355_REG_BASE + 0x30000)
3797 +#define IC_GROUP0_MASK (RC32355_REG_BASE + 0x30004)
3798 +#define IC_GROUP_OFFSET 0x08
3799 +
3800 +#define NUM_INTR_GROUPS 5
3801 +/*
3802 + * The IRQ mapping is as follows:
3803 + *
3804 + * IRQ Mapped To
3805 + * --- -------------------
3806 + * 0 SW0 (IP0) SW0 intr
3807 + * 1 SW1 (IP1) SW1 intr
3808 + * - Int0 (IP2) mapped to GROUP0_IRQ_BASE
3809 + * - Int1 (IP3) mapped to GROUP1_IRQ_BASE
3810 + * - Int2 (IP4) mapped to GROUP2_IRQ_BASE
3811 + * - Int3 (IP5) mapped to GROUP3_IRQ_BASE
3812 + * - Int4 (IP6) mapped to GROUP4_IRQ_BASE
3813 + * 7 Int5 (IP7) CP0 Timer
3814 + *
3815 + * IRQ's 8 and up are all mapped to Int0-4 (IP2-IP6), which
3816 + * internally on the RC32355 is routed to the Expansion
3817 + * Interrupt Controller.
3818 + */
3819 +#define MIPS_CPU_TIMER_IRQ 7
3820 +
3821 +#define GROUP0_IRQ_BASE 8 // Counter/Timers, UCW
3822 +#define GROUP1_IRQ_BASE (GROUP0_IRQ_BASE + 32) // DMA
3823 +#define GROUP2_IRQ_BASE (GROUP1_IRQ_BASE + 32) // ATM
3824 +#define GROUP3_IRQ_BASE (GROUP2_IRQ_BASE + 32) // TDM, Eth, USB, UARTs, I2C
3825 +#define GROUP4_IRQ_BASE (GROUP3_IRQ_BASE + 32) // GPIO
3826 +
3827 +#define RC32355_NR_IRQS (GROUP4_IRQ_BASE + 32)
3828 +
3829 +/* DMA - see rc32355_dma.h for full list of registers */
3830 +
3831 +#define RC32355_DMA_BASE (RC32355_REG_BASE + 0x38000)
3832 +#define DMA_CHAN_OFFSET 0x14
3833 +
3834 +/* GPIO Controller */
3835 +
3836 +/* TDM Bus */
3837 +
3838 +/* 16550 UARTs */
3839 +#ifdef __MIPSEB__
3840 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50003)
3841 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50023)
3842 +#else
3843 +#define RC32300_UART0_BASE (RC32355_REG_BASE + 0x50000)
3844 +#define RC32300_UART1_BASE (RC32355_REG_BASE + 0x50020)
3845 +#endif
3846 +
3847 +#define RC32300_UART0_IRQ (GROUP3_IRQ_BASE + 14)
3848 +#define RC32300_UART1_IRQ (GROUP3_IRQ_BASE + 17)
3849 +
3850 +/* ATM */
3851 +
3852 +/* Ethernet - see rc32355_eth.h for full list of registers */
3853 +
3854 +#define RC32355_ETH_BASE (RC32355_REG_BASE + 0x60000)
3855 +
3856 +
3857 +#define IDT_CLOCK_MULT 2
3858 +
3859 +/* Memory map of 79EB355 board */
3860 +
3861 +/* DRAM */
3862 +#define RAM_BASE 0x00000000
3863 +#define RAM_SIZE (32*1024*1024)
3864 +
3865 +/* SRAM (device 1) */
3866 +#define SRAM_BASE 0x02000000
3867 +#define SRAM_SIZE 0x00100000
3868 +
3869 +/* FLASH (device 2) */
3870 +#define FLASH_BASE 0x0C000000
3871 +#define FLASH_SIZE 0x00C00000
3872 +
3873 +/* ATM PHY (device 4) */
3874 +#define ATM_PHY_BASE 0x14000000
3875 +
3876 +/* TDM switch (device 3) */
3877 +#define TDM_BASE 0x1A000000
3878 +
3879 +/* LCD panel (device 3) */
3880 +#define LCD_BASE 0x1A002000
3881 +
3882 +/* RTC (DS1511W) (device 3) */
3883 +#define RTC_BASE 0x1A004000
3884 +
3885 +/* NVRAM (256 bytes internal to the DS1511 RTC) */
3886 +#define NVRAM_ADDR RTC_BASE + 0x10
3887 +#define NVRAM_DATA RTC_BASE + 0x13
3888 +#define NVRAM_ENVSIZE_OFF 4
3889 +#define NVRAM_ENVSTART_OFF 32
3890 +
3891 +#endif /* _RC32355_H_ */
3892 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h
3893 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 1970-01-01 01:00:00.000000000 +0100
3894 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma.h 2006-03-20 14:25:10.000000000 +0100
3895 @@ -0,0 +1,226 @@
3896 +/**************************************************************************
3897 + *
3898 + * BRIEF MODULE DESCRIPTION
3899 + * RC32365/336 DMA hardware abstraction.
3900 + *
3901 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
3902 + *
3903 + * This program is free software; you can redistribute it and/or modify it
3904 + * under the terms of the GNU General Public License as published by the
3905 + * Free Software Foundation; either version 2 of the License, or (at your
3906 + * option) any later version.
3907 + *
3908 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3909 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3910 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3911 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3912 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3913 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3914 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3915 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3916 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3917 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3918 + *
3919 + * You should have received a copy of the GNU General Public License along
3920 + * with this program; if not, write to the Free Software Foundation, Inc.,
3921 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3922 + *
3923 + *
3924 + **************************************************************************
3925 + * May 2004 P. Sadik.
3926 + *
3927 + * Initial Release
3928 + *
3929 + *
3930 + *
3931 + **************************************************************************
3932 + */
3933 +
3934 +#ifndef __IDT_RC32365_DMA_H__
3935 +#define __IDT_RC32365_DMA_H__
3936 +
3937 +enum
3938 +{
3939 + DMA0_PhysicalAddress = 0x18038000,
3940 + DMA_PhysicalAddress = DMA0_PhysicalAddress, // Default
3941 +
3942 + DMA0_VirtualAddress = 0xb8038000,
3943 + DMA_VirtualAddress = DMA0_VirtualAddress, // Default
3944 +} ;
3945 +
3946 +/*
3947 + * DMA descriptor (in physical memory).
3948 + */
3949 +
3950 +typedef struct DMAD_s
3951 +{
3952 + u32 control ; // Control. use DMAD_*
3953 + u32 ca ; // Current Address.
3954 + u32 devcs ; // Device control and status.
3955 + u32 link ; // Next descriptor in chain.
3956 +} volatile *DMAD_t ;
3957 +
3958 +enum
3959 +{
3960 + DMAD_size = sizeof (struct DMAD_s),
3961 + DMAD_count_b = 0, // in DMAD_t -> control
3962 + DMAD_count_m = 0x0003ffff, // in DMAD_t -> control
3963 + DMAD_ds_b = 20, // in DMAD_t -> control
3964 + DMAD_ds_m = 0x00300000, // in DMAD_t -> control
3965 + DMAD_ds_extToMem0_v = 0,
3966 + DMAD_ds_memToExt0_v = 1,
3967 + DMAD_ds_extToMem1_v = 0,
3968 + DMAD_ds_memToExt1_v = 1,
3969 + DMAD_ds_ethRcv0_v = 0,
3970 + DMAD_ds_ethXmt0_v = 0,
3971 + DMAD_ds_ethRcv1_v = 0,
3972 + DMAD_ds_ethXmt2_v = 0,
3973 + DMAD_ds_memToFifo_v = 0,
3974 + DMAD_ds_fifoToMem_v = 0,
3975 + DMAD_ds_rng_de_v = 1,//randomNumberGenerator on LC/DE
3976 + DMAD_ds_pciToMem_v = 0,
3977 + DMAD_ds_memToPci_v = 0,
3978 + DMAD_ds_securityInput_v = 0,
3979 + DMAD_ds_securityOutput_v = 0,
3980 + DMAD_ds_rng_se_v = 0,//randomNumberGenerator on SE
3981 +
3982 + DMAD_devcmd_b = 22, // in DMAD_t -> control
3983 + DMAD_devcmd_m = 0x01c00000, // in DMAD_t -> control
3984 + DMAD_devcmd_byte_v = 0, //memory-to-memory
3985 + DMAD_devcmd_halfword_v = 1, //memory-to-memory
3986 + DMAD_devcmd_word_v = 2, //memory-to-memory
3987 + DMAD_devcmd_2words_v = 3, //memory-to-memory
3988 + DMAD_devcmd_4words_v = 4, //memory-to-memory
3989 + DMAD_devcmd_6words_v = 5, //memory-to-memory
3990 + DMAD_devcmd_8words_v = 6, //memory-to-memory
3991 + DMAD_devcmd_16words_v = 7, //memory-to-memory
3992 + DMAD_cof_b = 25, // chain on finished
3993 + DMAD_cof_m = 0x02000000, //
3994 + DMAD_cod_b = 26, // chain on done
3995 + DMAD_cod_m = 0x04000000, //
3996 + DMAD_iof_b = 27, // interrupt on finished
3997 + DMAD_iof_m = 0x08000000, //
3998 + DMAD_iod_b = 28, // interrupt on done
3999 + DMAD_iod_m = 0x10000000, //
4000 + DMAD_t_b = 29, // terminated
4001 + DMAD_t_m = 0x20000000, //
4002 + DMAD_d_b = 30, // done
4003 + DMAD_d_m = 0x40000000, //
4004 + DMAD_f_b = 31, // finished
4005 + DMAD_f_m = 0x80000000, //
4006 +} ;
4007 +
4008 +/*
4009 + * DMA register (within Internal Register Map).
4010 + */
4011 +
4012 +struct DMA_Chan_s
4013 +{
4014 + u32 dmac ; // Control.
4015 + u32 dmas ; // Status.
4016 + u32 dmasm ; // Mask.
4017 + u32 dmadptr ; // Descriptor pointer.
4018 + u32 dmandptr ; // Next descriptor pointer.
4019 +};
4020 +
4021 +typedef struct DMA_Chan_s volatile *DMA_Chan_t ;
4022 +
4023 +//DMA_Channels use DMACH_count instead
4024 +
4025 +enum
4026 +{
4027 + DMAC_run_b = 0, //
4028 + DMAC_run_m = 0x00000001, //
4029 + DMAC_dm_b = 1, // done mask
4030 + DMAC_dm_m = 0x00000002, //
4031 + DMAC_mode_b = 2, //
4032 + DMAC_mode_m = 0x0000000c, //
4033 + DMAC_mode_auto_v = 0,
4034 + DMAC_mode_burst_v = 1,
4035 + DMAC_mode_transfer_v = 2, //usually used
4036 + DMAC_mode_reserved_v = 3,
4037 + DMAC_a_b = 4, //
4038 + DMAC_a_m = 0x00000010, //
4039 +
4040 + DMAS_f_b = 0, // finished (sticky)
4041 + DMAS_f_m = 0x00000001, //
4042 + DMAS_d_b = 1, // done (sticky)
4043 + DMAS_d_m = 0x00000002, //
4044 + DMAS_c_b = 2, // chain (sticky)
4045 + DMAS_c_m = 0x00000004, //
4046 + DMAS_e_b = 3, // error (sticky)
4047 + DMAS_e_m = 0x00000008, //
4048 + DMAS_h_b = 4, // halt (sticky)
4049 + DMAS_h_m = 0x00000010, //
4050 +
4051 + DMASM_f_b = 0, // finished (1=mask)
4052 + DMASM_f_m = 0x00000001, //
4053 + DMASM_d_b = 1, // done (1=mask)
4054 + DMASM_d_m = 0x00000002, //
4055 + DMASM_c_b = 2, // chain (1=mask)
4056 + DMASM_c_m = 0x00000004, //
4057 + DMASM_e_b = 3, // error (1=mask)
4058 + DMASM_e_m = 0x00000008, //
4059 + DMASM_h_b = 4, // halt (1=mask)
4060 + DMASM_h_m = 0x00000010, //
4061 +} ;
4062 +
4063 +/*
4064 + * DMA channel definitions
4065 + */
4066 +
4067 +enum
4068 +{
4069 + DMACH_ethRcv0 = 0,
4070 + DMACH_ethXmt0 = 1,
4071 + DMACH_ethRcv1 = 2,
4072 + DMACH_ethXmt2 = 3,
4073 + DMACH_pciToMem = 4,
4074 + DMACH_memToPci = 5,
4075 + DMACH_securityInput = 6,
4076 + DMACH_securityOutput = 7,
4077 + DMACH_rng = 8,
4078 +
4079 + DMACH_count //must be last
4080 +};
4081 +
4082 +
4083 +typedef struct DMAC_s
4084 +{
4085 + struct DMA_Chan_s ch [DMACH_count] ; //use ch[DMACH_]
4086 +} volatile *DMA_t ;
4087 +
4088 +
4089 +/*
4090 + * External DMA parameters
4091 +*/
4092 +
4093 +enum
4094 +{
4095 + DMADEVCMD_ts_b = 0, // ts field in devcmd
4096 + DMADEVCMD_ts_m = 0x00000007, // ts field in devcmd
4097 + DMADEVCMD_ts_byte_v = 0,
4098 + DMADEVCMD_ts_halfword_v = 1,
4099 + DMADEVCMD_ts_word_v = 2,
4100 + DMADEVCMD_ts_2word_v = 3,
4101 + DMADEVCMD_ts_4word_v = 4,
4102 + DMADEVCMD_ts_6word_v = 5,
4103 + DMADEVCMD_ts_8word_v = 6,
4104 + DMADEVCMD_ts_16word_v = 7
4105 +};
4106 +
4107 +
4108 +#if 1 // aws - Compatibility.
4109 +# define EXTDMA_ts_b DMADEVCMD_ts_b
4110 +# define EXTDMA_ts_m DMADEVCMD_ts_m
4111 +# define EXTDMA_ts_byte_v DMADEVCMD_ts_byte_v
4112 +# define EXTDMA_ts_halfword_v DMADEVCMD_ts_halfword_v
4113 +# define EXTDMA_ts_word_v DMADEVCMD_ts_word_v
4114 +# define EXTDMA_ts_2word_v DMADEVCMD_ts_2word_v
4115 +# define EXTDMA_ts_4word_v DMADEVCMD_ts_4word_v
4116 +# define EXTDMA_ts_6word_v DMADEVCMD_ts_6word_v
4117 +# define EXTDMA_ts_8word_v DMADEVCMD_ts_8word_v
4118 +# define EXTDMA_ts_16word_v DMADEVCMD_ts_16word_v
4119 +#endif // aws - Compatibility.
4120 +
4121 +#endif // __IDT_RC32365_DMA_H__
4122 diff -Nur linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h
4123 --- linux-2.6.16/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 1970-01-01 01:00:00.000000000 +0100
4124 +++ linux-2.6.16-owrt/include/asm-mips/idt-boards/rc32300/rc32365_dma_v.h 2006-03-20 14:25:10.000000000 +0100
4125 @@ -0,0 +1,86 @@
4126 +/**************************************************************************
4127 + *
4128 + * BRIEF MODULE DESCRIPTION
4129 + * RC32365/336 DMA interface routines.
4130 + *
4131 + * Copyright 2004 IDT Inc. (rischelp@idt.com)
4132 + *
4133 + * This program is free software; you can redistribute it and/or modify it
4134 + * under the terms of the GNU General Public License as published by the
4135 + * Free Software Foundation; either version 2 of the License, or (at your
4136 + * option) any later version.
4137 + *
4138 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
4139 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
4140 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
4141 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
4142 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
4143 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
4144 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
4145 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
4146 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
4147 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
4148 + *
4149 + * You should have received a copy of the GNU General Public License along
4150 + * with this program; if not, write to the Free Software Foundation, Inc.,
4151 + * 675 Mass Ave, Cambridge, MA 02139, USA.
4152 + *
4153 + *
4154 + **************************************************************************
4155 + * May 2004 P. Sadik.
4156 + *
4157 + * Initial Release
4158 + *
4159 + *
4160 + *
4161 + **************************************************************************
4162 + */
4163 +
4164 +#ifndef __IDT_RC32365_DMA_V_H__
4165 +#define __IDT_RC32365_DMA_V_H__
4166 +
4167 +
4168 +#include <asm/idt-boards/rc32300/rc32300.h>
4169 +#include <asm/idt-boards/rc32300/rc32365_dma.h>
4170 +#include <asm/idt-boards/rc32300/rc32365.h>
4171 +
4172 +#define DMA_CHAN_OFFSET 0x14
4173 +#define IS_DMA_USED(X) (((X) & (DMAD_f_m | DMAD_d_m | DMAD_t_m)) != 0)
4174 +#define IS_DMA_FINISHED(X) (((X) & (DMAD_f_m)) != 0)
4175 +#define IS_DMA_DONE(X) (((X) & (DMAD_d_m)) != 0)
4176 +
4177 +#define DMA_COUNT(count) \
4178 + ((count) & DMAD_count_m)
4179 +
4180 +#define DMA_HALT_TIMEOUT 500
4181 +
4182 +static inline int rc32365_halt_dma(DMA_Chan_t ch)
4183 +{
4184 + int timeout=1;
4185 + if (local_readl(&ch->dmac) & DMAC_run_m) {
4186 + local_writel(0, &ch->dmac);
4187 +
4188 + for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
4189 + if (local_readl(&ch->dmas) & DMAS_h_m) {