split kernel patches into board dependend and generic
[openwrt/staging/mkresin.git] / openwrt / target / linux / linux-2.4 / patches / generic / 000-linux_mips.patch
1 diff -Nur linux-2.4.30/Makefile linux-2.4.30-mips/Makefile
2 --- linux-2.4.30/Makefile 2005-04-04 03:42:20.000000000 +0200
3 +++ linux-2.4.30-mips/Makefile 2005-04-05 21:09:54.000000000 +0200
4 @@ -5,7 +5,7 @@
5
6 KERNELRELEASE=$(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION)
7
8 -ARCH := $(shell uname -m | sed -e s/i.86/i386/ -e s/sun4u/sparc64/ -e s/arm.*/arm/ -e s/sa110/arm/)
9 +ARCH = mips
10 KERNELPATH=kernel-$(shell echo $(KERNELRELEASE) | sed -e "s/-//g")
11
12 CONFIG_SHELL := $(shell if [ -x "$$BASH" ]; then echo $$BASH; \
13 @@ -462,10 +462,11 @@
14 $(MAKE) -C Documentation/DocBook mrproper
15
16 distclean: mrproper
17 - rm -f core `find . \( -not -type d \) -and \
18 - \( -name '*.orig' -o -name '*.rej' -o -name '*~' \
19 - -o -name '*.bak' -o -name '#*#' -o -name '.*.orig' \
20 - -o -name '.*.rej' -o -name '.SUMS' -o -size 0 \) -type f -print` TAGS tags
21 + find . \( -not -type d \) -and \
22 + \( -name core -o -name '*.orig' -o -name '*.rej' \
23 + -o -name '*~' -o -name '*.bak' -o -name '#*#' \
24 + -o -name '.*.rej' -o -name '.SUMS' -o -size 0 \
25 + -o -name TAGS -o -name tags \) -print | env -i xargs rm -f
26
27 backup: mrproper
28 cd .. && tar cf - linux/ | gzip -9 > backup.gz
29 @@ -492,7 +493,7 @@
30 $(MAKE) -C Documentation/DocBook man
31
32 sums:
33 - find . -type f -print | sort | xargs sum > .SUMS
34 + find . -type f -print | sort | env -i xargs sum > .SUMS
35
36 dep-files: scripts/mkdep archdep include/linux/version.h
37 rm -f .depend .hdepend
38 diff -Nur linux-2.4.30/arch/mips/Makefile linux-2.4.30-mips/arch/mips/Makefile
39 --- linux-2.4.30/arch/mips/Makefile 2005-01-19 15:09:26.000000000 +0100
40 +++ linux-2.4.30-mips/arch/mips/Makefile 2005-01-30 09:01:26.000000000 +0100
41 @@ -211,7 +211,7 @@
42 endif
43
44 #
45 -# Au1000 (Alchemy Semi PB1000) eval board
46 +# Au1x AMD Alchemy eval boards
47 #
48 ifdef CONFIG_MIPS_PB1000
49 LIBS += arch/mips/au1000/pb1000/pb1000.o \
50 @@ -220,9 +220,6 @@
51 LOADADDR := 0x80100000
52 endif
53
54 -#
55 -# Au1100 (Alchemy Semi PB1100) eval board
56 -#
57 ifdef CONFIG_MIPS_PB1100
58 LIBS += arch/mips/au1000/pb1100/pb1100.o \
59 arch/mips/au1000/common/au1000.o
60 @@ -230,9 +227,6 @@
61 LOADADDR += 0x80100000
62 endif
63
64 -#
65 -# Au1500 (Alchemy Semi PB1500) eval board
66 -#
67 ifdef CONFIG_MIPS_PB1500
68 LIBS += arch/mips/au1000/pb1500/pb1500.o \
69 arch/mips/au1000/common/au1000.o
70 @@ -240,9 +234,6 @@
71 LOADADDR := 0x80100000
72 endif
73
74 -#
75 -# Au1x00 (AMD/Alchemy) eval boards
76 -#
77 ifdef CONFIG_MIPS_DB1000
78 LIBS += arch/mips/au1000/db1x00/db1x00.o \
79 arch/mips/au1000/common/au1000.o
80 @@ -313,6 +304,27 @@
81 LOADADDR += 0x80100000
82 endif
83
84 +ifdef CONFIG_MIPS_PB1200
85 +LIBS += arch/mips/au1000/pb1200/pb1200.o \
86 + arch/mips/au1000/common/au1000.o
87 +SUBDIRS += arch/mips/au1000/pb1200 arch/mips/au1000/common
88 +LOADADDR += 0x80100000
89 +endif
90 +
91 +ifdef CONFIG_MIPS_DB1200
92 +LIBS += arch/mips/au1000/pb1200/pb1200.o \
93 + arch/mips/au1000/common/au1000.o
94 +SUBDIRS += arch/mips/au1000/pb1200 arch/mips/au1000/common
95 +LOADADDR += 0x80100000
96 +endif
97 +
98 +ifdef CONFIG_MIPS_FICMMP
99 +LIBS += arch/mips/au1000/ficmmp/ficmmp.o \
100 + arch/mips/au1000/common/au1000.o
101 +SUBDIRS += arch/mips/au1000/ficmmp arch/mips/au1000/common
102 +LOADADDR += 0x80100000
103 +endif
104 +
105
106 #
107 # Cogent CSB250
108 diff -Nur linux-2.4.30/arch/mips/au1000/common/Makefile linux-2.4.30-mips/arch/mips/au1000/common/Makefile
109 --- linux-2.4.30/arch/mips/au1000/common/Makefile 2005-01-19 15:09:26.000000000 +0100
110 +++ linux-2.4.30-mips/arch/mips/au1000/common/Makefile 2005-01-30 09:01:27.000000000 +0100
111 @@ -19,9 +19,9 @@
112 export-objs = prom.o clocks.o power.o usbdev.o
113
114 obj-y := prom.o int-handler.o irq.o puts.o time.o reset.o cputable.o \
115 - au1xxx_irqmap.o clocks.o power.o setup.o sleeper.o dma.o dbdma.o
116 + au1xxx_irqmap.o clocks.o power.o setup.o sleeper.o dma.o dbdma.o gpio.o
117
118 -export-objs += dma.o dbdma.o
119 +export-objs += dma.o dbdma.o gpio.o
120
121 obj-$(CONFIG_AU1X00_USB_DEVICE) += usbdev.o
122 obj-$(CONFIG_KGDB) += dbg_io.o
123 diff -Nur linux-2.4.30/arch/mips/au1000/common/au1xxx_irqmap.c linux-2.4.30-mips/arch/mips/au1000/common/au1xxx_irqmap.c
124 --- linux-2.4.30/arch/mips/au1000/common/au1xxx_irqmap.c 2005-01-19 15:09:26.000000000 +0100
125 +++ linux-2.4.30-mips/arch/mips/au1000/common/au1xxx_irqmap.c 2005-01-30 09:01:27.000000000 +0100
126 @@ -172,14 +172,14 @@
127 { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
128 { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0},
129 { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0},
130 - { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 },
131 - { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
132 - { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
133 - { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
134 - { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 },
135 - { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
136 - { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
137 - { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
138 + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
139 + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
140 + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
141 + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
142 + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
143 + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
144 + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
145 + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
146 { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0},
147 { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
148 { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
149 @@ -200,14 +200,14 @@
150 { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
151 { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0},
152 { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0},
153 - { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 },
154 - { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
155 - { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
156 - { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
157 - { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 },
158 - { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
159 - { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
160 - { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
161 + { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
162 + { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
163 + { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
164 + { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
165 + { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
166 + { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
167 + { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
168 + { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
169 { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0},
170 { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
171 { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
172 diff -Nur linux-2.4.30/arch/mips/au1000/common/cputable.c linux-2.4.30-mips/arch/mips/au1000/common/cputable.c
173 --- linux-2.4.30/arch/mips/au1000/common/cputable.c 2005-01-19 15:09:26.000000000 +0100
174 +++ linux-2.4.30-mips/arch/mips/au1000/common/cputable.c 2005-01-30 09:01:27.000000000 +0100
175 @@ -39,7 +39,8 @@
176 { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
177 { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
178 { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
179 - { 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 },
180 + { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0 },
181 + { 0xffffffff, 0x04030201, "Au1200 AC", 0, 0 },
182 { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
183 };
184
185 diff -Nur linux-2.4.30/arch/mips/au1000/common/dbdma.c linux-2.4.30-mips/arch/mips/au1000/common/dbdma.c
186 --- linux-2.4.30/arch/mips/au1000/common/dbdma.c 2005-01-19 15:09:26.000000000 +0100
187 +++ linux-2.4.30-mips/arch/mips/au1000/common/dbdma.c 2005-02-08 07:28:37.000000000 +0100
188 @@ -41,6 +41,8 @@
189 #include <asm/au1xxx_dbdma.h>
190 #include <asm/system.h>
191
192 +#include <linux/module.h>
193 +
194 #if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
195
196 /*
197 @@ -60,37 +62,10 @@
198 */
199 #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
200
201 -static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
202 -static int dbdma_initialized;
203 +static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
204 +static int dbdma_initialized=0;
205 static void au1xxx_dbdma_init(void);
206
207 -typedef struct dbdma_device_table {
208 - u32 dev_id;
209 - u32 dev_flags;
210 - u32 dev_tsize;
211 - u32 dev_devwidth;
212 - u32 dev_physaddr; /* If FIFO */
213 - u32 dev_intlevel;
214 - u32 dev_intpolarity;
215 -} dbdev_tab_t;
216 -
217 -typedef struct dbdma_chan_config {
218 - u32 chan_flags;
219 - u32 chan_index;
220 - dbdev_tab_t *chan_src;
221 - dbdev_tab_t *chan_dest;
222 - au1x_dma_chan_t *chan_ptr;
223 - au1x_ddma_desc_t *chan_desc_base;
224 - au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
225 - void *chan_callparam;
226 - void (*chan_callback)(int, void *, struct pt_regs *);
227 -} chan_tab_t;
228 -
229 -#define DEV_FLAGS_INUSE (1 << 0)
230 -#define DEV_FLAGS_ANYUSE (1 << 1)
231 -#define DEV_FLAGS_OUT (1 << 2)
232 -#define DEV_FLAGS_IN (1 << 3)
233 -
234 static dbdev_tab_t dbdev_tab[] = {
235 #ifdef CONFIG_SOC_AU1550
236 /* UARTS */
237 @@ -156,13 +131,13 @@
238 { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
239 { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
240
241 - { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
242 - { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
243 - { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
244 - { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
245 + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 },
246 + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 },
247 + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 4, 8, 0x10680000, 0, 0 },
248 + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 4, 8, 0x10680004, 0, 0 },
249
250 - { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
251 - { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
252 + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 },
253 + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 },
254
255 { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
256 { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
257 @@ -172,9 +147,9 @@
258 { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
259 { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
260
261 - { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
262 - { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
263 - { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
264 + { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 32, 0x14004020, 0, 0 },
265 + { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 32, 0x14004040, 0, 0 },
266 + { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 32, 0x14004060, 0, 0 },
267 { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
268
269 { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
270 @@ -183,6 +158,24 @@
271
272 { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
273 { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
274 +
275 + /* Provide 16 user definable device types */
276 + { 0, 0, 0, 0, 0, 0, 0 },
277 + { 0, 0, 0, 0, 0, 0, 0 },
278 + { 0, 0, 0, 0, 0, 0, 0 },
279 + { 0, 0, 0, 0, 0, 0, 0 },
280 + { 0, 0, 0, 0, 0, 0, 0 },
281 + { 0, 0, 0, 0, 0, 0, 0 },
282 + { 0, 0, 0, 0, 0, 0, 0 },
283 + { 0, 0, 0, 0, 0, 0, 0 },
284 + { 0, 0, 0, 0, 0, 0, 0 },
285 + { 0, 0, 0, 0, 0, 0, 0 },
286 + { 0, 0, 0, 0, 0, 0, 0 },
287 + { 0, 0, 0, 0, 0, 0, 0 },
288 + { 0, 0, 0, 0, 0, 0, 0 },
289 + { 0, 0, 0, 0, 0, 0, 0 },
290 + { 0, 0, 0, 0, 0, 0, 0 },
291 + { 0, 0, 0, 0, 0, 0, 0 },
292 };
293
294 #define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
295 @@ -202,6 +195,30 @@
296 return NULL;
297 }
298
299 +u32
300 +au1xxx_ddma_add_device(dbdev_tab_t *dev)
301 +{
302 + u32 ret = 0;
303 + dbdev_tab_t *p=NULL;
304 + static u16 new_id=0x1000;
305 +
306 + p = find_dbdev_id(0);
307 + if ( NULL != p )
308 + {
309 + memcpy(p, dev, sizeof(dbdev_tab_t));
310 + p->dev_id = DSCR_DEV2CUSTOM_ID(new_id,dev->dev_id);
311 + ret = p->dev_id;
312 + new_id++;
313 +#if 0
314 + printk("add_device: id:%x flags:%x padd:%x\n",
315 + p->dev_id, p->dev_flags, p->dev_physaddr );
316 +#endif
317 + }
318 +
319 + return ret;
320 +}
321 +EXPORT_SYMBOL(au1xxx_ddma_add_device);
322 +
323 /* Allocate a channel and return a non-zero descriptor if successful.
324 */
325 u32
326 @@ -214,7 +231,7 @@
327 int i;
328 dbdev_tab_t *stp, *dtp;
329 chan_tab_t *ctp;
330 - volatile au1x_dma_chan_t *cp;
331 + au1x_dma_chan_t *cp;
332
333 /* We do the intialization on the first channel allocation.
334 * We have to wait because of the interrupt handler initialization
335 @@ -224,9 +241,6 @@
336 au1xxx_dbdma_init();
337 dbdma_initialized = 1;
338
339 - if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS))
340 - return 0;
341 -
342 if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
343 if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
344
345 @@ -268,9 +282,9 @@
346 /* If kmalloc fails, it is caught below same
347 * as a channel not available.
348 */
349 - ctp = (chan_tab_t *)kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
350 + ctp = (chan_tab_t *)
351 + kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
352 chan_tab_ptr[i] = ctp;
353 - ctp->chan_index = chan = i;
354 break;
355 }
356 }
357 @@ -278,10 +292,11 @@
358
359 if (ctp != NULL) {
360 memset(ctp, 0, sizeof(chan_tab_t));
361 + ctp->chan_index = chan = i;
362 dcp = DDMA_CHANNEL_BASE;
363 dcp += (0x0100 * chan);
364 ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
365 - cp = (volatile au1x_dma_chan_t *)dcp;
366 + cp = (au1x_dma_chan_t *)dcp;
367 ctp->chan_src = stp;
368 ctp->chan_dest = dtp;
369 ctp->chan_callback = callback;
370 @@ -298,6 +313,9 @@
371 i |= DDMA_CFG_DED;
372 if (dtp->dev_intpolarity)
373 i |= DDMA_CFG_DP;
374 + if ((stp->dev_flags & DEV_FLAGS_SYNC) ||
375 + (dtp->dev_flags & DEV_FLAGS_SYNC))
376 + i |= DDMA_CFG_SYNC;
377 cp->ddma_cfg = i;
378 au_sync();
379
380 @@ -308,14 +326,14 @@
381 rv = (u32)(&chan_tab_ptr[chan]);
382 }
383 else {
384 - /* Release devices.
385 - */
386 + /* Release devices */
387 stp->dev_flags &= ~DEV_FLAGS_INUSE;
388 dtp->dev_flags &= ~DEV_FLAGS_INUSE;
389 }
390 }
391 return rv;
392 }
393 +EXPORT_SYMBOL(au1xxx_dbdma_chan_alloc);
394
395 /* Set the device width if source or destination is a FIFO.
396 * Should be 8, 16, or 32 bits.
397 @@ -343,6 +361,7 @@
398
399 return rv;
400 }
401 +EXPORT_SYMBOL(au1xxx_dbdma_set_devwidth);
402
403 /* Allocate a descriptor ring, initializing as much as possible.
404 */
405 @@ -369,7 +388,8 @@
406 * and if we try that first we are likely to not waste larger
407 * slabs of memory.
408 */
409 - desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL);
410 + desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t),
411 + GFP_KERNEL|GFP_DMA);
412 if (desc_base == 0)
413 return 0;
414
415 @@ -380,7 +400,7 @@
416 kfree((const void *)desc_base);
417 i = entries * sizeof(au1x_ddma_desc_t);
418 i += (sizeof(au1x_ddma_desc_t) - 1);
419 - if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0)
420 + if ((desc_base = (u32)kmalloc(i, GFP_KERNEL|GFP_DMA)) == 0)
421 return 0;
422
423 desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
424 @@ -460,9 +480,14 @@
425 /* If source input is fifo, set static address.
426 */
427 if (stp->dev_flags & DEV_FLAGS_IN) {
428 - src0 = stp->dev_physaddr;
429 - src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
430 + if ( stp->dev_flags & DEV_FLAGS_BURSTABLE )
431 + src1 |= DSCR_SRC1_SAM(DSCR_xAM_BURST);
432 + else
433 + src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
434 +
435 }
436 + if (stp->dev_physaddr)
437 + src0 = stp->dev_physaddr;
438
439 /* Set up dest1. For now, assume no stride and increment.
440 * A channel attribute update can change this later.
441 @@ -486,10 +511,18 @@
442 /* If destination output is fifo, set static address.
443 */
444 if (dtp->dev_flags & DEV_FLAGS_OUT) {
445 - dest0 = dtp->dev_physaddr;
446 + if ( dtp->dev_flags & DEV_FLAGS_BURSTABLE )
447 + dest1 |= DSCR_DEST1_DAM(DSCR_xAM_BURST);
448 + else
449 dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
450 }
451 + if (dtp->dev_physaddr)
452 + dest0 = dtp->dev_physaddr;
453
454 +#if 0
455 + printk("did:%x sid:%x cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
456 + dtp->dev_id, stp->dev_id, cmd0, cmd1, src0, src1, dest0, dest1 );
457 +#endif
458 for (i=0; i<entries; i++) {
459 dp->dscr_cmd0 = cmd0;
460 dp->dscr_cmd1 = cmd1;
461 @@ -498,6 +531,7 @@
462 dp->dscr_dest0 = dest0;
463 dp->dscr_dest1 = dest1;
464 dp->dscr_stat = 0;
465 + dp->sw_context = dp->sw_status = 0;
466 dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
467 dp++;
468 }
469 @@ -510,13 +544,14 @@
470
471 return (u32)(ctp->chan_desc_base);
472 }
473 +EXPORT_SYMBOL(au1xxx_dbdma_ring_alloc);
474
475 /* Put a source buffer into the DMA ring.
476 * This updates the source pointer and byte count. Normally used
477 * for memory to fifo transfers.
478 */
479 u32
480 -au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
481 +_au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags)
482 {
483 chan_tab_t *ctp;
484 au1x_ddma_desc_t *dp;
485 @@ -543,24 +578,40 @@
486 */
487 dp->dscr_source0 = virt_to_phys(buf);
488 dp->dscr_cmd1 = nbytes;
489 - dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
490 - ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */
491 -
492 + /* Check flags */
493 + if (flags & DDMA_FLAGS_IE)
494 + dp->dscr_cmd0 |= DSCR_CMD0_IE;
495 + if (flags & DDMA_FLAGS_NOIE)
496 + dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
497 /* Get next descriptor pointer.
498 */
499 ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
500
501 + /*
502 + * There is an errata on the Au1200/Au1550 parts that could result
503 + * in "stale" data being DMA'd. It has to do with the snoop logic on
504 + * the dache eviction buffer. NONCOHERENT_IO is on by default for
505 + * these parts. If it is fixedin the future, these dma_cache_inv will
506 + * just be nothing more than empty macros. See io.h.
507 + * */
508 + dma_cache_wback_inv(buf,nbytes);
509 + dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
510 + au_sync();
511 + dma_cache_wback_inv(dp, sizeof(dp));
512 + ctp->chan_ptr->ddma_dbell = 0;
513 +
514 /* return something not zero.
515 */
516 return nbytes;
517 }
518 +EXPORT_SYMBOL(_au1xxx_dbdma_put_source);
519
520 /* Put a destination buffer into the DMA ring.
521 * This updates the destination pointer and byte count. Normally used
522 * to place an empty buffer into the ring for fifo to memory transfers.
523 */
524 u32
525 -au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
526 +_au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags)
527 {
528 chan_tab_t *ctp;
529 au1x_ddma_desc_t *dp;
530 @@ -582,11 +633,33 @@
531 if (dp->dscr_cmd0 & DSCR_CMD0_V)
532 return 0;
533
534 - /* Load up buffer address and byte count.
535 - */
536 + /* Load up buffer address and byte count */
537 +
538 + /* Check flags */
539 + if (flags & DDMA_FLAGS_IE)
540 + dp->dscr_cmd0 |= DSCR_CMD0_IE;
541 + if (flags & DDMA_FLAGS_NOIE)
542 + dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
543 +
544 dp->dscr_dest0 = virt_to_phys(buf);
545 dp->dscr_cmd1 = nbytes;
546 +#if 0
547 + printk("cmd0:%x cmd1:%x source0:%x source1:%x dest0:%x dest1:%x\n",
548 + dp->dscr_cmd0, dp->dscr_cmd1, dp->dscr_source0,
549 + dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1 );
550 +#endif
551 + /*
552 + * There is an errata on the Au1200/Au1550 parts that could result in
553 + * "stale" data being DMA'd. It has to do with the snoop logic on the
554 + * dache eviction buffer. NONCOHERENT_IO is on by default for these
555 + * parts. If it is fixedin the future, these dma_cache_inv will just
556 + * be nothing more than empty macros. See io.h.
557 + * */
558 + dma_cache_inv(buf,nbytes);
559 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
560 + au_sync();
561 + dma_cache_wback_inv(dp, sizeof(dp));
562 + ctp->chan_ptr->ddma_dbell = 0;
563
564 /* Get next descriptor pointer.
565 */
566 @@ -596,6 +669,7 @@
567 */
568 return nbytes;
569 }
570 +EXPORT_SYMBOL(_au1xxx_dbdma_put_dest);
571
572 /* Get a destination buffer into the DMA ring.
573 * Normally used to get a full buffer from the ring during fifo
574 @@ -645,7 +719,7 @@
575 au1xxx_dbdma_stop(u32 chanid)
576 {
577 chan_tab_t *ctp;
578 - volatile au1x_dma_chan_t *cp;
579 + au1x_dma_chan_t *cp;
580 int halt_timeout = 0;
581
582 ctp = *((chan_tab_t **)chanid);
583 @@ -665,6 +739,7 @@
584 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
585 au_sync();
586 }
587 +EXPORT_SYMBOL(au1xxx_dbdma_stop);
588
589 /* Start using the current descriptor pointer. If the dbdma encounters
590 * a not valid descriptor, it will stop. In this case, we can just
591 @@ -674,17 +749,17 @@
592 au1xxx_dbdma_start(u32 chanid)
593 {
594 chan_tab_t *ctp;
595 - volatile au1x_dma_chan_t *cp;
596 + au1x_dma_chan_t *cp;
597
598 ctp = *((chan_tab_t **)chanid);
599 -
600 cp = ctp->chan_ptr;
601 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
602 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
603 au_sync();
604 - cp->ddma_dbell = 0xffffffff; /* Make it go */
605 + cp->ddma_dbell = 0;
606 au_sync();
607 }
608 +EXPORT_SYMBOL(au1xxx_dbdma_start);
609
610 void
611 au1xxx_dbdma_reset(u32 chanid)
612 @@ -703,15 +778,21 @@
613
614 do {
615 dp->dscr_cmd0 &= ~DSCR_CMD0_V;
616 + /* reset our SW status -- this is used to determine
617 + * if a descriptor is in use by upper level SW. Since
618 + * posting can reset 'V' bit.
619 + */
620 + dp->sw_status = 0;
621 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
622 } while (dp != ctp->chan_desc_base);
623 }
624 +EXPORT_SYMBOL(au1xxx_dbdma_reset);
625
626 u32
627 au1xxx_get_dma_residue(u32 chanid)
628 {
629 chan_tab_t *ctp;
630 - volatile au1x_dma_chan_t *cp;
631 + au1x_dma_chan_t *cp;
632 u32 rv;
633
634 ctp = *((chan_tab_t **)chanid);
635 @@ -746,15 +827,16 @@
636
637 kfree(ctp);
638 }
639 +EXPORT_SYMBOL(au1xxx_dbdma_chan_free);
640
641 static void
642 dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
643 {
644 - u32 intstat;
645 + u32 intstat, flags;
646 u32 chan_index;
647 chan_tab_t *ctp;
648 au1x_ddma_desc_t *dp;
649 - volatile au1x_dma_chan_t *cp;
650 + au1x_dma_chan_t *cp;
651
652 intstat = dbdma_gptr->ddma_intstat;
653 au_sync();
654 @@ -773,18 +855,26 @@
655 (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
656
657 ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
658 -
659 }
660
661 -static void
662 -au1xxx_dbdma_init(void)
663 +static void au1xxx_dbdma_init(void)
664 {
665 + int irq_nr;
666 +
667 dbdma_gptr->ddma_config = 0;
668 dbdma_gptr->ddma_throttle = 0;
669 dbdma_gptr->ddma_inten = 0xffff;
670 au_sync();
671
672 - if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT,
673 +#if defined(CONFIG_SOC_AU1550)
674 + irq_nr = AU1550_DDMA_INT;
675 +#elif defined(CONFIG_SOC_AU1200)
676 + irq_nr = AU1200_DDMA_INT;
677 +#else
678 + #error Unknown Au1x00 SOC
679 +#endif
680 +
681 + if (request_irq(irq_nr, dbdma_interrupt, SA_INTERRUPT,
682 "Au1xxx dbdma", (void *)dbdma_gptr))
683 printk("Can't get 1550 dbdma irq");
684 }
685 @@ -795,7 +885,8 @@
686 chan_tab_t *ctp;
687 au1x_ddma_desc_t *dp;
688 dbdev_tab_t *stp, *dtp;
689 - volatile au1x_dma_chan_t *cp;
690 + au1x_dma_chan_t *cp;
691 + u32 i = 0;
692
693 ctp = *((chan_tab_t **)chanid);
694 stp = ctp->chan_src;
695 @@ -820,15 +911,64 @@
696 dp = ctp->chan_desc_base;
697
698 do {
699 - printk("dp %08x, cmd0 %08x, cmd1 %08x\n",
700 - (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
701 - printk("src0 %08x, src1 %08x, dest0 %08x\n",
702 - dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0);
703 - printk("dest1 %08x, stat %08x, nxtptr %08x\n",
704 - dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr);
705 + printk("Dp[%d]= %08x, cmd0 %08x, cmd1 %08x\n",
706 + i++, (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
707 + printk("src0 %08x, src1 %08x, dest0 %08x, dest1 %08x\n",
708 + dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0, dp->dscr_dest1);
709 + printk("stat %08x, nxtptr %08x\n",
710 + dp->dscr_stat, dp->dscr_nxtptr);
711 dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
712 } while (dp != ctp->chan_desc_base);
713 }
714
715 +/* Put a descriptor into the DMA ring.
716 + * This updates the source/destination pointers and byte count.
717 + */
718 +u32
719 +au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr )
720 +{
721 + chan_tab_t *ctp;
722 + au1x_ddma_desc_t *dp;
723 + u32 nbytes=0;
724 +
725 + /* I guess we could check this to be within the
726 + * range of the table......
727 + */
728 + ctp = *((chan_tab_t **)chanid);
729 +
730 + /* We should have multiple callers for a particular channel,
731 + * an interrupt doesn't affect this pointer nor the descriptor,
732 + * so no locking should be needed.
733 + */
734 + dp = ctp->put_ptr;
735 +
736 + /* If the descriptor is valid, we are way ahead of the DMA
737 + * engine, so just return an error condition.
738 + */
739 + if (dp->dscr_cmd0 & DSCR_CMD0_V)
740 + return 0;
741 +
742 + /* Load up buffer addresses and byte count.
743 + */
744 + dp->dscr_dest0 = dscr->dscr_dest0;
745 + dp->dscr_source0 = dscr->dscr_source0;
746 + dp->dscr_dest1 = dscr->dscr_dest1;
747 + dp->dscr_source1 = dscr->dscr_source1;
748 + dp->dscr_cmd1 = dscr->dscr_cmd1;
749 + nbytes = dscr->dscr_cmd1;
750 + /* Allow the caller to specifiy if an interrupt is generated */
751 + dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
752 + dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
753 + ctp->chan_ptr->ddma_dbell = 0;
754 +
755 + /* Get next descriptor pointer.
756 + */
757 + ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
758 +
759 + /* return something not zero.
760 + */
761 + return nbytes;
762 +}
763 +
764 #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
765
766 diff -Nur linux-2.4.30/arch/mips/au1000/common/gpio.c linux-2.4.30-mips/arch/mips/au1000/common/gpio.c
767 --- linux-2.4.30/arch/mips/au1000/common/gpio.c 1970-01-01 01:00:00.000000000 +0100
768 +++ linux-2.4.30-mips/arch/mips/au1000/common/gpio.c 2005-01-30 09:01:27.000000000 +0100
769 @@ -0,0 +1,118 @@
770 +/*
771 + * This program is free software; you can redistribute it and/or modify it
772 + * under the terms of the GNU General Public License as published by the
773 + * Free Software Foundation; either version 2 of the License, or (at your
774 + * option) any later version.
775 + *
776 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
777 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
778 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
779 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
780 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
781 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
782 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
783 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
784 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
785 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
786 + *
787 + * You should have received a copy of the GNU General Public License along
788 + * with this program; if not, write to the Free Software Foundation, Inc.,
789 + * 675 Mass Ave, Cambridge, MA 02139, USA.
790 + */
791 +
792 +#include <asm/au1000.h>
793 +#include <asm/au1xxx_gpio.h>
794 +
795 +#define gpio1 sys
796 +#if !defined(CONFIG_SOC_AU1000)
797 +static AU1X00_GPIO2 * const gpio2 = (AU1X00_GPIO2 *)GPIO2_BASE;
798 +
799 +#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000
800 +
801 +int au1xxx_gpio2_read(int signal)
802 +{
803 + signal -= 200;
804 +/* gpio2->dir &= ~(0x01 << signal); //Set GPIO to input */
805 + return ((gpio2->pinstate >> signal) & 0x01);
806 +}
807 +
808 +void au1xxx_gpio2_write(int signal, int value)
809 +{
810 + signal -= 200;
811 +
812 + gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << signal) |
813 + (value << signal);
814 +}
815 +
816 +void au1xxx_gpio2_tristate(int signal)
817 +{
818 + signal -= 200;
819 + gpio2->dir &= ~(0x01 << signal); /* Set GPIO to input */
820 +}
821 +#endif
822 +
823 +int au1xxx_gpio1_read(int signal)
824 +{
825 +/* gpio1->trioutclr |= (0x01 << signal); */
826 + return ((gpio1->pinstaterd >> signal) & 0x01);
827 +}
828 +
829 +void au1xxx_gpio1_write(int signal, int value)
830 +{
831 + if(value)
832 + gpio1->outputset = (0x01 << signal);
833 + else
834 + gpio1->outputclr = (0x01 << signal); /* Output a Zero */
835 +}
836 +
837 +void au1xxx_gpio1_tristate(int signal)
838 +{
839 + gpio1->trioutclr = (0x01 << signal); /* Tristate signal */
840 +}
841 +
842 +
843 +int au1xxx_gpio_read(int signal)
844 +{
845 + if(signal >= 200)
846 +#if defined(CONFIG_SOC_AU1000)
847 + return 0;
848 +#else
849 + return au1xxx_gpio2_read(signal);
850 +#endif
851 + else
852 + return au1xxx_gpio1_read(signal);
853 +}
854 +
855 +void au1xxx_gpio_write(int signal, int value)
856 +{
857 + if(signal >= 200)
858 +#if defined(CONFIG_SOC_AU1000)
859 + ;
860 +#else
861 + au1xxx_gpio2_write(signal, value);
862 +#endif
863 + else
864 + au1xxx_gpio1_write(signal, value);
865 +}
866 +
867 +void au1xxx_gpio_tristate(int signal)
868 +{
869 + if(signal >= 200)
870 +#if defined(CONFIG_SOC_AU1000)
871 + ;
872 +#else
873 + au1xxx_gpio2_tristate(signal);
874 +#endif
875 + else
876 + au1xxx_gpio1_tristate(signal);
877 +}
878 +
879 +void au1xxx_gpio1_set_inputs(void)
880 +{
881 + gpio1->pininputen = 0;
882 +}
883 +
884 +EXPORT_SYMBOL(au1xxx_gpio1_set_inputs);
885 +EXPORT_SYMBOL(au1xxx_gpio_tristate);
886 +EXPORT_SYMBOL(au1xxx_gpio_write);
887 +EXPORT_SYMBOL(au1xxx_gpio_read);
888 diff -Nur linux-2.4.30/arch/mips/au1000/common/irq.c linux-2.4.30-mips/arch/mips/au1000/common/irq.c
889 --- linux-2.4.30/arch/mips/au1000/common/irq.c 2005-01-19 15:09:26.000000000 +0100
890 +++ linux-2.4.30-mips/arch/mips/au1000/common/irq.c 2005-03-13 08:56:57.000000000 +0100
891 @@ -303,8 +303,30 @@
892 };
893
894 #ifdef CONFIG_PM
895 -void startup_match20_interrupt(void)
896 +void startup_match20_interrupt(void (*handler)(int, void *, struct pt_regs *))
897 {
898 + static struct irqaction action;
899 + /* This is a big problem.... since we didn't use request_irq
900 + when kernel/irq.c calls probe_irq_xxx this interrupt will
901 + be probed for usage. This will end up disabling the device :(
902 +
903 + Give it a bogus "action" pointer -- this will keep it from
904 + getting auto-probed!
905 +
906 + By setting the status to match that of request_irq() we
907 + can avoid it. --cgray
908 + */
909 + action.dev_id = handler;
910 + action.flags = 0;
911 + action.mask = 0;
912 + action.name = "Au1xxx TOY";
913 + action.handler = handler;
914 + action.next = NULL;
915 +
916 + irq_desc[AU1000_TOY_MATCH2_INT].action = &action;
917 + irq_desc[AU1000_TOY_MATCH2_INT].status
918 + &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING | IRQ_INPROGRESS);
919 +
920 local_enable_irq(AU1000_TOY_MATCH2_INT);
921 }
922 #endif
923 @@ -508,6 +530,7 @@
924
925 if (!intc0_req0) return;
926
927 +#ifdef AU1000_USB_DEV_REQ_INT
928 /*
929 * Because of the tight timing of SETUP token to reply
930 * transactions, the USB devices-side packet complete
931 @@ -518,6 +541,7 @@
932 do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
933 return;
934 }
935 +#endif
936
937 irq = au_ffs(intc0_req0) - 1;
938 intc0_req0 &= ~(1<<irq);
939 @@ -536,17 +560,7 @@
940
941 irq = au_ffs(intc0_req1) - 1;
942 intc0_req1 &= ~(1<<irq);
943 -#ifdef CONFIG_PM
944 - if (irq == AU1000_TOY_MATCH2_INT) {
945 - mask_and_ack_rise_edge_irq(irq);
946 - counter0_irq(irq, NULL, regs);
947 - local_enable_irq(irq);
948 - }
949 - else
950 -#endif
951 - {
952 - do_IRQ(irq, regs);
953 - }
954 + do_IRQ(irq, regs);
955 }
956
957
958 diff -Nur linux-2.4.30/arch/mips/au1000/common/pci_fixup.c linux-2.4.30-mips/arch/mips/au1000/common/pci_fixup.c
959 --- linux-2.4.30/arch/mips/au1000/common/pci_fixup.c 2005-01-19 15:09:26.000000000 +0100
960 +++ linux-2.4.30-mips/arch/mips/au1000/common/pci_fixup.c 2004-12-03 09:00:32.000000000 +0100
961 @@ -75,9 +75,13 @@
962
963 #ifdef CONFIG_NONCOHERENT_IO
964 /*
965 - * Set the NC bit in controller for pre-AC silicon
966 + * Set the NC bit in controller for Au1500 pre-AC silicon
967 */
968 - au_writel( 1<<16 | au_readl(Au1500_PCI_CFG), Au1500_PCI_CFG);
969 + u32 prid = read_c0_prid();
970 + if ( (prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
971 + au_writel( 1<<16 | au_readl(Au1500_PCI_CFG), Au1500_PCI_CFG);
972 + printk("Non-coherent PCI accesses enabled\n");
973 + }
974 printk("Non-coherent PCI accesses enabled\n");
975 #endif
976
977 diff -Nur linux-2.4.30/arch/mips/au1000/common/pci_ops.c linux-2.4.30-mips/arch/mips/au1000/common/pci_ops.c
978 --- linux-2.4.30/arch/mips/au1000/common/pci_ops.c 2004-02-18 14:36:30.000000000 +0100
979 +++ linux-2.4.30-mips/arch/mips/au1000/common/pci_ops.c 2005-02-27 23:14:24.000000000 +0100
980 @@ -162,6 +162,7 @@
981 static int config_access(unsigned char access_type, struct pci_dev *dev,
982 unsigned char where, u32 * data)
983 {
984 + int error = PCIBIOS_SUCCESSFUL;
985 #if defined( CONFIG_SOC_AU1500 ) || defined( CONFIG_SOC_AU1550 )
986 unsigned char bus = dev->bus->number;
987 unsigned int dev_fn = dev->devfn;
988 @@ -170,7 +171,6 @@
989 unsigned long offset, status;
990 unsigned long cfg_base;
991 unsigned long flags;
992 - int error = PCIBIOS_SUCCESSFUL;
993 unsigned long entryLo0, entryLo1;
994
995 if (device > 19) {
996 @@ -205,9 +205,8 @@
997 last_entryLo0 = last_entryLo1 = 0xffffffff;
998 }
999
1000 - /* Since the Au1xxx doesn't do the idsel timing exactly to spec,
1001 - * many board vendors implement their own off-chip idsel, so call
1002 - * it now. If it doesn't succeed, may as well bail out at this point.
1003 + /* Allow board vendors to implement their own off-chip idsel.
1004 + * If it doesn't succeed, may as well bail out at this point.
1005 */
1006 if (board_pci_idsel) {
1007 if (board_pci_idsel(device, 1) == 0) {
1008 @@ -271,8 +270,11 @@
1009 }
1010
1011 local_irq_restore(flags);
1012 - return error;
1013 +#else
1014 + /* Fake out Config space access with no responder */
1015 + *data = 0xFFFFFFFF;
1016 #endif
1017 + return error;
1018 }
1019 #endif
1020
1021 diff -Nur linux-2.4.30/arch/mips/au1000/common/power.c linux-2.4.30-mips/arch/mips/au1000/common/power.c
1022 --- linux-2.4.30/arch/mips/au1000/common/power.c 2005-01-19 15:09:26.000000000 +0100
1023 +++ linux-2.4.30-mips/arch/mips/au1000/common/power.c 2005-04-07 02:37:19.000000000 +0200
1024 @@ -50,7 +50,6 @@
1025
1026 static void calibrate_delay(void);
1027
1028 -extern void set_au1x00_speed(unsigned int new_freq);
1029 extern unsigned int get_au1x00_speed(void);
1030 extern unsigned long get_au1x00_uart_baud_base(void);
1031 extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
1032 @@ -116,6 +115,7 @@
1033 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
1034 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
1035
1036 +#ifndef CONFIG_SOC_AU1200
1037 /* Shutdown USB host/device.
1038 */
1039 sleep_usbhost_enable = au_readl(USB_HOST_CONFIG);
1040 @@ -127,6 +127,7 @@
1041
1042 sleep_usbdev_enable = au_readl(USBD_ENABLE);
1043 au_writel(0, USBD_ENABLE); au_sync();
1044 +#endif
1045
1046 /* Save interrupt controller state.
1047 */
1048 @@ -212,14 +213,12 @@
1049 int au_sleep(void)
1050 {
1051 unsigned long wakeup, flags;
1052 - extern void save_and_sleep(void);
1053 + extern unsigned int save_and_sleep(void);
1054
1055 spin_lock_irqsave(&pm_lock,flags);
1056
1057 save_core_regs();
1058
1059 - flush_cache_all();
1060 -
1061 /** The code below is all system dependent and we should probably
1062 ** have a function call out of here to set this up. You need
1063 ** to configure the GPIO or timer interrupts that will bring
1064 @@ -227,27 +226,26 @@
1065 ** For testing, the TOY counter wakeup is useful.
1066 **/
1067
1068 -#if 0
1069 +#if 1
1070 au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
1071
1072 /* gpio 6 can cause a wake up event */
1073 wakeup = au_readl(SYS_WAKEMSK);
1074 wakeup &= ~(1 << 8); /* turn off match20 wakeup */
1075 - wakeup |= 1 << 6; /* turn on gpio 6 wakeup */
1076 + wakeup = 1 << 5; /* turn on gpio 6 wakeup */
1077 #else
1078 - /* For testing, allow match20 to wake us up.
1079 - */
1080 + /* For testing, allow match20 to wake us up. */
1081 #ifdef SLEEP_TEST_TIMEOUT
1082 wakeup_counter0_set(sleep_ticks);
1083 #endif
1084 wakeup = 1 << 8; /* turn on match20 wakeup */
1085 wakeup = 0;
1086 #endif
1087 - au_writel(1, SYS_WAKESRC); /* clear cause */
1088 + au_writel(0, SYS_WAKESRC); /* clear cause */
1089 au_sync();
1090 au_writel(wakeup, SYS_WAKEMSK);
1091 au_sync();
1092 -
1093 + DPRINTK("Entering sleep!\n");
1094 save_and_sleep();
1095
1096 /* after a wakeup, the cpu vectors back to 0x1fc00000 so
1097 @@ -255,6 +253,7 @@
1098 */
1099 restore_core_regs();
1100 spin_unlock_irqrestore(&pm_lock, flags);
1101 + DPRINTK("Leaving sleep!\n");
1102 return 0;
1103 }
1104
1105 @@ -285,7 +284,6 @@
1106
1107 if (retval)
1108 return retval;
1109 -
1110 au_sleep();
1111 retval = pm_send_all(PM_RESUME, (void *) 0);
1112 }
1113 @@ -296,7 +294,6 @@
1114 void *buffer, size_t * len)
1115 {
1116 int retval = 0;
1117 - void au1k_wait(void);
1118
1119 if (!write) {
1120 *len = 0;
1121 @@ -305,119 +302,9 @@
1122 if (retval)
1123 return retval;
1124 suspend_mode = 1;
1125 - au1k_wait();
1126 - retval = pm_send_all(PM_RESUME, (void *) 0);
1127 - }
1128 - return retval;
1129 -}
1130
1131 -
1132 -static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
1133 - void *buffer, size_t * len)
1134 -{
1135 - int retval = 0, i;
1136 - unsigned long val, pll;
1137 -#define TMPBUFLEN 64
1138 -#define MAX_CPU_FREQ 396
1139 - char buf[TMPBUFLEN], *p;
1140 - unsigned long flags, intc0_mask, intc1_mask;
1141 - unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk,
1142 - old_refresh;
1143 - unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
1144 -
1145 - spin_lock_irqsave(&pm_lock, flags);
1146 - if (!write) {
1147 - *len = 0;
1148 - } else {
1149 - /* Parse the new frequency */
1150 - if (*len > TMPBUFLEN - 1) {
1151 - spin_unlock_irqrestore(&pm_lock, flags);
1152 - return -EFAULT;
1153 - }
1154 - if (copy_from_user(buf, buffer, *len)) {
1155 - spin_unlock_irqrestore(&pm_lock, flags);
1156 - return -EFAULT;
1157 - }
1158 - buf[*len] = 0;
1159 - p = buf;
1160 - val = simple_strtoul(p, &p, 0);
1161 - if (val > MAX_CPU_FREQ) {
1162 - spin_unlock_irqrestore(&pm_lock, flags);
1163 - return -EFAULT;
1164 - }
1165 -
1166 - pll = val / 12;
1167 - if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
1168 - /* revisit this for higher speed cpus */
1169 - spin_unlock_irqrestore(&pm_lock, flags);
1170 - return -EFAULT;
1171 - }
1172 -
1173 - old_baud_base = get_au1x00_uart_baud_base();
1174 - old_cpu_freq = get_au1x00_speed();
1175 -
1176 - new_cpu_freq = pll * 12 * 1000000;
1177 - new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
1178 - set_au1x00_speed(new_cpu_freq);
1179 - set_au1x00_uart_baud_base(new_baud_base);
1180 -
1181 - old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
1182 - new_refresh =
1183 - ((old_refresh * new_cpu_freq) /
1184 - old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
1185 -
1186 - au_writel(pll, SYS_CPUPLL);
1187 - au_sync_delay(1);
1188 - au_writel(new_refresh, MEM_SDREFCFG);
1189 - au_sync_delay(1);
1190 -
1191 - for (i = 0; i < 4; i++) {
1192 - if (au_readl
1193 - (UART_BASE + UART_MOD_CNTRL +
1194 - i * 0x00100000) == 3) {
1195 - old_clk =
1196 - au_readl(UART_BASE + UART_CLK +
1197 - i * 0x00100000);
1198 - // baud_rate = baud_base/clk
1199 - baud_rate = old_baud_base / old_clk;
1200 - /* we won't get an exact baud rate and the error
1201 - * could be significant enough that our new
1202 - * calculation will result in a clock that will
1203 - * give us a baud rate that's too far off from
1204 - * what we really want.
1205 - */
1206 - if (baud_rate > 100000)
1207 - baud_rate = 115200;
1208 - else if (baud_rate > 50000)
1209 - baud_rate = 57600;
1210 - else if (baud_rate > 30000)
1211 - baud_rate = 38400;
1212 - else if (baud_rate > 17000)
1213 - baud_rate = 19200;
1214 - else
1215 - (baud_rate = 9600);
1216 - // new_clk = new_baud_base/baud_rate
1217 - new_clk = new_baud_base / baud_rate;
1218 - au_writel(new_clk,
1219 - UART_BASE + UART_CLK +
1220 - i * 0x00100000);
1221 - au_sync_delay(10);
1222 - }
1223 - }
1224 + retval = pm_send_all(PM_RESUME, (void *) 0);
1225 }
1226 -
1227 -
1228 - /* We don't want _any_ interrupts other than
1229 - * match20. Otherwise our calibrate_delay()
1230 - * calculation will be off, potentially a lot.
1231 - */
1232 - intc0_mask = save_local_and_disable(0);
1233 - intc1_mask = save_local_and_disable(1);
1234 - local_enable_irq(AU1000_TOY_MATCH2_INT);
1235 - spin_unlock_irqrestore(&pm_lock, flags);
1236 - calibrate_delay();
1237 - restore_local_and_enable(0, intc0_mask);
1238 - restore_local_and_enable(1, intc1_mask);
1239 return retval;
1240 }
1241
1242 @@ -425,7 +312,6 @@
1243 static struct ctl_table pm_table[] = {
1244 {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, &pm_do_suspend},
1245 {ACPI_SLEEP, "sleep", NULL, 0, 0600, NULL, &pm_do_sleep},
1246 - {CTL_ACPI, "freq", NULL, 0, 0600, NULL, &pm_do_freq},
1247 {0}
1248 };
1249
1250 diff -Nur linux-2.4.30/arch/mips/au1000/common/reset.c linux-2.4.30-mips/arch/mips/au1000/common/reset.c
1251 --- linux-2.4.30/arch/mips/au1000/common/reset.c 2005-01-19 15:09:26.000000000 +0100
1252 +++ linux-2.4.30-mips/arch/mips/au1000/common/reset.c 2005-03-19 08:17:51.000000000 +0100
1253 @@ -37,8 +37,6 @@
1254 #include <asm/system.h>
1255 #include <asm/au1000.h>
1256
1257 -extern int au_sleep(void);
1258 -
1259 void au1000_restart(char *command)
1260 {
1261 /* Set all integrated peripherals to disabled states */
1262 @@ -144,6 +142,26 @@
1263 au_writel(0x00, 0xb1900064); /* sys_auxpll */
1264 au_writel(0x00, 0xb1900100); /* sys_pininputen */
1265 break;
1266 + case 0x04000000: /* Au1200 */
1267 + au_writel(0x00, 0xb400300c); /* ddma */
1268 + au_writel(0x00, 0xb1a00004); /* psc 0 */
1269 + au_writel(0x00, 0xb1b00004); /* psc 1 */
1270 + au_writel(0x00d02000, 0xb4020004); /* ehci, ohci, udc, otg */
1271 + au_writel(0x00, 0xb5000004); /* lcd */
1272 + au_writel(0x00, 0xb060000c); /* sd0 */
1273 + au_writel(0x00, 0xb068000c); /* sd1 */
1274 + au_writel(0x00, 0xb1100100); /* swcnt */
1275 + au_writel(0x00, 0xb0300000); /* aes */
1276 + au_writel(0x00, 0xb4004000); /* cim */
1277 + au_writel(0x00, 0xb1100100); /* uart0_enable */
1278 + au_writel(0x00, 0xb1200100); /* uart1_enable */
1279 + au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
1280 + au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
1281 + au_writel(0x00, 0xb1900028); /* sys_clksrc */
1282 + au_writel(0x10, 0xb1900060); /* sys_cpupll */
1283 + au_writel(0x00, 0xb1900064); /* sys_auxpll */
1284 + au_writel(0x00, 0xb1900100); /* sys_pininputen */
1285 + break;
1286
1287 default:
1288 break;
1289 @@ -163,32 +181,23 @@
1290
1291 void au1000_halt(void)
1292 {
1293 -#if defined(CONFIG_MIPS_PB1550)
1294 - /* power off system */
1295 - printk("\n** Powering off Pb1550\n");
1296 - au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
1297 - au_sync();
1298 - while(1); /* should not get here */
1299 -#endif
1300 - printk(KERN_NOTICE "\n** You can safely turn off the power\n");
1301 -#ifdef CONFIG_MIPS_MIRAGE
1302 - au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
1303 -#endif
1304 -#ifdef CONFIG_PM
1305 - au_sleep();
1306 -
1307 - /* should not get here */
1308 - printk(KERN_ERR "Unable to put cpu in sleep mode\n");
1309 - while(1);
1310 -#else
1311 - while (1)
1312 + /* Use WAIT in a low-power infinite spin loop */
1313 + while (1) {
1314 __asm__(".set\tmips3\n\t"
1315 "wait\n\t"
1316 ".set\tmips0");
1317 -#endif
1318 + }
1319 }
1320
1321 void au1000_power_off(void)
1322 {
1323 + extern void board_power_off (void);
1324 +
1325 + printk(KERN_NOTICE "\n** You can safely turn off the power\n");
1326 +
1327 + /* Give board a chance to power-off */
1328 + board_power_off();
1329 +
1330 + /* If board can't power-off, spin forever */
1331 au1000_halt();
1332 }
1333 diff -Nur linux-2.4.30/arch/mips/au1000/common/setup.c linux-2.4.30-mips/arch/mips/au1000/common/setup.c
1334 --- linux-2.4.30/arch/mips/au1000/common/setup.c 2005-01-19 15:09:26.000000000 +0100
1335 +++ linux-2.4.30-mips/arch/mips/au1000/common/setup.c 2005-01-30 09:01:27.000000000 +0100
1336 @@ -174,6 +174,40 @@
1337 initrd_end = (unsigned long)&__rd_end;
1338 #endif
1339
1340 +#if defined(CONFIG_SOC_AU1200)
1341 +#ifdef CONFIG_USB_EHCI_HCD
1342 + if ((argptr = strstr(argptr, "usb_ehci=")) == NULL) {
1343 + char usb_args[80];
1344 + argptr = prom_getcmdline();
1345 + memset(usb_args, 0, sizeof(usb_args));
1346 + sprintf(usb_args, " usb_ehci=base:0x%x,len:0x%x,irq:%d",
1347 + USB_EHCI_BASE, USB_EHCI_LEN, AU1000_USB_HOST_INT);
1348 + strcat(argptr, usb_args);
1349 + }
1350 +#ifdef CONFIG_USB_AMD5536UDC
1351 + /* enable EHC + OHC + UDC clocks, memory and bus mastering */
1352 +/* au_writel( 0x00DF207F, USB_MSR_BASE + 4); */
1353 + au_writel( 0xC0DF207F, USB_MSR_BASE + 4); // incl. prefetch
1354 +#else
1355 + /* enable EHC + OHC clocks, memory and bus mastering */
1356 +/* au_writel( 0x00DB200F, USB_MSR_BASE + 4); */
1357 + au_writel( 0xC0DB200F, USB_MSR_BASE + 4); /* incl. prefetch */
1358 +#endif
1359 + udelay(1000);
1360 +
1361 +#else /* CONFIG_USB_EHCI_HCD */
1362 +
1363 +#ifdef CONFIG_USB_AMD5536UDC
1364 +#ifndef CONFIG_USB_OHCI
1365 + /* enable UDC clocks, memory and bus mastering */
1366 +/* au_writel( 0x00DC2070, USB_MSR_BASE + 4); */
1367 + au_writel( 0xC0DC2070, USB_MSR_BASE + 4); // incl. prefetch
1368 + udelay(1000);
1369 +#endif
1370 +#endif
1371 +#endif /* CONFIG_USB_EHCI_HCD */
1372 +#endif /* CONFIG_SOC_AU1200 */
1373 +
1374 #if defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
1375 #ifdef CONFIG_USB_OHCI
1376 if ((argptr = strstr(argptr, "usb_ohci=")) == NULL) {
1377 @@ -187,19 +221,38 @@
1378 #endif
1379
1380 #ifdef CONFIG_USB_OHCI
1381 - // enable host controller and wait for reset done
1382 +#if defined(CONFIG_SOC_AU1200)
1383 +#ifndef CONFIG_USB_EHCI_HCD
1384 +#ifdef CONFIG_USB_AMD5536UDC
1385 + /* enable OHC + UDC clocks, memory and bus mastering */
1386 +/* au_writel( 0x00DD2073, USB_MSR_BASE + 4); */
1387 + au_writel( 0xC0DD2073, USB_MSR_BASE + 4); // incl. prefetch
1388 +#else
1389 + /* enable OHC clocks, memory and bus mastering */
1390 + au_writel( 0x00D12003, USB_MSR_BASE + 4);
1391 +#endif
1392 + udelay(1000);
1393 +printk("DEBUG: Reading Au1200 USB2 reg 0x%x\n", au_readl(USB_MSR_BASE + 4));
1394 +#endif
1395 +#else
1396 + /* Au1000, Au1500, Au1100, Au1550 */
1397 + /* enable host controller and wait for reset done */
1398 au_writel(0x08, USB_HOST_CONFIG);
1399 udelay(1000);
1400 au_writel(0x0E, USB_HOST_CONFIG);
1401 udelay(1000);
1402 - au_readl(USB_HOST_CONFIG); // throw away first read
1403 + au_readl(USB_HOST_CONFIG); /* throw away first read */
1404 while (!(au_readl(USB_HOST_CONFIG) & 0x10))
1405 au_readl(USB_HOST_CONFIG);
1406 +#endif /* CONFIG_SOC_AU1200 */
1407 #endif
1408 -#endif // defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE)
1409 +#else
1410 +
1411 +#endif /* defined (CONFIG_USB_OHCI) || defined (CONFIG_AU1X00_USB_DEVICE) */
1412 +
1413
1414 #ifdef CONFIG_FB
1415 - // Needed if PCI video card in use
1416 + /* Needed if PCI video card in use */
1417 conswitchp = &dummy_con;
1418 #endif
1419
1420 @@ -209,8 +262,7 @@
1421 #endif
1422
1423 #ifdef CONFIG_BLK_DEV_IDE
1424 - /* Board setup takes precedence for unique devices.
1425 - */
1426 + /* Board setup takes precedence for unique devices. */
1427 if ((ide_ops == NULL) || (ide_ops == &no_ide_ops))
1428 ide_ops = &std_ide_ops;
1429 #endif
1430 diff -Nur linux-2.4.30/arch/mips/au1000/common/sleeper.S linux-2.4.30-mips/arch/mips/au1000/common/sleeper.S
1431 --- linux-2.4.30/arch/mips/au1000/common/sleeper.S 2004-02-18 14:36:30.000000000 +0100
1432 +++ linux-2.4.30-mips/arch/mips/au1000/common/sleeper.S 2005-01-30 09:01:27.000000000 +0100
1433 @@ -15,17 +15,48 @@
1434 #include <asm/addrspace.h>
1435 #include <asm/regdef.h>
1436 #include <asm/stackframe.h>
1437 +#include <asm/au1000.h>
1438 +
1439 +/*
1440 + * Note: This file is *not* conditional on CONFIG_PM since Alchemy sleep
1441 + * need not be tied to any particular power management scheme.
1442 + */
1443 +
1444 + .extern ___flush_cache_all
1445
1446 .text
1447 - .set macro
1448 - .set noat
1449 .align 5
1450
1451 -/* Save all of the processor general registers and go to sleep.
1452 - * A wakeup condition will get us back here to restore the registers.
1453 +/*
1454 + * Save the processor general registers and go to sleep. A wakeup
1455 + * condition will get us back here to restore the registers.
1456 */
1457 -LEAF(save_and_sleep)
1458
1459 +/* still need to fix alignment issues here */
1460 +save_and_sleep_frmsz = 48
1461 +NESTED(save_and_sleep, save_and_sleep_frmsz, ra)
1462 + .set noreorder
1463 + .set nomacro
1464 + .set noat
1465 + subu sp, save_and_sleep_frmsz
1466 + sw ra, save_and_sleep_frmsz-4(sp)
1467 + sw s0, save_and_sleep_frmsz-8(sp)
1468 + sw s1, save_and_sleep_frmsz-12(sp)
1469 + sw s2, save_and_sleep_frmsz-16(sp)
1470 + sw s3, save_and_sleep_frmsz-20(sp)
1471 + sw s4, save_and_sleep_frmsz-24(sp)
1472 + sw s5, save_and_sleep_frmsz-28(sp)
1473 + sw s6, save_and_sleep_frmsz-32(sp)
1474 + sw s7, save_and_sleep_frmsz-36(sp)
1475 + sw s8, save_and_sleep_frmsz-40(sp)
1476 + sw gp, save_and_sleep_frmsz-44(sp)
1477 +
1478 + /* We only need to save the registers that the calling function
1479 + * hasn't saved for us. 0 is always zero. 8 - 15, 24 and 25 are
1480 + * temporaries and can be used without saving. 26 and 27 are reserved
1481 + * for interrupt/trap handling and expected to change. 29 is the
1482 + * stack pointer which is handled as a special case here.
1483 + */
1484 subu sp, PT_SIZE
1485 sw $1, PT_R1(sp)
1486 sw $2, PT_R2(sp)
1487 @@ -34,14 +65,6 @@
1488 sw $5, PT_R5(sp)
1489 sw $6, PT_R6(sp)
1490 sw $7, PT_R7(sp)
1491 - sw $8, PT_R8(sp)
1492 - sw $9, PT_R9(sp)
1493 - sw $10, PT_R10(sp)
1494 - sw $11, PT_R11(sp)
1495 - sw $12, PT_R12(sp)
1496 - sw $13, PT_R13(sp)
1497 - sw $14, PT_R14(sp)
1498 - sw $15, PT_R15(sp)
1499 sw $16, PT_R16(sp)
1500 sw $17, PT_R17(sp)
1501 sw $18, PT_R18(sp)
1502 @@ -50,32 +73,47 @@
1503 sw $21, PT_R21(sp)
1504 sw $22, PT_R22(sp)
1505 sw $23, PT_R23(sp)
1506 - sw $24, PT_R24(sp)
1507 - sw $25, PT_R25(sp)
1508 - sw $26, PT_R26(sp)
1509 - sw $27, PT_R27(sp)
1510 sw $28, PT_R28(sp)
1511 - sw $29, PT_R29(sp)
1512 sw $30, PT_R30(sp)
1513 sw $31, PT_R31(sp)
1514 +#define PT_C0STATUS PT_LO
1515 +#define PT_CONTEXT PT_HI
1516 +#define PT_PAGEMASK PT_EPC
1517 +#define PT_CONFIG PT_BVADDR
1518 mfc0 k0, CP0_STATUS
1519 - sw k0, 0x20(sp)
1520 + sw k0, PT_C0STATUS(sp) // 0x20
1521 mfc0 k0, CP0_CONTEXT
1522 - sw k0, 0x1c(sp)
1523 + sw k0, PT_CONTEXT(sp) // 0x1c
1524 mfc0 k0, CP0_PAGEMASK
1525 - sw k0, 0x18(sp)
1526 + sw k0, PT_PAGEMASK(sp) // 0x18
1527 mfc0 k0, CP0_CONFIG
1528 - sw k0, 0x14(sp)
1529 + sw k0, PT_CONFIG(sp) // 0x14
1530 +
1531 + .set macro
1532 + .set at
1533 +
1534 + li t0, SYS_SLPPWR
1535 + sw zero, 0(t0) /* Get the processor ready to sleep */
1536 + sync
1537
1538 /* Now set up the scratch registers so the boot rom will
1539 * return to this point upon wakeup.
1540 + * sys_scratch0 : SP
1541 + * sys_scratch1 : RA
1542 + */
1543 + li t0, SYS_SCRATCH0
1544 + li t1, SYS_SCRATCH1
1545 + sw sp, 0(t0)
1546 + la k0, resume_from_sleep
1547 + sw k0, 0(t1)
1548 +
1549 +/*
1550 + * Flush DCACHE to make sure context is in memory
1551 */
1552 - la k0, 1f
1553 - lui k1, 0xb190
1554 - ori k1, 0x18
1555 - sw sp, 0(k1)
1556 - ori k1, 0x1c
1557 - sw k0, 0(k1)
1558 + la t1,___flush_cache_all /* _flush_cache_all is a function pointer */
1559 + lw t0,0(t1)
1560 + jal t0
1561 + nop
1562
1563 /* Put SDRAM into self refresh. Preload instructions into cache,
1564 * issue a precharge, then auto refresh, then sleep commands to it.
1565 @@ -88,30 +126,65 @@
1566 cache 0x14, 96(t0)
1567 .set mips0
1568
1569 + /* Put SDRAM to sleep */
1570 sdsleep:
1571 - lui k0, 0xb400
1572 - sw zero, 0x001c(k0) /* Precharge */
1573 - sw zero, 0x0020(k0) /* Auto refresh */
1574 - sw zero, 0x0030(k0) /* SDRAM sleep */
1575 + li a0, MEM_PHYS_ADDR
1576 + or a0, a0, 0xA0000000
1577 +#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500)
1578 + lw k0, MEM_SDMODE0(a0)
1579 + sw zero, MEM_SDPRECMD(a0) /* Precharge */
1580 + sw zero, MEM_SDAUTOREF(a0) /* Auto Refresh */
1581 + sw zero, MEM_SDSLEEP(a0) /* Sleep */
1582 sync
1583 -
1584 - lui k1, 0xb190
1585 - sw zero, 0x0078(k1) /* get ready to sleep */
1586 +#endif
1587 +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
1588 + sw zero, MEM_SDPRECMD(a0) /* Precharge */
1589 + sw zero, MEM_SDSREF(a0)
1590 +
1591 + #lw t0, MEM_SDSTAT(a0)
1592 + #and t0, t0, 0x01000000
1593 + li t0, 0x01000000
1594 +refresh_not_set:
1595 + lw t1, MEM_SDSTAT(a0)
1596 + and t2, t1, t0
1597 + beq zero, t2, refresh_not_set
1598 + nop
1599 +
1600 + li t0, ~0x30000000
1601 + lw t1, MEM_SDCONFIGA(a0)
1602 + and t1, t0, t1
1603 + sw t1, MEM_SDCONFIGA(a0)
1604 sync
1605 - sw zero, 0x007c(k1) /* Put processor to sleep */
1606 +#endif
1607 +
1608 + li t0, SYS_SLEEP
1609 + sw zero, 0(t0) /* Put processor to sleep */
1610 sync
1611 + nop
1612 + nop
1613 + nop
1614 + nop
1615 + nop
1616 + nop
1617 + nop
1618 + nop
1619 +
1620
1621 /* This is where we return upon wakeup.
1622 * Reload all of the registers and return.
1623 */
1624 -1: nop
1625 - lw k0, 0x20(sp)
1626 +resume_from_sleep:
1627 + nop
1628 + .set nomacro
1629 + .set noat
1630 +
1631 + lw k0, PT_C0STATUS(sp) // 0x20
1632 mtc0 k0, CP0_STATUS
1633 - lw k0, 0x1c(sp)
1634 + lw k0, PT_CONTEXT(sp) // 0x1c
1635 mtc0 k0, CP0_CONTEXT
1636 - lw k0, 0x18(sp)
1637 + lw k0, PT_PAGEMASK(sp) // 0x18
1638 mtc0 k0, CP0_PAGEMASK
1639 - lw k0, 0x14(sp)
1640 + lw k0, PT_CONFIG(sp) // 0x14
1641 mtc0 k0, CP0_CONFIG
1642 lw $1, PT_R1(sp)
1643 lw $2, PT_R2(sp)
1644 @@ -120,14 +193,6 @@
1645 lw $5, PT_R5(sp)
1646 lw $6, PT_R6(sp)
1647 lw $7, PT_R7(sp)
1648 - lw $8, PT_R8(sp)
1649 - lw $9, PT_R9(sp)
1650 - lw $10, PT_R10(sp)
1651 - lw $11, PT_R11(sp)
1652 - lw $12, PT_R12(sp)
1653 - lw $13, PT_R13(sp)
1654 - lw $14, PT_R14(sp)
1655 - lw $15, PT_R15(sp)
1656 lw $16, PT_R16(sp)
1657 lw $17, PT_R17(sp)
1658 lw $18, PT_R18(sp)
1659 @@ -136,15 +201,36 @@
1660 lw $21, PT_R21(sp)
1661 lw $22, PT_R22(sp)
1662 lw $23, PT_R23(sp)
1663 - lw $24, PT_R24(sp)
1664 - lw $25, PT_R25(sp)
1665 - lw $26, PT_R26(sp)
1666 - lw $27, PT_R27(sp)
1667 lw $28, PT_R28(sp)
1668 - lw $29, PT_R29(sp)
1669 lw $30, PT_R30(sp)
1670 lw $31, PT_R31(sp)
1671 +
1672 + .set macro
1673 + .set at
1674 +
1675 + /* clear the wake source, but save it as the return value of the function */
1676 + li t0, SYS_WAKESRC
1677 + lw v0, 0(t0)
1678 + sw v0, PT_R2(sp)
1679 + sw zero, 0(t0)
1680 +
1681 addiu sp, PT_SIZE
1682
1683 + lw gp, save_and_sleep_frmsz-44(sp)
1684 + lw s8, save_and_sleep_frmsz-40(sp)
1685 + lw s7, save_and_sleep_frmsz-36(sp)
1686 + lw s6, save_and_sleep_frmsz-32(sp)
1687 + lw s5, save_and_sleep_frmsz-28(sp)
1688 + lw s4, save_and_sleep_frmsz-24(sp)
1689 + lw s3, save_and_sleep_frmsz-20(sp)
1690 + lw s2, save_and_sleep_frmsz-16(sp)
1691 + lw s1, save_and_sleep_frmsz-12(sp)
1692 + lw s0, save_and_sleep_frmsz-8(sp)
1693 + lw ra, save_and_sleep_frmsz-4(sp)
1694 +
1695 + addu sp, save_and_sleep_frmsz
1696 jr ra
1697 + nop
1698 + .set reorder
1699 END(save_and_sleep)
1700 +
1701 diff -Nur linux-2.4.30/arch/mips/au1000/common/time.c linux-2.4.30-mips/arch/mips/au1000/common/time.c
1702 --- linux-2.4.30/arch/mips/au1000/common/time.c 2005-01-19 15:09:26.000000000 +0100
1703 +++ linux-2.4.30-mips/arch/mips/au1000/common/time.c 2005-04-08 10:33:17.000000000 +0200
1704 @@ -50,7 +50,6 @@
1705 #include <linux/mc146818rtc.h>
1706 #include <linux/timex.h>
1707
1708 -extern void startup_match20_interrupt(void);
1709 extern void do_softirq(void);
1710 extern volatile unsigned long wall_jiffies;
1711 unsigned long missed_heart_beats = 0;
1712 @@ -59,14 +58,14 @@
1713 static unsigned long r4k_cur; /* What counter should be at next timer irq */
1714 extern rwlock_t xtime_lock;
1715 int no_au1xxx_32khz;
1716 -void (*au1k_wait_ptr)(void);
1717 +extern int allow_au1k_wait; /* default off for CP0 Counter */
1718
1719 /* Cycle counter value at the previous timer interrupt.. */
1720 static unsigned int timerhi = 0, timerlo = 0;
1721
1722 #ifdef CONFIG_PM
1723 #define MATCH20_INC 328
1724 -extern void startup_match20_interrupt(void);
1725 +extern void startup_match20_interrupt(void (*handler)(int, void *, struct pt_regs *));
1726 static unsigned long last_pc0, last_match20;
1727 #endif
1728
1729 @@ -385,7 +384,6 @@
1730 {
1731 unsigned int est_freq;
1732 extern unsigned long (*do_gettimeoffset)(void);
1733 - extern void au1k_wait(void);
1734
1735 printk("calculating r4koff... ");
1736 r4k_offset = cal_r4koff();
1737 @@ -437,9 +435,6 @@
1738 au_writel(0, SYS_TOYWRITE);
1739 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
1740
1741 - au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
1742 - au_writel(~0, SYS_WAKESRC);
1743 - au_sync();
1744 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
1745
1746 /* setup match20 to interrupt once every 10ms */
1747 @@ -447,13 +442,13 @@
1748 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
1749 au_sync();
1750 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
1751 - startup_match20_interrupt();
1752 + startup_match20_interrupt(counter0_irq);
1753
1754 do_gettimeoffset = do_fast_pm_gettimeoffset;
1755
1756 /* We can use the real 'wait' instruction.
1757 */
1758 - au1k_wait_ptr = au1k_wait;
1759 + allow_au1k_wait = 1;
1760 }
1761
1762 #else
1763 diff -Nur linux-2.4.30/arch/mips/au1000/db1x00/Makefile linux-2.4.30-mips/arch/mips/au1000/db1x00/Makefile
1764 --- linux-2.4.30/arch/mips/au1000/db1x00/Makefile 2005-01-19 15:09:26.000000000 +0100
1765 +++ linux-2.4.30-mips/arch/mips/au1000/db1x00/Makefile 2005-01-30 09:06:19.000000000 +0100
1766 @@ -17,4 +17,11 @@
1767 obj-y := init.o board_setup.o irqmap.o
1768 obj-$(CONFIG_WM97XX_COMODULE) += mirage_ts.o
1769
1770 +ifdef CONFIG_MIPS_DB1100
1771 +ifdef CONFIG_MMC
1772 +obj-y += mmc_support.o
1773 +export-objs += mmc_support.o
1774 +endif
1775 +endif
1776 +
1777 include $(TOPDIR)/Rules.make
1778 diff -Nur linux-2.4.30/arch/mips/au1000/db1x00/board_setup.c linux-2.4.30-mips/arch/mips/au1000/db1x00/board_setup.c
1779 --- linux-2.4.30/arch/mips/au1000/db1x00/board_setup.c 2005-01-19 15:09:26.000000000 +0100
1780 +++ linux-2.4.30-mips/arch/mips/au1000/db1x00/board_setup.c 2005-03-19 08:17:51.000000000 +0100
1781 @@ -46,10 +46,22 @@
1782 #include <asm/au1000.h>
1783 #include <asm/db1x00.h>
1784
1785 -extern struct rtc_ops no_rtc_ops;
1786 +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) && defined(CONFIG_MIPS_DB1550)
1787 +#include <asm/au1xxx_dbdma.h>
1788 +extern struct ide_ops *ide_ops;
1789 +extern struct ide_ops au1xxx_ide_ops;
1790 +extern u32 au1xxx_ide_virtbase;
1791 +extern u64 au1xxx_ide_physbase;
1792 +extern int au1xxx_ide_irq;
1793 +
1794 +/* Ddma */
1795 +chan_tab_t *ide_read_ch, *ide_write_ch;
1796 +u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma
1797 +
1798 +dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 };
1799 +#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */
1800
1801 -/* not correct for db1550 */
1802 -static BCSR * const bcsr = (BCSR *)0xAE000000;
1803 +extern struct rtc_ops no_rtc_ops;
1804
1805 void board_reset (void)
1806 {
1807 @@ -57,6 +69,13 @@
1808 au_writel(0x00000000, 0xAE00001C);
1809 }
1810
1811 +void board_power_off (void)
1812 +{
1813 +#ifdef CONFIG_MIPS_MIRAGE
1814 + au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
1815 +#endif
1816 +}
1817 +
1818 void __init board_setup(void)
1819 {
1820 u32 pin_func;
1821 @@ -108,8 +127,42 @@
1822 au_writel(0x02000200, GPIO2_OUTPUT);
1823 #endif
1824
1825 +#if defined(CONFIG_AU1XXX_SMC91111)
1826 +#define CPLD_CONTROL (0xAF00000C)
1827 + {
1828 + extern uint32_t au1xxx_smc91111_base;
1829 + extern unsigned int au1xxx_smc91111_irq;
1830 + extern int au1xxx_smc91111_nowait;
1831 +
1832 + au1xxx_smc91111_base = 0xAC000300;
1833 + au1xxx_smc91111_irq = AU1000_GPIO_8;
1834 + au1xxx_smc91111_nowait = 1;
1835 +
1836 + /* set up the Static Bus timing - only 396Mhz */
1837 + bcsr->resets |= 0x7;
1838 + au_writel(0x00010003, MEM_STCFG0);
1839 + au_writel(0x000c00c0, MEM_STCFG2);
1840 + au_writel(0x85E1900D, MEM_STTIME2);
1841 + }
1842 +#endif /* end CONFIG_SMC91111 */
1843 au_sync();
1844
1845 +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX) && defined(CONFIG_MIPS_DB1550)
1846 + /*
1847 + * Iniz IDE parameters
1848 + */
1849 + ide_ops = &au1xxx_ide_ops;
1850 + au1xxx_ide_irq = DAUGHTER_CARD_IRQ;
1851 + au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR;
1852 + au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR);
1853 +
1854 + /*
1855 + * change PIO or PIO+Ddma
1856 + * check the GPIO-6 pin condition. db1550:s6_dot
1857 + */
1858 + switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 6)) ? 1 : 0;
1859 +#endif
1860 +
1861 #ifdef CONFIG_MIPS_DB1000
1862 printk("AMD Alchemy Au1000/Db1000 Board\n");
1863 #endif
1864 diff -Nur linux-2.4.30/arch/mips/au1000/db1x00/irqmap.c linux-2.4.30-mips/arch/mips/au1000/db1x00/irqmap.c
1865 --- linux-2.4.30/arch/mips/au1000/db1x00/irqmap.c 2005-01-19 15:09:26.000000000 +0100
1866 +++ linux-2.4.30-mips/arch/mips/au1000/db1x00/irqmap.c 2005-01-30 09:06:19.000000000 +0100
1867 @@ -53,6 +53,7 @@
1868 #ifdef CONFIG_MIPS_DB1550
1869 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card 0 IRQ#
1870 { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card 1 IRQ#
1871 + { AU1000_GPIO_8, INTC_INT_LOW_LEVEL, 0 }, // Daughtercard IRQ#
1872 #else
1873 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card 0 Fully_Interted#
1874 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card 0 STSCHG#
1875 diff -Nur linux-2.4.30/arch/mips/au1000/db1x00/mmc_support.c linux-2.4.30-mips/arch/mips/au1000/db1x00/mmc_support.c
1876 --- linux-2.4.30/arch/mips/au1000/db1x00/mmc_support.c 1970-01-01 01:00:00.000000000 +0100
1877 +++ linux-2.4.30-mips/arch/mips/au1000/db1x00/mmc_support.c 2005-01-30 09:07:01.000000000 +0100
1878 @@ -0,0 +1,126 @@
1879 +/*
1880 + * BRIEF MODULE DESCRIPTION
1881 + *
1882 + * MMC support routines for DB1100.
1883 + *
1884 + *
1885 + * Copyright (c) 2003-2004 Embedded Edge, LLC.
1886 + * Author: Embedded Edge, LLC.
1887 + * Contact: dan@embeddededge.com
1888 + *
1889 + * This program is free software; you can redistribute it and/or modify it
1890 + * under the terms of the GNU General Public License as published by the
1891 + * Free Software Foundation; either version 2 of the License, or (at your
1892 + * option) any later version.
1893 + *
1894 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
1895 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
1896 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
1897 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
1898 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
1899 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
1900 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
1901 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
1902 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
1903 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
1904 + *
1905 + * You should have received a copy of the GNU General Public License along
1906 + * with this program; if not, write to the Free Software Foundation, Inc.,
1907 + * 675 Mass Ave, Cambridge, MA 02139, USA.
1908 + *
1909 + */
1910 +
1911 +
1912 +#include <linux/config.h>
1913 +#include <linux/kernel.h>
1914 +#include <linux/module.h>
1915 +#include <linux/init.h>
1916 +
1917 +#include <asm/irq.h>
1918 +#include <asm/au1000.h>
1919 +#include <asm/au1100_mmc.h>
1920 +#include <asm/db1x00.h>
1921 +
1922 +
1923 +/* SD/MMC controller support functions */
1924 +
1925 +/*
1926 + * Detect card.
1927 + */
1928 +void mmc_card_inserted(int _n_, int *_res_)
1929 +{
1930 + u32 gpios = au_readl(SYS_PINSTATERD);
1931 + u32 emptybit = (_n_) ? (1<<20) : (1<<19);
1932 + *_res_ = ((gpios & emptybit) == 0);
1933 +}
1934 +
1935 +/*
1936 + * Check card write protection.
1937 + */
1938 +void mmc_card_writable(int _n_, int *_res_)
1939 +{
1940 + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
1941 + unsigned long mmc_wp, board_specific;
1942 +
1943 + if (_n_) {
1944 + mmc_wp = BCSR_BOARD_SD1_WP;
1945 + } else {
1946 + mmc_wp = BCSR_BOARD_SD0_WP;
1947 + }
1948 +
1949 + board_specific = au_readl((unsigned long)(&bcsr->specific));
1950 +
1951 + if (!(board_specific & mmc_wp)) {/* low means card writable */
1952 + *_res_ = 1;
1953 + } else {
1954 + *_res_ = 0;
1955 + }
1956 +}
1957 +
1958 +/*
1959 + * Apply power to card slot.
1960 + */
1961 +void mmc_power_on(int _n_)
1962 +{
1963 + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
1964 + unsigned long mmc_pwr, board_specific;
1965 +
1966 + if (_n_) {
1967 + mmc_pwr = BCSR_BOARD_SD1_PWR;
1968 + } else {
1969 + mmc_pwr = BCSR_BOARD_SD0_PWR;
1970 + }
1971 +
1972 + board_specific = au_readl((unsigned long)(&bcsr->specific));
1973 + board_specific |= mmc_pwr;
1974 +
1975 + au_writel(board_specific, (int)(&bcsr->specific));
1976 + au_sync_delay(1);
1977 +}
1978 +
1979 +/*
1980 + * Remove power from card slot.
1981 + */
1982 +void mmc_power_off(int _n_)
1983 +{
1984 + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
1985 + unsigned long mmc_pwr, board_specific;
1986 +
1987 + if (_n_) {
1988 + mmc_pwr = BCSR_BOARD_SD1_PWR;
1989 + } else {
1990 + mmc_pwr = BCSR_BOARD_SD0_PWR;
1991 + }
1992 +
1993 + board_specific = au_readl((unsigned long)(&bcsr->specific));
1994 + board_specific &= ~mmc_pwr;
1995 +
1996 + au_writel(board_specific, (int)(&bcsr->specific));
1997 + au_sync_delay(1);
1998 +}
1999 +
2000 +EXPORT_SYMBOL(mmc_card_inserted);
2001 +EXPORT_SYMBOL(mmc_card_writable);
2002 +EXPORT_SYMBOL(mmc_power_on);
2003 +EXPORT_SYMBOL(mmc_power_off);
2004 +
2005 diff -Nur linux-2.4.30/arch/mips/au1000/ficmmp/Makefile linux-2.4.30-mips/arch/mips/au1000/ficmmp/Makefile
2006 --- linux-2.4.30/arch/mips/au1000/ficmmp/Makefile 1970-01-01 01:00:00.000000000 +0100
2007 +++ linux-2.4.30-mips/arch/mips/au1000/ficmmp/Makefile 2005-01-30 09:01:27.000000000 +0100
2008 @@ -0,0 +1,25 @@
2009 +#
2010 +# Copyright 2000 MontaVista Software Inc.
2011 +# Author: MontaVista Software, Inc.
2012 +# ppopov@mvista.com or source@mvista.com
2013 +#
2014 +# Makefile for the Alchemy Semiconductor FIC board.
2015 +#
2016 +# Note! Dependencies are done automagically by 'make dep', which also
2017 +# removes any old dependencies. DON'T put your own dependencies here
2018 +# unless it's something special (ie not a .c file).
2019 +#
2020 +
2021 +USE_STANDARD_AS_RULE := true
2022 +
2023 +O_TARGET := ficmmp.o
2024 +
2025 +obj-y := init.o board_setup.o irqmap.o au1200_ibutton.o au1xxx_dock.o
2026 +
2027 +ifdef CONFIG_MMC
2028 +obj-y += mmc_support.o
2029 +export-objs +=mmc_support.o
2030 +endif
2031 +
2032 +
2033 +include $(TOPDIR)/Rules.make
2034 diff -Nur linux-2.4.30/arch/mips/au1000/ficmmp/au1200_ibutton.c linux-2.4.30-mips/arch/mips/au1000/ficmmp/au1200_ibutton.c
2035 --- linux-2.4.30/arch/mips/au1000/ficmmp/au1200_ibutton.c 1970-01-01 01:00:00.000000000 +0100
2036 +++ linux-2.4.30-mips/arch/mips/au1000/ficmmp/au1200_ibutton.c 2005-02-03 07:35:29.000000000 +0100
2037 @@ -0,0 +1,270 @@
2038 +/* ----------------------------------------------------------------------
2039 + * mtwilson_keys.c
2040 + *
2041 + * Copyright (C) 2003 Intrinsyc Software Inc.
2042 + *
2043 + * Intel Personal Media Player buttons
2044 + *
2045 + * This program is free software; you can redistribute it and/or modify
2046 + * it under the terms of the GNU General Public License version 2 as
2047 + * published by the Free Software Foundation.
2048 + *
2049 + * May 02, 2003 : Initial version [FB]
2050 + *
2051 + ------------------------------------------------------------------------*/
2052 +
2053 +#include <linux/config.h>
2054 +#include <linux/module.h>
2055 +#include <linux/kernel.h>
2056 +#include <linux/init.h>
2057 +#include <linux/fs.h>
2058 +#include <linux/sched.h>
2059 +#include <linux/miscdevice.h>
2060 +#include <linux/errno.h>
2061 +#include <linux/poll.h>
2062 +#include <linux/delay.h>
2063 +#include <linux/input.h>
2064 +
2065 +#include <asm/au1000.h>
2066 +#include <asm/uaccess.h>
2067 +#include <asm/au1xxx_gpio.h>
2068 +#include <asm/irq.h>
2069 +#include <asm/keyboard.h>
2070 +#include <linux/time.h>
2071 +
2072 +#define DRIVER_VERSION "V1.0"
2073 +#define DRIVER_AUTHOR "FIC"
2074 +#define DRIVER_DESC "FIC Travis Media Player Button Driver"
2075 +#define DRIVER_NAME "Au1200Button"
2076 +
2077 +#define BUTTON_MAIN (1<<1)
2078 +#define BUTTON_SELECT (1<<6)
2079 +#define BUTTON_GUIDE (1<<12)
2080 +#define BUTTON_DOWN (1<<17)
2081 +#define BUTTON_LEFT (1<<19)
2082 +#define BUTTON_RIGHT (1<<26)
2083 +#define BUTTON_UP (1<<28)
2084 +
2085 +#define BUTTON_MASK (\
2086 + BUTTON_MAIN \
2087 + | BUTTON_SELECT \
2088 + | BUTTON_GUIDE \
2089 + | BUTTON_DOWN \
2090 + | BUTTON_LEFT \
2091 + | BUTTON_RIGHT \
2092 + | BUTTON_UP \
2093 + )
2094 +
2095 +#define BUTTON_INVERT (\
2096 + BUTTON_MAIN \
2097 + | 0 \
2098 + | BUTTON_GUIDE \
2099 + | 0 \
2100 + | 0 \
2101 + | 0 \
2102 + | 0 \
2103 + )
2104 +
2105 +char button_map[32]={0,KEY_S,0,0,0,0,KEY_ENTER,0,0,0,0,0,KEY_G,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0};
2106 +//char button_map[32]={0,0,0,0,0,0,KEY_ENTER,0,0,0,0,0,KEY_G,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0};
2107 +
2108 +//char button_map[32]={0,KEY_TAB,0,0,0,0,KEY_M,0,0,0,0,0,KEY_S,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0};
2109 +//char button_map[32]={0,0,0,0,0,0,KEY_M,0,0,0,0,0,KEY_S,0,0,0,0,KEY_DOWN,0,KEY_LEFT,0,0,0,0,0,0,KEY_RIGHT,0,KEY_UP,0,0,0};
2110 +
2111 +#define BUTTON_COUNT (sizeof (button_map) / sizeof (button_map[0]))
2112 +
2113 +struct input_dev dev;
2114 +struct timeval cur_tv;
2115 +
2116 +static unsigned int old_tv_usec = 0;
2117 +
2118 +static unsigned int read_button_state(void)
2119 +{
2120 + unsigned int state;
2121 +
2122 + state = au_readl(SYS_PINSTATERD) & BUTTON_MASK; /* get gpio status */
2123 +
2124 + state ^= BUTTON_INVERT; /* invert main & guide button */
2125 +
2126 + /* printk("au1200_ibutton.c: button state [0x%X]\r\n",state); */
2127 + return state;
2128 +}
2129 +
2130 +//This function returns 0 if the allowed microseconds have elapsed since the last call to ths function, otherwise it returns 1 to indicate a bounce condition
2131 +static unsigned int bounce()
2132 +{
2133 +
2134 + unsigned int elapsed_time;
2135 +
2136 + do_gettimeofday (&cur_tv);
2137 +
2138 + if (!old_tv_usec) {
2139 + old_tv_usec = cur_tv.tv_usec;
2140 + return 0;
2141 + }
2142 +
2143 + if(cur_tv.tv_usec > old_tv_usec) {
2144 + /* If there hasn't been rollover */
2145 + elapsed_time = ((cur_tv.tv_usec - old_tv_usec));
2146 + }
2147 + else {
2148 + /* Accounting for rollover */
2149 + elapsed_time = ((1000000 - old_tv_usec + cur_tv.tv_usec));
2150 + }
2151 +
2152 + if (elapsed_time > 250000) {
2153 + old_tv_usec = 0; /* reset the bounce time */
2154 + return 0;
2155 + }
2156 +
2157 + return 1;
2158 +}
2159 +
2160 +/* button interrupt handler */
2161 +static void button_interrupt(int irq, void *dev, struct pt_regs *regs)
2162 +{
2163 +
2164 + unsigned int i,bit_mask, key_choice;
2165 + u32 button_state;
2166 +
2167 + /* Report state to upper level */
2168 +
2169 + button_state = read_button_state() & BUTTON_MASK; /* get new gpio status */
2170 +
2171 + /* Return if this is a repeated (bouncing) event */
2172 + if(bounce())
2173 + return;
2174 +
2175 + /* we want to make keystrokes */
2176 + for( i=0; i< BUTTON_COUNT; i++) {
2177 + bit_mask = 1<<i;
2178 + if (button_state & bit_mask) {
2179 + key_choice = button_map[i];
2180 + /* toggle key down */
2181 + input_report_key(dev, key_choice, 1);
2182 + /* toggle key up */
2183 + input_report_key(dev, key_choice, 0);
2184 + printk("ibutton gpio %d stat %x scan code %d\r\n",
2185 + i, button_state, key_choice);
2186 + /* Only report the first key event; it doesn't make
2187 + * sense for two keys to be pressed at the same time,
2188 + * and causes problems with the directional keys
2189 + * return;
2190 + */
2191 + }
2192 + }
2193 +}
2194 +
2195 +static int
2196 +button_translate(unsigned char scancode, unsigned char *keycode, char raw_mode)
2197 +{
2198 + static int prev_scancode;
2199 +
2200 + printk( "ibutton.c: translate: scancode=%x raw_mode=%x\n",
2201 + scancode, raw_mode);
2202 +
2203 + if (scancode == 0xe0 || scancode == 0xe1) {
2204 + prev_scancode = scancode;
2205 + return 0;
2206 + }
2207 +
2208 + if (scancode == 0x00 || scancode == 0xff) {
2209 + prev_scancode = 0;
2210 + return 0;
2211 + }
2212 +
2213 + *keycode = scancode;
2214 +
2215 + return 1;
2216 +}
2217 +
2218 +/* init button hardware */
2219 +static int button_hw_init(void)
2220 +{
2221 + unsigned int ipinfunc=0;
2222 +
2223 + printk("au1200_ibutton.c: Initializing buttons hardware\n");
2224 +
2225 + // initialize GPIO pin function assignments
2226 +
2227 + ipinfunc = au_readl(SYS_PINFUNC);
2228 +
2229 + ipinfunc &= ~(SYS_PINFUNC_DMA | SYS_PINFUNC_S0A | SYS_PINFUNC_S0B);
2230 + au_writel( ipinfunc ,SYS_PINFUNC);
2231 +
2232 + ipinfunc |= (SYS_PINFUNC_S0C);
2233 + au_writel( ipinfunc ,SYS_PINFUNC);
2234 +
2235 + return 0;
2236 +}
2237 +
2238 +/* button driver init */
2239 +static int __init button_init(void)
2240 +{
2241 + int ret, i;
2242 + unsigned int flag=0;
2243 +
2244 + printk("au1200_ibutton.c: button_init()\r\n");
2245 +
2246 + button_hw_init();
2247 +
2248 + /* register all button irq handler */
2249 +
2250 + for(i=0; i< sizeof(button_map)/sizeof(button_map[0]); i++)
2251 + {
2252 + /* register irq <-- gpio 1 ,6 ,12 , 17 ,19 , 26 ,28 */
2253 + if(button_map[i] != 0)
2254 + {
2255 + ret = request_irq(AU1000_GPIO_0 + i ,
2256 + &button_interrupt , SA_INTERRUPT ,
2257 + DRIVER_NAME , &dev);
2258 + if(ret) flag |= 1<<i;
2259 + }
2260 + }
2261 +
2262 + printk("au1200_ibutton.c: request_irq,ret:0x%x\r\n",ret);
2263 +
2264 + if (ret) {
2265 + printk("au1200_ibutton.c: request_irq:%X failed\r\n",flag);
2266 + return ret;
2267 + }
2268 +
2269 + dev.name = DRIVER_NAME;
2270 + dev.evbit[0] = BIT(EV_KEY) | BIT(EV_REP);
2271 +
2272 + for (i=0;i<sizeof(button_map)/sizeof(button_map[0]);i++)
2273 + {
2274 + dev.keybit[LONG(button_map[i])] |= BIT(button_map[i]);
2275 + }
2276 +
2277 + input_register_device(&dev);
2278 +
2279 + /* ready to receive interrupts */
2280 +
2281 + return 0;
2282 +}
2283 +
2284 +/* button driver exit */
2285 +static void __exit button_exit(void)
2286 +{
2287 + int i;
2288 +
2289 + for(i=0;i<sizeof(button_map)/sizeof(button_map[0]);i++)
2290 + {
2291 + if(button_map[i] != 0)
2292 + {
2293 + free_irq( AU1000_GPIO_0 + i, &dev);
2294 + }
2295 + }
2296 +
2297 + input_unregister_device(&dev);
2298 +
2299 + printk("au1200_ibutton.c: button_exit()\r\n");
2300 +}
2301 +
2302 +module_init(button_init);
2303 +module_exit(button_exit);
2304 +
2305 +MODULE_AUTHOR( DRIVER_AUTHOR );
2306 +MODULE_DESCRIPTION( DRIVER_DESC );
2307 +MODULE_LICENSE("GPL");
2308 diff -Nur linux-2.4.30/arch/mips/au1000/ficmmp/au1xxx_dock.c linux-2.4.30-mips/arch/mips/au1000/ficmmp/au1xxx_dock.c
2309 --- linux-2.4.30/arch/mips/au1000/ficmmp/au1xxx_dock.c 1970-01-01 01:00:00.000000000 +0100
2310 +++ linux-2.4.30-mips/arch/mips/au1000/ficmmp/au1xxx_dock.c 2005-01-30 09:01:27.000000000 +0100
2311 @@ -0,0 +1,261 @@
2312 +/*
2313 + * Copyright (C) 2003 Metrowerks, All Rights Reserved.
2314 + *
2315 + * This program is free software; you can redistribute it and/or modify
2316 + * it under the terms of the GNU General Public License version 2 as
2317 + * published by the Free Software Foundation.
2318 + */
2319 +
2320 +#include <linux/config.h>
2321 +#include <linux/module.h>
2322 +#include <linux/init.h>
2323 +#include <linux/fs.h>
2324 +#include <linux/sched.h>
2325 +#include <linux/miscdevice.h>
2326 +#include <linux/errno.h>
2327 +#include <linux/poll.h>
2328 +#include <asm/au1000.h>
2329 +#include <asm/uaccess.h>
2330 +#include <asm/au1xxx_gpio.h>
2331 +
2332 +
2333 +#if defined(CONFIG_MIPS_FICMMP)
2334 + #define DOCK_GPIO 215
2335 +#else
2336 + #error Unsupported Au1xxx Platform
2337 +#endif
2338 +
2339 +#define MAKE_FLAG 0x20
2340 +
2341 +#undef DEBUG
2342 +
2343 +#define DEBUG 0
2344 +//#define DEBUG 1
2345 +
2346 +#if DEBUG
2347 +#define DPRINTK(format, args...) printk(__FUNCTION__ ": " format, ## args)
2348 +#else
2349 +#define DPRINTK(format, args...) do { } while (0)
2350 +#endif
2351 +
2352 +/* Please note that this driver is based on a timer and is not interrupt
2353 + * driven. If you are going to make use of this driver, you will need to have
2354 + * your application open the dock listing from the /dev directory first.
2355 + */
2356 +
2357 +struct au1xxx_dock {
2358 + struct fasync_struct *fasync;
2359 + wait_queue_head_t read_wait;
2360 + int open_count;
2361 + unsigned int debounce;
2362 + unsigned int current;
2363 + unsigned int last;
2364 +};
2365 +
2366 +static struct au1xxx_dock dock_info;
2367 +
2368 +
2369 +static void dock_timer_periodic(void *data);
2370 +
2371 +static struct tq_struct dock_task = {
2372 + routine: dock_timer_periodic,
2373 + data: NULL
2374 +};
2375 +
2376 +static int cleanup_flag = 0;
2377 +static DECLARE_WAIT_QUEUE_HEAD(cleanup_wait_queue);
2378 +
2379 +
2380 +static unsigned int read_dock_state(void)
2381 +{
2382 + u32 state;
2383 +
2384 + state = au1xxx_gpio_read(DOCK_GPIO);
2385 +
2386 + /* printk( "Current Dock State: %d\n", state ); */
2387 +
2388 + return state;
2389 +}
2390 +
2391 +
2392 +static void dock_timer_periodic(void *data)
2393 +{
2394 + struct au1xxx_dock *dock = (struct au1xxx_dock *)data;
2395 + unsigned long dock_state;
2396 +
2397 + /* If cleanup wants us to die */
2398 + if (cleanup_flag) {
2399 + /* now cleanup_module can return */
2400 + wake_up(&cleanup_wait_queue);
2401 + } else {
2402 + /* put ourselves back in the task queue */
2403 + queue_task(&dock_task, &tq_timer);
2404 + }
2405 +
2406 + /* read current dock */
2407 + dock_state = read_dock_state();
2408 +
2409 + /* if dock states hasn't changed */
2410 + /* save time and be done. */
2411 + if (dock_state == dock->current) {
2412 + return;
2413 + }
2414 +
2415 + if (dock_state == dock->debounce) {
2416 + dock->current = dock_state;
2417 + } else {
2418 + dock->debounce = dock_state;
2419 + }
2420 + if (dock->current != dock->last) {
2421 + if (waitqueue_active(&dock->read_wait)) {
2422 + wake_up_interruptible(&dock->read_wait);
2423 + }
2424 + }
2425 +}
2426 +
2427 +
2428 +static ssize_t au1xxx_dock_read(struct file *filp, char *buffer, size_t count, loff_t *ppos)
2429 +{
2430 + struct au1xxx_dock *dock = filp->private_data;
2431 + char event[3];
2432 + int last;
2433 + int cur;
2434 + int err;
2435 +
2436 +try_again:
2437 +
2438 + while (dock->current == dock->last) {
2439 + if (filp->f_flags & O_NONBLOCK) {
2440 + return -EAGAIN;
2441 + }
2442 + interruptible_sleep_on(&dock->read_wait);
2443 + if (signal_pending(current)) {
2444 + return -ERESTARTSYS;
2445 + }
2446 + }
2447 +
2448 + cur = dock->current;
2449 + last = dock->last;
2450 +
2451 + if(cur != last)
2452 + {
2453 + event[0] = cur ? 'D' : 'U';
2454 + event[1] = '\r';
2455 + event[2] = '\n';
2456 + }
2457 + else
2458 + goto try_again;
2459 +
2460 + dock->last = cur;
2461 + err = copy_to_user(buffer, &event, 3);
2462 + if (err) {
2463 + return err;
2464 + }
2465 +
2466 + return 3;
2467 +}
2468 +
2469 +
2470 +static int au1xxx_dock_open(struct inode *inode, struct file *filp)
2471 +{
2472 + struct au1xxx_dock *dock = &dock_info;
2473 +
2474 + MOD_INC_USE_COUNT;
2475 +
2476 + filp->private_data = dock;
2477 +
2478 + if (dock->open_count++ == 0) {
2479 + dock_task.data = dock;
2480 + cleanup_flag = 0;
2481 + queue_task(&dock_task, &tq_timer);
2482 + }
2483 +
2484 + return 0;
2485 +}
2486 +
2487 +
2488 +static unsigned int au1xxx_dock_poll(struct file *filp, poll_table *wait)
2489 +{
2490 + struct au1xxx_dock *dock = filp->private_data;
2491 + int ret = 0;
2492 +
2493 + DPRINTK("start\n");
2494 + poll_wait(filp, &dock->read_wait, wait);
2495 + if (dock->current != dock->last) {
2496 + ret = POLLIN | POLLRDNORM;
2497 + }
2498 + return ret;
2499 +}
2500 +
2501 +
2502 +static int au1xxx_dock_release(struct inode *inode, struct file *filp)
2503 +{
2504 + struct au1xxx_dock *dock = filp->private_data;
2505 +
2506 + DPRINTK("start\n");
2507 +
2508 + if (--dock->open_count == 0) {
2509 + cleanup_flag = 1;
2510 + sleep_on(&cleanup_wait_queue);
2511 + }
2512 + MOD_DEC_USE_COUNT;
2513 +
2514 + return 0;
2515 +}
2516 +
2517 +
2518 +
2519 +static struct file_operations au1xxx_dock_fops = {
2520 + owner: THIS_MODULE,
2521 + read: au1xxx_dock_read,
2522 + poll: au1xxx_dock_poll,
2523 + open: au1xxx_dock_open,
2524 + release: au1xxx_dock_release,
2525 +};
2526 +
2527 +/*
2528 + * The au1xxx dock is a misc device:
2529 + * Major 10 char
2530 + * Minor 22 /dev/dock
2531 + *
2532 + * This is /dev/misc/dock if devfs is used.
2533 + */
2534 +
2535 +static struct miscdevice au1xxx_dock_dev = {
2536 + minor: 23,
2537 + name: "dock",
2538 + fops: &au1xxx_dock_fops,
2539 +};
2540 +
2541 +static int __init au1xxx_dock_init(void)
2542 +{
2543 + struct au1xxx_dock *dock = &dock_info;
2544 + int ret;
2545 +
2546 + DPRINTK("Initializing dock driver\n");
2547 + dock->open_count = 0;
2548 + cleanup_flag = 0;
2549 + init_waitqueue_head(&dock->read_wait);
2550 +
2551 +
2552 + /* yamon configures GPIO pins for the dock
2553 + * no initialization needed
2554 + */
2555 +
2556 + ret = misc_register(&au1xxx_dock_dev);
2557 +
2558 + DPRINTK("dock driver fully initialized.\n");
2559 +
2560 + return ret;
2561 +}
2562 +
2563 +
2564 +static void __exit au1xxx_dock_exit(void)
2565 +{
2566 + DPRINTK("unloading dock driver\n");
2567 + misc_deregister(&au1xxx_dock_dev);
2568 +}
2569 +
2570 +
2571 +module_init(au1xxx_dock_init);
2572 +module_exit(au1xxx_dock_exit);
2573 diff -Nur linux-2.4.30/arch/mips/au1000/ficmmp/board_setup.c linux-2.4.30-mips/arch/mips/au1000/ficmmp/board_setup.c
2574 --- linux-2.4.30/arch/mips/au1000/ficmmp/board_setup.c 1970-01-01 01:00:00.000000000 +0100
2575 +++ linux-2.4.30-mips/arch/mips/au1000/ficmmp/board_setup.c 2005-03-19 08:17:51.000000000 +0100
2576 @@ -0,0 +1,226 @@
2577 +/*
2578 + *
2579 + * BRIEF MODULE DESCRIPTION
2580 + * Alchemy Pb1200 board setup.
2581 + *
2582 + * This program is free software; you can redistribute it and/or modify it
2583 + * under the terms of the GNU General Public License as published by the
2584 + * Free Software Foundation; either version 2 of the License, or (at your
2585 + * option) any later version.
2586 + *
2587 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2588 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2589 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2590 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2591 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2592 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2593 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2594 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2595 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2596 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2597 + *
2598 + * You should have received a copy of the GNU General Public License along
2599 + * with this program; if not, write to the Free Software Foundation, Inc.,
2600 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2601 + */
2602 +#include <linux/config.h>
2603 +#include <linux/init.h>
2604 +#include <linux/sched.h>
2605 +#include <linux/ioport.h>
2606 +#include <linux/mm.h>
2607 +#include <linux/console.h>
2608 +#include <linux/mc146818rtc.h>
2609 +#include <linux/delay.h>
2610 +#include <linux/ide.h>
2611 +
2612 +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
2613 +#include <linux/ide.h>
2614 +#endif
2615 +
2616 +#include <asm/cpu.h>
2617 +#include <asm/bootinfo.h>
2618 +#include <asm/irq.h>
2619 +#include <asm/keyboard.h>
2620 +#include <asm/mipsregs.h>
2621 +#include <asm/reboot.h>
2622 +#include <asm/pgtable.h>
2623 +#include <asm/au1000.h>
2624 +#include <asm/ficmmp.h>
2625 +#include <asm/au1xxx_dbdma.h>
2626 +#include <asm/au1xxx_gpio.h>
2627 +
2628 +extern struct rtc_ops no_rtc_ops;
2629 +
2630 +/* value currently in the board configuration register */
2631 +u16 ficmmp_config = 0;
2632 +
2633 +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
2634 +extern struct ide_ops *ide_ops;
2635 +extern struct ide_ops au1xxx_ide_ops;
2636 +extern u32 au1xxx_ide_virtbase;
2637 +extern u64 au1xxx_ide_physbase;
2638 +extern int au1xxx_ide_irq;
2639 +
2640 +u32 led_base_addr;
2641 +/* Ddma */
2642 +chan_tab_t *ide_read_ch, *ide_write_ch;
2643 +u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma
2644 +
2645 +dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 };
2646 +#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */
2647 +
2648 +void board_reset (void)
2649 +{
2650 + au_writel(0, 0xAD80001C);
2651 +}
2652 +
2653 +void board_power_off (void)
2654 +{
2655 +}
2656 +
2657 +void __init board_setup(void)
2658 +{
2659 + char *argptr = NULL;
2660 + u32 pin_func;
2661 + rtc_ops = &no_rtc_ops;
2662 +
2663 + ficmmp_config_init(); //Initialize FIC control register
2664 +
2665 +#if 0
2666 + /* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
2667 + * but it is board specific code, so put it here.
2668 + */
2669 + pin_func = au_readl(SYS_PINFUNC);
2670 + au_sync();
2671 + pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
2672 + au_writel(pin_func, SYS_PINFUNC);
2673 +
2674 + au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
2675 + au_sync();
2676 +#endif
2677 +
2678 +#if defined( CONFIG_I2C_ALGO_AU1550 )
2679 + {
2680 + u32 freq0, clksrc;
2681 +
2682 + /* Select SMBUS in CPLD */
2683 + /* bcsr->resets &= ~(BCSR_RESETS_PCS0MUX); */
2684 +
2685 + pin_func = au_readl(SYS_PINFUNC);
2686 + au_sync();
2687 + pin_func &= ~(3<<17 | 1<<4);
2688 + /* Set GPIOs correctly */
2689 + pin_func |= 2<<17;
2690 + au_writel(pin_func, SYS_PINFUNC);
2691 + au_sync();
2692 +
2693 + /* The i2c driver depends on 50Mhz clock */
2694 + freq0 = au_readl(SYS_FREQCTRL0);
2695 + au_sync();
2696 + freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
2697 + freq0 |= (3<<SYS_FC_FRDIV1_BIT);
2698 + /* 396Mhz / (3+1)*2 == 49.5Mhz */
2699 + au_writel(freq0, SYS_FREQCTRL0);
2700 + au_sync();
2701 + freq0 |= SYS_FC_FE1;
2702 + au_writel(freq0, SYS_FREQCTRL0);
2703 + au_sync();
2704 +
2705 + clksrc = au_readl(SYS_CLKSRC);
2706 + au_sync();
2707 + clksrc &= ~0x01f00000;
2708 + /* bit 22 is EXTCLK0 for PSC0 */
2709 + clksrc |= (0x3 << 22);
2710 + au_writel(clksrc, SYS_CLKSRC);
2711 + au_sync();
2712 + }
2713 +#endif
2714 +
2715 +#ifdef CONFIG_FB_AU1200
2716 + argptr = prom_getcmdline();
2717 + strcat(argptr, " video=au1200fb:");
2718 +#endif
2719 +
2720 +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
2721 + /*
2722 + * Iniz IDE parameters
2723 + */
2724 + ide_ops = &au1xxx_ide_ops;
2725 + au1xxx_ide_irq = FICMMP_IDE_INT;
2726 + au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR;
2727 + au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR);
2728 + switch4ddma = 0;
2729 + /*
2730 + ide_ops = &au1xxx_ide_ops;
2731 + au1xxx_ide_irq = FICMMP_IDE_INT;
2732 + au1xxx_ide_base = KSEG1ADDR(AU1XXX_ATA_BASE);
2733 + */
2734 + au1xxx_gpio_write(9, 1);
2735 + printk("B4001010: %X\n", *((u32*)0xB4001010));
2736 + printk("B4001014: %X\n", *((u32*)0xB4001014));
2737 + printk("B4001018: %X\n", *((u32*)0xB4001018));
2738 + printk("B1900100: %X\n", *((u32*)0xB1900100));
2739 +
2740 +#if 0
2741 + ficmmp_config_clear(FICMMP_CONFIG_IDERST);
2742 + mdelay(100);
2743 + ficmmp_config_set(FICMMP_CONFIG_IDERST);
2744 + mdelay(100);
2745 +#endif
2746 + /*
2747 + * change PIO or PIO+Ddma
2748 + * check the GPIO-5 pin condition. pb1200:s18_dot
2749 + */
2750 +/* switch4ddma = 0; //(au_readl(SYS_PINSTATERD) & (1 << 5)) ? 1 : 0; */
2751 +#endif
2752 +
2753 + /* The Pb1200 development board uses external MUX for PSC0 to
2754 + support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
2755 + */
2756 +#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550)
2757 + #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\
2758 + Refer to Pb1200 documentation.
2759 +#elif defined( CONFIG_AU1550_PSC_SPI )
2760 + //bcsr->resets |= BCSR_RESETS_PCS0MUX;
2761 +#elif defined( CONFIG_I2C_ALGO_AU1550 )
2762 + //bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
2763 +#endif
2764 + au_sync();
2765 +
2766 + printk("FIC Multimedia Player Board\n");
2767 + au1xxx_gpio_tristate(5);
2768 + printk("B1900100: %X\n", *((volatile u32*)0xB1900100));
2769 + printk("B190002C: %X\n", *((volatile u32*)0xB190002C));
2770 +}
2771 +
2772 +int
2773 +board_au1200fb_panel (void)
2774 +{
2775 + au1xxx_gpio_tristate(6);
2776 +
2777 + if (au1xxx_gpio_read(12) == 0)
2778 + return 9; /* FS453_640x480 (Composite/S-Video) */
2779 + else
2780 + return 7; /* Sharp 320x240 TFT */
2781 +}
2782 +
2783 +int
2784 +board_au1200fb_panel_init (void)
2785 +{
2786 + /*Enable data buffers*/
2787 + ficmmp_config_clear(FICMMP_CONFIG_LCMDATAOUT);
2788 + /*Take LCD out of reset*/
2789 + ficmmp_config_set(FICMMP_CONFIG_LCMPWREN | FICMMP_CONFIG_LCMEN);
2790 + return 0;
2791 +}
2792 +
2793 +int
2794 +board_au1200fb_panel_shutdown (void)
2795 +{
2796 + /*Disable data buffers*/
2797 + ficmmp_config_set(FICMMP_CONFIG_LCMDATAOUT);
2798 + /*Put LCD in reset, remove power*/
2799 + ficmmp_config_clear(FICMMP_CONFIG_LCMEN | FICMMP_CONFIG_LCMPWREN);
2800 + return 0;
2801 +}
2802 +
2803 diff -Nur linux-2.4.30/arch/mips/au1000/ficmmp/init.c linux-2.4.30-mips/arch/mips/au1000/ficmmp/init.c
2804 --- linux-2.4.30/arch/mips/au1000/ficmmp/init.c 1970-01-01 01:00:00.000000000 +0100
2805 +++ linux-2.4.30-mips/arch/mips/au1000/ficmmp/init.c 2005-01-30 09:01:27.000000000 +0100
2806 @@ -0,0 +1,76 @@
2807 +/*
2808 + *
2809 + * BRIEF MODULE DESCRIPTION
2810 + * PB1200 board setup
2811 + *
2812 + * This program is free software; you can redistribute it and/or modify it
2813 + * under the terms of the GNU General Public License as published by the
2814 + * Free Software Foundation; either version 2 of the License, or (at your
2815 + * option) any later version.
2816 + *
2817 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2818 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2819 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2820 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2821 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2822 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2823 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2824 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2825 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2826 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2827 + *
2828 + * You should have received a copy of the GNU General Public License along
2829 + * with this program; if not, write to the Free Software Foundation, Inc.,
2830 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2831 + */
2832 +
2833 +#include <linux/init.h>
2834 +#include <linux/mm.h>
2835 +#include <linux/sched.h>
2836 +#include <linux/bootmem.h>
2837 +#include <asm/addrspace.h>
2838 +#include <asm/bootinfo.h>
2839 +#include <linux/config.h>
2840 +#include <linux/string.h>
2841 +#include <linux/kernel.h>
2842 +#include <linux/sched.h>
2843 +
2844 +int prom_argc;
2845 +char **prom_argv, **prom_envp;
2846 +extern void __init prom_init_cmdline(void);
2847 +extern char *prom_getenv(char *envname);
2848 +
2849 +const char *get_system_type(void)
2850 +{
2851 + return "FIC Multimedia Player (Au1200)";
2852 +}
2853 +
2854 +u32 mae_memsize = 0;
2855 +
2856 +int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
2857 +{
2858 + unsigned char *memsize_str;
2859 + unsigned long memsize;
2860 +
2861 + prom_argc = argc;
2862 + prom_argv = argv;
2863 + prom_envp = envp;
2864 +
2865 + mips_machgroup = MACH_GROUP_ALCHEMY;
2866 + mips_machtype = MACH_PB1000; /* set the platform # */
2867 + prom_init_cmdline();
2868 +
2869 + memsize_str = prom_getenv("memsize");
2870 + if (!memsize_str) {
2871 + memsize = 0x08000000;
2872 + } else {
2873 + memsize = simple_strtol(memsize_str, NULL, 0);
2874 + }
2875 +
2876 + /* reserved 32MB for MAE driver */
2877 + memsize -= (32 * 1024 * 1024);
2878 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2879 + mae_memsize = memsize; /* for drivers/char/au1xxx_mae.c */
2880 + return 0;
2881 +}
2882 +
2883 diff -Nur linux-2.4.30/arch/mips/au1000/ficmmp/irqmap.c linux-2.4.30-mips/arch/mips/au1000/ficmmp/irqmap.c
2884 --- linux-2.4.30/arch/mips/au1000/ficmmp/irqmap.c 1970-01-01 01:00:00.000000000 +0100
2885 +++ linux-2.4.30-mips/arch/mips/au1000/ficmmp/irqmap.c 2005-01-30 09:01:27.000000000 +0100
2886 @@ -0,0 +1,61 @@
2887 +/*
2888 + * BRIEF MODULE DESCRIPTION
2889 + * Au1xxx irq map table
2890 + *
2891 + * This program is free software; you can redistribute it and/or modify it
2892 + * under the terms of the GNU General Public License as published by the
2893 + * Free Software Foundation; either version 2 of the License, or (at your
2894 + * option) any later version.
2895 + *
2896 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
2897 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
2898 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
2899 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
2900 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
2901 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
2902 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
2903 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
2904 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
2905 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2906 + *
2907 + * You should have received a copy of the GNU General Public License along
2908 + * with this program; if not, write to the Free Software Foundation, Inc.,
2909 + * 675 Mass Ave, Cambridge, MA 02139, USA.
2910 + */
2911 +#include <linux/errno.h>
2912 +#include <linux/init.h>
2913 +#include <linux/irq.h>
2914 +#include <linux/kernel_stat.h>
2915 +#include <linux/module.h>
2916 +#include <linux/signal.h>
2917 +#include <linux/sched.h>
2918 +#include <linux/types.h>
2919 +#include <linux/interrupt.h>
2920 +#include <linux/ioport.h>
2921 +#include <linux/timex.h>
2922 +#include <linux/slab.h>
2923 +#include <linux/random.h>
2924 +#include <linux/delay.h>
2925 +
2926 +#include <asm/bitops.h>
2927 +#include <asm/bootinfo.h>
2928 +#include <asm/io.h>
2929 +#include <asm/mipsregs.h>
2930 +#include <asm/system.h>
2931 +#include <asm/au1000.h>
2932 +#include <asm/ficmmp.h>
2933 +
2934 +au1xxx_irq_map_t au1xxx_irq_map[] = {
2935 + { FICMMP_IDE_INT, INTC_INT_HIGH_LEVEL, 0 },
2936 + { AU1XXX_SMC91111_IRQ, INTC_INT_HIGH_LEVEL, 0 },
2937 + { AU1000_GPIO_1 , INTC_INT_FALL_EDGE, 0 }, // main button
2938 + { AU1000_GPIO_6 , INTC_INT_RISE_EDGE, 0 }, // select button
2939 + { AU1000_GPIO_12, INTC_INT_FALL_EDGE, 0 }, // guide button
2940 + { AU1000_GPIO_17, INTC_INT_RISE_EDGE, 0 }, // down button
2941 + { AU1000_GPIO_19, INTC_INT_RISE_EDGE, 0 }, // left button
2942 + { AU1000_GPIO_26, INTC_INT_RISE_EDGE, 0 }, // right button
2943 + { AU1000_GPIO_28, INTC_INT_RISE_EDGE, 0 }, // up button
2944 +};
2945 +
2946 +int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
2947 +
2948 diff -Nur linux-2.4.30/arch/mips/au1000/hydrogen3/Makefile linux-2.4.30-mips/arch/mips/au1000/hydrogen3/Makefile
2949 --- linux-2.4.30/arch/mips/au1000/hydrogen3/Makefile 2005-01-19 15:09:26.000000000 +0100
2950 +++ linux-2.4.30-mips/arch/mips/au1000/hydrogen3/Makefile 2005-02-11 22:09:55.000000000 +0100
2951 @@ -14,6 +14,11 @@
2952
2953 O_TARGET := hydrogen3.o
2954
2955 -obj-y := init.o board_setup.o irqmap.o
2956 +obj-y := init.o board_setup.o irqmap.o buttons.o
2957 +
2958 +ifdef CONFIG_MMC
2959 +obj-y += mmc_support.o
2960 +export-objs +=mmc_support.o
2961 +endif
2962
2963 include $(TOPDIR)/Rules.make
2964 diff -Nur linux-2.4.30/arch/mips/au1000/hydrogen3/board_setup.c linux-2.4.30-mips/arch/mips/au1000/hydrogen3/board_setup.c
2965 --- linux-2.4.30/arch/mips/au1000/hydrogen3/board_setup.c 2005-01-19 15:09:26.000000000 +0100
2966 +++ linux-2.4.30-mips/arch/mips/au1000/hydrogen3/board_setup.c 2005-03-19 08:17:51.000000000 +0100
2967 @@ -51,12 +51,19 @@
2968 {
2969 }
2970
2971 +void board_power_off (void)
2972 +{
2973 +}
2974 +
2975 void __init board_setup(void)
2976 {
2977 u32 pin_func;
2978
2979 rtc_ops = &no_rtc_ops;
2980
2981 + /* Set GPIO14 high to make CD/DAT1 high for MMC to work */
2982 + au_writel(1<<14, SYS_OUTPUTSET);
2983 +
2984 #ifdef CONFIG_AU1X00_USB_DEVICE
2985 // 2nd USB port is USB device
2986 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000);
2987 diff -Nur linux-2.4.30/arch/mips/au1000/hydrogen3/buttons.c linux-2.4.30-mips/arch/mips/au1000/hydrogen3/buttons.c
2988 --- linux-2.4.30/arch/mips/au1000/hydrogen3/buttons.c 1970-01-01 01:00:00.000000000 +0100
2989 +++ linux-2.4.30-mips/arch/mips/au1000/hydrogen3/buttons.c 2005-02-11 22:09:55.000000000 +0100
2990 @@ -0,0 +1,308 @@
2991 +/*
2992 + * Copyright (C) 2003 Metrowerks, All Rights Reserved.
2993 + *
2994 + * This program is free software; you can redistribute it and/or modify
2995 + * it under the terms of the GNU General Public License version 2 as
2996 + * published by the Free Software Foundation.
2997 + */
2998 +
2999 +#include <linux/config.h>
3000 +#include <linux/module.h>
3001 +#include <linux/init.h>
3002 +#include <linux/fs.h>
3003 +#include <linux/sched.h>
3004 +#include <linux/miscdevice.h>
3005 +#include <linux/errno.h>
3006 +#include <linux/poll.h>
3007 +#include <asm/au1000.h>
3008 +#include <asm/uaccess.h>
3009 +
3010 +#define BUTTON_SELECT (1<<1)
3011 +#define BUTTON_1 (1<<2)
3012 +#define BUTTON_2 (1<<3)
3013 +#define BUTTON_ONOFF (1<<6)
3014 +#define BUTTON_3 (1<<7)
3015 +#define BUTTON_4 (1<<8)
3016 +#define BUTTON_LEFT (1<<9)
3017 +#define BUTTON_DOWN (1<<10)
3018 +#define BUTTON_RIGHT (1<<11)
3019 +#define BUTTON_UP (1<<12)
3020 +
3021 +#define BUTTON_MASK (\
3022 + BUTTON_SELECT \
3023 + | BUTTON_1 \
3024 + | BUTTON_2 \
3025 + | BUTTON_ONOFF \
3026 + | BUTTON_3 \
3027 + | BUTTON_4 \
3028 + | BUTTON_LEFT \
3029 + | BUTTON_DOWN \
3030 + | BUTTON_RIGHT \
3031 + | BUTTON_UP \
3032 + )
3033 +
3034 +#define BUTTON_INVERT (\
3035 + BUTTON_SELECT \
3036 + | BUTTON_1 \
3037 + | BUTTON_2 \
3038 + | BUTTON_3 \
3039 + | BUTTON_4 \
3040 + | BUTTON_LEFT \
3041 + | BUTTON_DOWN \
3042 + | BUTTON_RIGHT \
3043 + | BUTTON_UP \
3044 + )
3045 +
3046 +
3047 +
3048 +#define MAKE_FLAG 0x20
3049 +
3050 +#undef DEBUG
3051 +
3052 +#define DEBUG 0
3053 +//#define DEBUG 1
3054 +
3055 +#if DEBUG
3056 +#define DPRINTK(format, args...) printk(__FUNCTION__ ": " format, ## args)
3057 +#else
3058 +#define DPRINTK(format, args...) do { } while (0)
3059 +#endif
3060 +
3061 +/* Please note that this driver is based on a timer and is not interrupt
3062 + * driven. If you are going to make use of this driver, you will need to have
3063 + * your application open the buttons listing from the /dev directory first.
3064 + */
3065 +
3066 +struct hydrogen3_buttons {
3067 + struct fasync_struct *fasync;
3068 + wait_queue_head_t read_wait;
3069 + int open_count;
3070 + unsigned int debounce;
3071 + unsigned int current;
3072 + unsigned int last;
3073 +};
3074 +
3075 +static struct hydrogen3_buttons buttons_info;
3076 +
3077 +
3078 +static void button_timer_periodic(void *data);
3079 +
3080 +static struct tq_struct button_task = {
3081 + routine: button_timer_periodic,
3082 + data: NULL
3083 +};
3084 +
3085 +static int cleanup_flag = 0;
3086 +static DECLARE_WAIT_QUEUE_HEAD(cleanup_wait_queue);
3087 +
3088 +
3089 +static unsigned int read_button_state(void)
3090 +{
3091 + unsigned long state;
3092 +
3093 + state = inl(SYS_PINSTATERD) & BUTTON_MASK;
3094 + state ^= BUTTON_INVERT;
3095 +
3096 + DPRINTK( "Current Button State: %d\n", state );
3097 +
3098 + return state;
3099 +}
3100 +
3101 +
3102 +static void button_timer_periodic(void *data)
3103 +{
3104 + struct hydrogen3_buttons *buttons = (struct hydrogen3_buttons *)data;
3105 + unsigned long button_state;
3106 +
3107 + // If cleanup wants us to die
3108 + if (cleanup_flag) {
3109 + wake_up(&cleanup_wait_queue); // now cleanup_module can return
3110 + } else {
3111 + queue_task(&button_task, &tq_timer); // put ourselves back in the task queue
3112 + }
3113 +
3114 + // read current buttons
3115 + button_state = read_button_state();
3116 +
3117 + // if no buttons are down and nothing to do then
3118 + // save time and be done.
3119 + if ((button_state == 0) && (buttons->current == 0)) {
3120 + return;
3121 + }
3122 +
3123 + if (button_state == buttons->debounce) {
3124 + buttons->current = button_state;
3125 + } else {
3126 + buttons->debounce = button_state;
3127 + }
3128 +// printk("0x%04x\n", button_state);
3129 + if (buttons->current != buttons->last) {
3130 + if (waitqueue_active(&buttons->read_wait)) {
3131 + wake_up_interruptible(&buttons->read_wait);
3132 + }
3133 + }
3134 +}
3135 +
3136 +
3137 +static ssize_t hydrogen3_buttons_read(struct file *filp, char *buffer, size_t count, loff_t *ppos)
3138 +{
3139 + struct hydrogen3_buttons *buttons = filp->private_data;
3140 + char events[16];
3141 + int index;
3142 + int last;
3143 + int cur;
3144 + int bit;
3145 + int bit_mask;
3146 + int err;
3147 +
3148 + DPRINTK("start\n");
3149 +
3150 +try_again:
3151 +
3152 + while (buttons->current == buttons->last) {
3153 + if (filp->f_flags & O_NONBLOCK) {
3154 + return -EAGAIN;
3155 + }
3156 + interruptible_sleep_on(&buttons->read_wait);
3157 + if (signal_pending(current)) {
3158 + return -ERESTARTSYS;
3159 + }
3160 + }
3161 +
3162 + cur = buttons->current;
3163 + last = buttons->last;
3164 +
3165 + index = 0;
3166 + bit_mask = 1;
3167 + for (bit = 0; (bit < 16) && count; bit++) {
3168 + if ((cur ^ last) & bit_mask) {
3169 + if (cur & bit_mask) {
3170 + events[index] = (bit | MAKE_FLAG) + 'A';
3171 + last |= bit_mask;
3172 + } else {
3173 + events[index] = bit + 'A';
3174 + last &= ~bit_mask;
3175 + }
3176 + index++;
3177 + count--;
3178 + }
3179 + bit_mask <<= 1;
3180 + }
3181 + buttons->last = last;
3182 +
3183 + if (index == 0) {
3184 + goto try_again;
3185 + }
3186 +
3187 + err = copy_to_user(buffer, events, index);
3188 + if (err) {
3189 + return err;
3190 + }
3191 +
3192 + return index;
3193 +}
3194 +
3195 +
3196 +static int hydrogen3_buttons_open(struct inode *inode, struct file *filp)
3197 +{
3198 + struct hydrogen3_buttons *buttons = &buttons_info;
3199 +
3200 + DPRINTK("start\n");
3201 + MOD_INC_USE_COUNT;
3202 +
3203 + filp->private_data = buttons;
3204 +
3205 + if (buttons->open_count++ == 0) {
3206 + button_task.data = buttons;
3207 + cleanup_flag = 0;
3208 + queue_task(&button_task, &tq_timer);
3209 + }
3210 +
3211 + return 0;
3212 +}
3213 +
3214 +
3215 +static unsigned int hydrogen3_buttons_poll(struct file *filp, poll_table *wait)
3216 +{
3217 + struct hydrogen3_buttons *buttons = filp->private_data;
3218 + int ret = 0;
3219 +
3220 + DPRINTK("start\n");
3221 + poll_wait(filp, &buttons->read_wait, wait);
3222 + if (buttons->current != buttons->last) {
3223 + ret = POLLIN | POLLRDNORM;
3224 + }
3225 + return ret;
3226 +}
3227 +
3228 +
3229 +static int hydrogen3_buttons_release(struct inode *inode, struct file *filp)
3230 +{
3231 + struct hydrogen3_buttons *buttons = filp->private_data;
3232 +
3233 + DPRINTK("start\n");
3234 +
3235 + if (--buttons->open_count == 0) {
3236 + cleanup_flag = 1;
3237 + sleep_on(&cleanup_wait_queue);
3238 + }
3239 + MOD_DEC_USE_COUNT;
3240 +
3241 + return 0;
3242 +}
3243 +
3244 +
3245 +
3246 +static struct file_operations hydrogen3_buttons_fops = {
3247 + owner: THIS_MODULE,
3248 + read: hydrogen3_buttons_read,
3249 + poll: hydrogen3_buttons_poll,
3250 + open: hydrogen3_buttons_open,
3251 + release: hydrogen3_buttons_release,
3252 +};
3253 +
3254 +/*
3255 + * The hydrogen3 buttons is a misc device:
3256 + * Major 10 char
3257 + * Minor 22 /dev/buttons
3258 + *
3259 + * This is /dev/misc/buttons if devfs is used.
3260 + */
3261 +
3262 +static struct miscdevice hydrogen3_buttons_dev = {
3263 + minor: 22,
3264 + name: "buttons",
3265 + fops: &hydrogen3_buttons_fops,
3266 +};
3267 +
3268 +static int __init hydrogen3_buttons_init(void)
3269 +{
3270 + struct hydrogen3_buttons *buttons = &buttons_info;
3271 + int ret;
3272 +
3273 + DPRINTK("Initializing buttons driver\n");
3274 + buttons->open_count = 0;
3275 + cleanup_flag = 0;
3276 + init_waitqueue_head(&buttons->read_wait);
3277 +
3278 +
3279 + // yamon configures GPIO pins for the buttons
3280 + // no initialization needed
3281 +
3282 + ret = misc_register(&hydrogen3_buttons_dev);
3283 +
3284 + DPRINTK("Buttons driver fully initialized.\n");
3285 +
3286 + return ret;
3287 +}
3288 +
3289 +
3290 +static void __exit hydrogen3_buttons_exit(void)
3291 +{
3292 + DPRINTK("unloading buttons driver\n");
3293 + misc_deregister(&hydrogen3_buttons_dev);
3294 +}
3295 +
3296 +
3297 +module_init(hydrogen3_buttons_init);
3298 +module_exit(hydrogen3_buttons_exit);
3299 diff -Nur linux-2.4.30/arch/mips/au1000/hydrogen3/mmc_support.c linux-2.4.30-mips/arch/mips/au1000/hydrogen3/mmc_support.c
3300 --- linux-2.4.30/arch/mips/au1000/hydrogen3/mmc_support.c 1970-01-01 01:00:00.000000000 +0100
3301 +++ linux-2.4.30-mips/arch/mips/au1000/hydrogen3/mmc_support.c 2005-02-02 05:27:06.000000000 +0100
3302 @@ -0,0 +1,89 @@
3303 +/*
3304 + * BRIEF MODULE DESCRIPTION
3305 + *
3306 + * MMC support routines for Hydrogen3.
3307 + *
3308 + *
3309 + * Copyright (c) 2003-2004 Embedded Edge, LLC.
3310 + * Author: Embedded Edge, LLC.
3311 + * Contact: dan@embeddededge.com
3312 + *
3313 + * This program is free software; you can redistribute it and/or modify it
3314 + * under the terms of the GNU General Public License as published by the
3315 + * Free Software Foundation; either version 2 of the License, or (at your
3316 + * option) any later version.
3317 + *
3318 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3319 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3320 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3321 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3322 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3323 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3324 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3325 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3326 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3327 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3328 + *
3329 + * You should have received a copy of the GNU General Public License along
3330 + * with this program; if not, write to the Free Software Foundation, Inc.,
3331 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3332 + *
3333 + */
3334 +
3335 +
3336 +#include <linux/config.h>
3337 +#include <linux/kernel.h>
3338 +#include <linux/module.h>
3339 +#include <linux/init.h>
3340 +
3341 +#include <asm/irq.h>
3342 +#include <asm/au1000.h>
3343 +#include <asm/au1100_mmc.h>
3344 +
3345 +#define GPIO_17_WP 0x20000
3346 +
3347 +/* SD/MMC controller support functions */
3348 +
3349 +/*
3350 + * Detect card.
3351 + */
3352 +void mmc_card_inserted(int _n_, int *_res_)
3353 +{
3354 + u32 gpios = au_readl(SYS_PINSTATERD);
3355 + u32 emptybit = (1<<16);
3356 + *_res_ = ((gpios & emptybit) == 0);
3357 +}
3358 +
3359 +/*
3360 + * Check card write protection.
3361 + */
3362 +void mmc_card_writable(int _n_, int *_res_)
3363 +{
3364 + unsigned long mmc_wp, board_specific;
3365 + board_specific = au_readl(SYS_OUTPUTSET);
3366 + mmc_wp=GPIO_17_WP;
3367 + if (!(board_specific & mmc_wp)) {/* low means card writable */
3368 + *_res_ = 1;
3369 + } else {
3370 + *_res_ = 0;
3371 + }
3372 +}
3373 +/*
3374 + * Apply power to card slot.
3375 + */
3376 +void mmc_power_on(int _n_)
3377 +{
3378 +}
3379 +
3380 +/*
3381 + * Remove power from card slot.
3382 + */
3383 +void mmc_power_off(int _n_)
3384 +{
3385 +}
3386 +
3387 +EXPORT_SYMBOL(mmc_card_inserted);
3388 +EXPORT_SYMBOL(mmc_card_writable);
3389 +EXPORT_SYMBOL(mmc_power_on);
3390 +EXPORT_SYMBOL(mmc_power_off);
3391 +
3392 diff -Nur linux-2.4.30/arch/mips/au1000/mtx-1/board_setup.c linux-2.4.30-mips/arch/mips/au1000/mtx-1/board_setup.c
3393 --- linux-2.4.30/arch/mips/au1000/mtx-1/board_setup.c 2004-02-18 14:36:30.000000000 +0100
3394 +++ linux-2.4.30-mips/arch/mips/au1000/mtx-1/board_setup.c 2004-11-26 09:37:16.000000000 +0100
3395 @@ -48,6 +48,12 @@
3396
3397 extern struct rtc_ops no_rtc_ops;
3398
3399 +void board_reset (void)
3400 +{
3401 + /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
3402 + au_writel(0x00000000, 0xAE00001C);
3403 +}
3404 +
3405 void __init board_setup(void)
3406 {
3407 rtc_ops = &no_rtc_ops;
3408 diff -Nur linux-2.4.30/arch/mips/au1000/mtx-1/irqmap.c linux-2.4.30-mips/arch/mips/au1000/mtx-1/irqmap.c
3409 --- linux-2.4.30/arch/mips/au1000/mtx-1/irqmap.c 2005-01-19 15:09:26.000000000 +0100
3410 +++ linux-2.4.30-mips/arch/mips/au1000/mtx-1/irqmap.c 2004-11-26 09:37:16.000000000 +0100
3411 @@ -72,10 +72,10 @@
3412 * A B C D
3413 */
3414 {
3415 - {INTA, INTB, INTC, INTD}, /* IDSEL 0 */
3416 - {INTA, INTB, INTC, INTD}, /* IDSEL 1 */
3417 - {INTA, INTB, INTC, INTD}, /* IDSEL 2 */
3418 - {INTA, INTB, INTC, INTD}, /* IDSEL 3 */
3419 + {INTA, INTB, INTX, INTX}, /* IDSEL 0 */
3420 + {INTB, INTA, INTX, INTX}, /* IDSEL 1 */
3421 + {INTC, INTD, INTX, INTX}, /* IDSEL 2 */
3422 + {INTD, INTC, INTX, INTX}, /* IDSEL 3 */
3423 };
3424 const long min_idsel = 0, max_idsel = 3, irqs_per_slot = 4;
3425 return PCI_IRQ_TABLE_LOOKUP;
3426 diff -Nur linux-2.4.30/arch/mips/au1000/pb1000/board_setup.c linux-2.4.30-mips/arch/mips/au1000/pb1000/board_setup.c
3427 --- linux-2.4.30/arch/mips/au1000/pb1000/board_setup.c 2005-01-19 15:09:26.000000000 +0100
3428 +++ linux-2.4.30-mips/arch/mips/au1000/pb1000/board_setup.c 2005-03-19 08:17:51.000000000 +0100
3429 @@ -58,6 +58,10 @@
3430 {
3431 }
3432
3433 +void board_power_off (void)
3434 +{
3435 +}
3436 +
3437 void __init board_setup(void)
3438 {
3439 u32 pin_func, static_cfg0;
3440 diff -Nur linux-2.4.30/arch/mips/au1000/pb1100/Makefile linux-2.4.30-mips/arch/mips/au1000/pb1100/Makefile
3441 --- linux-2.4.30/arch/mips/au1000/pb1100/Makefile 2003-08-25 13:44:39.000000000 +0200
3442 +++ linux-2.4.30-mips/arch/mips/au1000/pb1100/Makefile 2005-01-30 09:10:29.000000000 +0100
3443 @@ -16,4 +16,10 @@
3444
3445 obj-y := init.o board_setup.o irqmap.o
3446
3447 +
3448 +ifdef CONFIG_MMC
3449 +obj-y += mmc_support.o
3450 +export-objs += mmc_support.o
3451 +endif
3452 +
3453 include $(TOPDIR)/Rules.make
3454 diff -Nur linux-2.4.30/arch/mips/au1000/pb1100/board_setup.c linux-2.4.30-mips/arch/mips/au1000/pb1100/board_setup.c
3455 --- linux-2.4.30/arch/mips/au1000/pb1100/board_setup.c 2005-01-19 15:09:26.000000000 +0100
3456 +++ linux-2.4.30-mips/arch/mips/au1000/pb1100/board_setup.c 2005-03-19 08:17:51.000000000 +0100
3457 @@ -62,6 +62,10 @@
3458 au_writel(0x00000000, 0xAE00001C);
3459 }
3460
3461 +void board_power_off (void)
3462 +{
3463 +}
3464 +
3465 void __init board_setup(void)
3466 {
3467 u32 pin_func;
3468 diff -Nur linux-2.4.30/arch/mips/au1000/pb1100/mmc_support.c linux-2.4.30-mips/arch/mips/au1000/pb1100/mmc_support.c
3469 --- linux-2.4.30/arch/mips/au1000/pb1100/mmc_support.c 1970-01-01 01:00:00.000000000 +0100
3470 +++ linux-2.4.30-mips/arch/mips/au1000/pb1100/mmc_support.c 2005-01-30 09:10:29.000000000 +0100
3471 @@ -0,0 +1,126 @@
3472 +/*
3473 + * BRIEF MODULE DESCRIPTION
3474 + *
3475 + * MMC support routines for PB1100.
3476 + *
3477 + *
3478 + * Copyright (c) 2003-2004 Embedded Edge, LLC.
3479 + * Author: Embedded Edge, LLC.
3480 + * Contact: dan@embeddededge.com
3481 + *
3482 + * This program is free software; you can redistribute it and/or modify it
3483 + * under the terms of the GNU General Public License as published by the
3484 + * Free Software Foundation; either version 2 of the License, or (at your
3485 + * option) any later version.
3486 + *
3487 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3488 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3489 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3490 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3491 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3492 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3493 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3494 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3495 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3496 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3497 + *
3498 + * You should have received a copy of the GNU General Public License along
3499 + * with this program; if not, write to the Free Software Foundation, Inc.,
3500 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3501 + *
3502 + */
3503 +
3504 +
3505 +#include <linux/config.h>
3506 +#include <linux/kernel.h>
3507 +#include <linux/module.h>
3508 +#include <linux/init.h>
3509 +
3510 +#include <asm/irq.h>
3511 +#include <asm/au1000.h>
3512 +#include <asm/au1100_mmc.h>
3513 +#include <asm/pb1100.h>
3514 +
3515 +
3516 +/* SD/MMC controller support functions */
3517 +
3518 +/*
3519 + * Detect card.
3520 + */
3521 +void mmc_card_inserted(int _n_, int *_res_)
3522 +{
3523 + u32 gpios = au_readl(SYS_PINSTATERD);
3524 + u32 emptybit = (_n_) ? (1<<15) : (1<<14);
3525 + *_res_ = ((gpios & emptybit) == 0);
3526 +}
3527 +
3528 +/*
3529 + * Check card write protection.
3530 + */
3531 +void mmc_card_writable(int _n_, int *_res_)
3532 +{
3533 + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
3534 + unsigned long mmc_wp, board_specific;
3535 +
3536 + if (_n_) {
3537 + mmc_wp = BCSR_PCMCIA_SD1_WP;
3538 + } else {
3539 + mmc_wp = BCSR_PCMCIA_SD0_WP;
3540 + }
3541 +
3542 + board_specific = au_readl((unsigned long)(&bcsr->pcmcia));
3543 +
3544 + if (!(board_specific & mmc_wp)) {/* low means card writable */
3545 + *_res_ = 1;
3546 + } else {
3547 + *_res_ = 0;
3548 + }
3549 +}
3550 +
3551 +/*
3552 + * Apply power to card slot.
3553 + */
3554 +void mmc_power_on(int _n_)
3555 +{
3556 + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
3557 + unsigned long mmc_pwr, board_specific;
3558 +
3559 + if (_n_) {
3560 + mmc_pwr = BCSR_PCMCIA_SD1_PWR;
3561 + } else {
3562 + mmc_pwr = BCSR_PCMCIA_SD0_PWR;
3563 + }
3564 +
3565 + board_specific = au_readl((unsigned long)(&bcsr->pcmcia));
3566 + board_specific |= mmc_pwr;
3567 +
3568 + au_writel(board_specific, (int)(&bcsr->pcmcia));
3569 + au_sync_delay(1);
3570 +}
3571 +
3572 +/*
3573 + * Remove power from card slot.
3574 + */
3575 +void mmc_power_off(int _n_)
3576 +{
3577 + BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
3578 + unsigned long mmc_pwr, board_specific;
3579 +
3580 + if (_n_) {
3581 + mmc_pwr = BCSR_PCMCIA_SD1_PWR;
3582 + } else {
3583 + mmc_pwr = BCSR_PCMCIA_SD0_PWR;
3584 + }
3585 +
3586 + board_specific = au_readl((unsigned long)(&bcsr->pcmcia));
3587 + board_specific &= ~mmc_pwr;
3588 +
3589 + au_writel(board_specific, (int)(&bcsr->pcmcia));
3590 + au_sync_delay(1);
3591 +}
3592 +
3593 +EXPORT_SYMBOL(mmc_card_inserted);
3594 +EXPORT_SYMBOL(mmc_card_writable);
3595 +EXPORT_SYMBOL(mmc_power_on);
3596 +EXPORT_SYMBOL(mmc_power_off);
3597 +
3598 diff -Nur linux-2.4.30/arch/mips/au1000/pb1200/Makefile linux-2.4.30-mips/arch/mips/au1000/pb1200/Makefile
3599 --- linux-2.4.30/arch/mips/au1000/pb1200/Makefile 1970-01-01 01:00:00.000000000 +0100
3600 +++ linux-2.4.30-mips/arch/mips/au1000/pb1200/Makefile 2005-01-30 09:01:27.000000000 +0100
3601 @@ -0,0 +1,25 @@
3602 +#
3603 +# Copyright 2000 MontaVista Software Inc.
3604 +# Author: MontaVista Software, Inc.
3605 +# ppopov@mvista.com or source@mvista.com
3606 +#
3607 +# Makefile for the Alchemy Semiconductor PB1000 board.
3608 +#
3609 +# Note! Dependencies are done automagically by 'make dep', which also
3610 +# removes any old dependencies. DON'T put your own dependencies here
3611 +# unless it's something special (ie not a .c file).
3612 +#
3613 +
3614 +USE_STANDARD_AS_RULE := true
3615 +
3616 +O_TARGET := pb1200.o
3617 +
3618 +obj-y := init.o board_setup.o irqmap.o
3619 +
3620 +ifdef CONFIG_MMC
3621 +obj-y += mmc_support.o
3622 +export-objs +=mmc_support.o
3623 +endif
3624 +
3625 +
3626 +include $(TOPDIR)/Rules.make
3627 diff -Nur linux-2.4.30/arch/mips/au1000/pb1200/board_setup.c linux-2.4.30-mips/arch/mips/au1000/pb1200/board_setup.c
3628 --- linux-2.4.30/arch/mips/au1000/pb1200/board_setup.c 1970-01-01 01:00:00.000000000 +0100
3629 +++ linux-2.4.30-mips/arch/mips/au1000/pb1200/board_setup.c 2005-03-19 08:17:51.000000000 +0100
3630 @@ -0,0 +1,221 @@
3631 +/*
3632 + *
3633 + * BRIEF MODULE DESCRIPTION
3634 + * Alchemy Pb1200 board setup.
3635 + *
3636 + * This program is free software; you can redistribute it and/or modify it
3637 + * under the terms of the GNU General Public License as published by the
3638 + * Free Software Foundation; either version 2 of the License, or (at your
3639 + * option) any later version.
3640 + *
3641 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3642 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3643 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3644 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3645 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3646 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3647 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3648 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3649 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3650 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3651 + *
3652 + * You should have received a copy of the GNU General Public License along
3653 + * with this program; if not, write to the Free Software Foundation, Inc.,
3654 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3655 + */
3656 +#include <linux/config.h>
3657 +#include <linux/init.h>
3658 +#include <linux/sched.h>
3659 +#include <linux/ioport.h>
3660 +#include <linux/mm.h>
3661 +#include <linux/console.h>
3662 +#include <linux/mc146818rtc.h>
3663 +#include <linux/delay.h>
3664 +
3665 +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
3666 +#include <linux/ide.h>
3667 +#endif
3668 +
3669 +#include <asm/cpu.h>
3670 +#include <asm/bootinfo.h>
3671 +#include <asm/irq.h>
3672 +#include <asm/keyboard.h>
3673 +#include <asm/mipsregs.h>
3674 +#include <asm/reboot.h>
3675 +#include <asm/pgtable.h>
3676 +#include <asm/au1000.h>
3677 +#include <asm/au1xxx_dbdma.h>
3678 +
3679 +#ifdef CONFIG_MIPS_PB1200
3680 +#include <asm/pb1200.h>
3681 +#endif
3682 +
3683 +#ifdef CONFIG_MIPS_DB1200
3684 +#include <asm/db1200.h>
3685 +#define PB1200_ETH_INT DB1200_ETH_INT
3686 +#define PB1200_IDE_INT DB1200_IDE_INT
3687 +#endif
3688 +
3689 +extern struct rtc_ops no_rtc_ops;
3690 +
3691 +extern void _board_init_irq(void);
3692 +extern void (*board_init_irq)(void);
3693 +
3694 +#ifdef CONFIG_BLK_DEV_IDE_AU1XXX
3695 +extern struct ide_ops *ide_ops;
3696 +extern struct ide_ops au1xxx_ide_ops;
3697 +extern u32 au1xxx_ide_virtbase;
3698 +extern u64 au1xxx_ide_physbase;
3699 +extern int au1xxx_ide_irq;
3700 +
3701 +u32 led_base_addr;
3702 +/* Ddma */
3703 +chan_tab_t *ide_read_ch, *ide_write_ch;
3704 +u32 au1xxx_ide_ddma_enable = 0, switch4ddma = 1; // PIO+ddma
3705 +
3706 +dbdev_tab_t new_dbdev_tab_element = { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 };
3707 +#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX */
3708 +
3709 +void board_reset (void)
3710 +{
3711 + bcsr->resets = 0;
3712 +}
3713 +
3714 +void board_power_off (void)
3715 +{
3716 + bcsr->resets = 0xC000;
3717 +}
3718 +
3719 +void __init board_setup(void)
3720 +{
3721 + char *argptr = NULL;
3722 + u32 pin_func;
3723 + rtc_ops = &no_rtc_ops;
3724 +
3725 +#if 0
3726 + /* Enable PSC1 SYNC for AC97. Normaly done in audio driver,
3727 + * but it is board specific code, so put it here.
3728 + */
3729 + pin_func = au_readl(SYS_PINFUNC);
3730 + au_sync();
3731 + pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
3732 + au_writel(pin_func, SYS_PINFUNC);
3733 +
3734 + au_writel(0, (u32)bcsr|0x10); /* turn off pcmcia power */
3735 + au_sync();
3736 +#endif
3737 +
3738 +#if defined( CONFIG_I2C_ALGO_AU1550 )
3739 + {
3740 + u32 freq0, clksrc;
3741 +
3742 + /* Select SMBUS in CPLD */
3743 + bcsr->resets &= ~(BCSR_RESETS_PCS0MUX);
3744 +
3745 + pin_func = au_readl(SYS_PINFUNC);
3746 + au_sync();
3747 + pin_func &= ~(3<<17 | 1<<4);
3748 + /* Set GPIOs correctly */
3749 + pin_func |= 2<<17;
3750 + au_writel(pin_func, SYS_PINFUNC);
3751 + au_sync();
3752 +
3753 + /* The i2c driver depends on 50Mhz clock */
3754 + freq0 = au_readl(SYS_FREQCTRL0);
3755 + au_sync();
3756 + freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
3757 + freq0 |= (3<<SYS_FC_FRDIV1_BIT);
3758 + /* 396Mhz / (3+1)*2 == 49.5Mhz */
3759 + au_writel(freq0, SYS_FREQCTRL0);
3760 + au_sync();
3761 + freq0 |= SYS_FC_FE1;
3762 + au_writel(freq0, SYS_FREQCTRL0);
3763 + au_sync();
3764 +
3765 + clksrc = au_readl(SYS_CLKSRC);
3766 + au_sync();
3767 + clksrc &= ~0x01f00000;
3768 + /* bit 22 is EXTCLK0 for PSC0 */
3769 + clksrc |= (0x3 << 22);
3770 + au_writel(clksrc, SYS_CLKSRC);
3771 + au_sync();
3772 + }
3773 +#endif
3774 +
3775 +#ifdef CONFIG_FB_AU1200
3776 + argptr = prom_getcmdline();
3777 + strcat(argptr, " video=au1200fb:");
3778 +#endif
3779 +
3780 +#if defined(CONFIG_BLK_DEV_IDE_AU1XXX)
3781 + /*
3782 + * Iniz IDE parameters
3783 + */
3784 + ide_ops = &au1xxx_ide_ops;
3785 + au1xxx_ide_irq = PB1200_IDE_INT;
3786 + au1xxx_ide_physbase = AU1XXX_ATA_PHYS_ADDR;
3787 + au1xxx_ide_virtbase = KSEG1ADDR(AU1XXX_ATA_PHYS_ADDR);
3788 + /*
3789 + * change PIO or PIO+Ddma
3790 + * check the GPIO-5 pin condition. pb1200:s18_dot */
3791 + switch4ddma = (au_readl(SYS_PINSTATERD) & (1 << 5)) ? 1 : 0;
3792 +#endif
3793 +
3794 + /* The Pb1200 development board uses external MUX for PSC0 to
3795 + support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
3796 + */
3797 +#if defined(CONFIG_AU1550_PSC_SPI) && defined(CONFIG_I2C_ALGO_AU1550)
3798 + #error I2C and SPI are mutually exclusive. Both are physically connected to PSC0.\
3799 + Refer to Pb1200/Db1200 documentation.
3800 +#elif defined( CONFIG_AU1550_PSC_SPI )
3801 + bcsr->resets |= BCSR_RESETS_PCS0MUX;
3802 +#elif defined( CONFIG_I2C_ALGO_AU1550 )
3803 + bcsr->resets &= (~BCSR_RESETS_PCS0MUX);
3804 +#endif
3805 + au_sync();
3806 +
3807 +#ifdef CONFIG_MIPS_PB1200
3808 + printk("AMD Alchemy Pb1200 Board\n");
3809 +#endif
3810 +#ifdef CONFIG_MIPS_DB1200
3811 + printk("AMD Alchemy Db1200 Board\n");
3812 +#endif
3813 +
3814 + /* Setup Pb1200 External Interrupt Controller */
3815 + {
3816 + extern void (*board_init_irq)(void);
3817 + extern void _board_init_irq(void);
3818 + board_init_irq = _board_init_irq;
3819 + }
3820 +}
3821 +
3822 +int
3823 +board_au1200fb_panel (void)
3824 +{
3825 + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
3826 + int p;
3827 +
3828 + p = bcsr->switches;
3829 + p >>= 8;
3830 + p &= 0x0F;
3831 + return p;
3832 +}
3833 +
3834 +int
3835 +board_au1200fb_panel_init (void)
3836 +{
3837 + /* Apply power */
3838 + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
3839 + bcsr->board |= (BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL);
3840 + return 0;
3841 +}
3842 +
3843 +int
3844 +board_au1200fb_panel_shutdown (void)
3845 +{
3846 + /* Remove power */
3847 + BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
3848 + bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL);
3849 + return 0;
3850 +}
3851 +
3852 diff -Nur linux-2.4.30/arch/mips/au1000/pb1200/init.c linux-2.4.30-mips/arch/mips/au1000/pb1200/init.c
3853 --- linux-2.4.30/arch/mips/au1000/pb1200/init.c 1970-01-01 01:00:00.000000000 +0100
3854 +++ linux-2.4.30-mips/arch/mips/au1000/pb1200/init.c 2005-01-30 09:01:28.000000000 +0100
3855 @@ -0,0 +1,72 @@
3856 +/*
3857 + *
3858 + * BRIEF MODULE DESCRIPTION
3859 + * PB1200 board setup
3860 + *
3861 + * This program is free software; you can redistribute it and/or modify it
3862 + * under the terms of the GNU General Public License as published by the
3863 + * Free Software Foundation; either version 2 of the License, or (at your
3864 + * option) any later version.
3865 + *
3866 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3867 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3868 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3869 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3870 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3871 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3872 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3873 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3874 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3875 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3876 + *
3877 + * You should have received a copy of the GNU General Public License along
3878 + * with this program; if not, write to the Free Software Foundation, Inc.,
3879 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3880 + */
3881 +
3882 +#include <linux/init.h>
3883 +#include <linux/mm.h>
3884 +#include <linux/sched.h>
3885 +#include <linux/bootmem.h>
3886 +#include <asm/addrspace.h>
3887 +#include <asm/bootinfo.h>
3888 +#include <linux/config.h>
3889 +#include <linux/string.h>
3890 +#include <linux/kernel.h>
3891 +#include <linux/sched.h>
3892 +
3893 +int prom_argc;
3894 +char **prom_argv, **prom_envp;
3895 +extern void __init prom_init_cmdline(void);
3896 +extern char *prom_getenv(char *envname);
3897 +
3898 +const char *get_system_type(void)
3899 +{
3900 + return "AMD Alchemy Au1200/Pb1200";
3901 +}
3902 +
3903 +u32 mae_memsize = 0;
3904 +
3905 +int __init prom_init(int argc, char **argv, char **envp, int *prom_vec)
3906 +{
3907 + unsigned char *memsize_str;
3908 + unsigned long memsize;
3909 +
3910 + prom_argc = argc;
3911 + prom_argv = argv;
3912 + prom_envp = envp;
3913 +
3914 + mips_machgroup = MACH_GROUP_ALCHEMY;
3915 + mips_machtype = MACH_PB1000; /* set the platform # */
3916 + prom_init_cmdline();
3917 +
3918 + memsize_str = prom_getenv("memsize");
3919 + if (!memsize_str) {
3920 + memsize = 0x08000000;
3921 + } else {
3922 + memsize = simple_strtol(memsize_str, NULL, 0);
3923 + }
3924 + add_memory_region(0, memsize, BOOT_MEM_RAM);
3925 + return 0;
3926 +}
3927 +
3928 diff -Nur linux-2.4.30/arch/mips/au1000/pb1200/irqmap.c linux-2.4.30-mips/arch/mips/au1000/pb1200/irqmap.c
3929 --- linux-2.4.30/arch/mips/au1000/pb1200/irqmap.c 1970-01-01 01:00:00.000000000 +0100
3930 +++ linux-2.4.30-mips/arch/mips/au1000/pb1200/irqmap.c 2005-01-30 09:01:28.000000000 +0100
3931 @@ -0,0 +1,180 @@
3932 +/*
3933 + * BRIEF MODULE DESCRIPTION
3934 + * Au1xxx irq map table
3935 + *
3936 + * This program is free software; you can redistribute it and/or modify it
3937 + * under the terms of the GNU General Public License as published by the
3938 + * Free Software Foundation; either version 2 of the License, or (at your
3939 + * option) any later version.
3940 + *
3941 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
3942 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
3943 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
3944 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
3945 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
3946 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
3947 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
3948 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
3949 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
3950 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
3951 + *
3952 + * You should have received a copy of the GNU General Public License along
3953 + * with this program; if not, write to the Free Software Foundation, Inc.,
3954 + * 675 Mass Ave, Cambridge, MA 02139, USA.
3955 + */
3956 +#include <linux/errno.h>
3957 +#include <linux/init.h>
3958 +#include <linux/irq.h>
3959 +#include <linux/kernel_stat.h>
3960 +#include <linux/module.h>
3961 +#include <linux/signal.h>
3962 +#include <linux/sched.h>
3963 +#include <linux/types.h>
3964 +#include <linux/interrupt.h>
3965 +#include <linux/ioport.h>
3966 +#include <linux/timex.h>
3967 +#include <linux/slab.h>
3968 +#include <linux/random.h>
3969 +#include <linux/delay.h>
3970 +
3971 +#include <asm/bitops.h>
3972 +#include <asm/bootinfo.h>
3973 +#include <asm/io.h>
3974 +#include <asm/mipsregs.h>
3975 +#include <asm/system.h>
3976 +#include <asm/au1000.h>
3977 +
3978 +#ifdef CONFIG_MIPS_PB1200
3979 +#include <asm/pb1200.h>
3980 +#endif
3981 +
3982 +#ifdef CONFIG_MIPS_DB1200
3983 +#include <asm/db1200.h>
3984 +#define PB1200_INT_BEGIN DB1200_INT_BEGIN
3985 +#define PB1200_INT_END DB1200_INT_END
3986 +#endif
3987 +
3988 +au1xxx_irq_map_t au1xxx_irq_map[] = {
3989 + { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, // This is exteranl interrupt cascade
3990 +};
3991 +
3992 +int au1xxx_nr_irqs = sizeof(au1xxx_irq_map)/sizeof(au1xxx_irq_map_t);
3993 +
3994 +/*
3995 + * Support for External interrupts on the PbAu1200 Development platform.
3996 + */
3997 +static volatile int pb1200_cascade_en=0;
3998 +
3999 +void pb1200_cascade_handler( int irq, void *dev_id, struct pt_regs *regs)
4000 +{
4001 + unsigned short bisr = bcsr->int_status;
4002 + int extirq_nr = 0;
4003 +
4004 + /* Clear all the edge interrupts. This has no effect on level */
4005 + bcsr->int_status = bisr;
4006 + for( ; bisr; bisr &= (bisr-1) )
4007 + {