ar71xx: improve SPI flash read/write performance
[openwrt/staging/mkresin.git] / target / linux / ar71xx / patches-3.3 / 207-spi-ath79-make-chipselect-logic-more-flexible.patch
1 From bdbd9b2861ba73557795915598bb276a8568d130 Mon Sep 17 00:00:00 2001
2 From: Gabor Juhos <juhosg@openwrt.org>
3 Date: Wed, 11 Jan 2012 22:25:11 +0100
4 Subject: [PATCH 7/7] spi/ath79: make chipselect logic more flexible
5
6 Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
7 ---
8 arch/mips/ath79/mach-ap121.c | 6 ++
9 arch/mips/ath79/mach-ap81.c | 6 ++
10 arch/mips/ath79/mach-pb44.c | 6 ++
11 arch/mips/ath79/mach-ubnt-xm.c | 6 ++
12 .../include/asm/mach-ath79/ath79_spi_platform.h | 8 ++-
13 drivers/spi/spi-ath79.c | 63 ++++++++++++--------
14 6 files changed, 69 insertions(+), 26 deletions(-)
15
16 --- a/arch/mips/ath79/mach-ap121.c
17 +++ b/arch/mips/ath79/mach-ap121.c
18 @@ -58,12 +58,18 @@ static struct gpio_keys_button ap121_gpi
19 }
20 };
21
22 +static struct ath79_spi_controller_data ap121_spi0_data = {
23 + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
24 + .cs_line = 0,
25 +};
26 +
27 static struct spi_board_info ap121_spi_info[] = {
28 {
29 .bus_num = 0,
30 .chip_select = 0,
31 .max_speed_hz = 25000000,
32 .modalias = "mx25l1606e",
33 + .controller_data = &ap121_spi0_data,
34 }
35 };
36
37 --- a/arch/mips/ath79/mach-ap81.c
38 +++ b/arch/mips/ath79/mach-ap81.c
39 @@ -67,12 +67,18 @@ static struct gpio_keys_button ap81_gpio
40 }
41 };
42
43 +static struct ath79_spi_controller_data ap81_spi0_data = {
44 + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
45 + .cs_line = 0,
46 +};
47 +
48 static struct spi_board_info ap81_spi_info[] = {
49 {
50 .bus_num = 0,
51 .chip_select = 0,
52 .max_speed_hz = 25000000,
53 .modalias = "m25p64",
54 + .controller_data = &ap81_spi0_data,
55 }
56 };
57
58 --- a/arch/mips/ath79/mach-pb44.c
59 +++ b/arch/mips/ath79/mach-pb44.c
60 @@ -87,12 +87,18 @@ static struct gpio_keys_button pb44_gpio
61 }
62 };
63
64 +static struct ath79_spi_controller_data pb44_spi0_data = {
65 + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
66 + .cs_line = 0,
67 +};
68 +
69 static struct spi_board_info pb44_spi_info[] = {
70 {
71 .bus_num = 0,
72 .chip_select = 0,
73 .max_speed_hz = 25000000,
74 .modalias = "m25p64",
75 + .controller_data = &pb44_spi0_data,
76 },
77 };
78
79 --- a/arch/mips/ath79/mach-ubnt-xm.c
80 +++ b/arch/mips/ath79/mach-ubnt-xm.c
81 @@ -65,12 +65,18 @@ static struct gpio_keys_button ubnt_xm_g
82 }
83 };
84
85 +static struct ath79_spi_controller_data ubnt_xm_spi0_data = {
86 + .cs_type = ATH79_SPI_CS_TYPE_INTERNAL,
87 + .cs_line = 0,
88 +};
89 +
90 static struct spi_board_info ubnt_xm_spi_info[] = {
91 {
92 .bus_num = 0,
93 .chip_select = 0,
94 .max_speed_hz = 25000000,
95 .modalias = "mx25l6405d",
96 + .controller_data = &ubnt_xm_spi0_data,
97 }
98 };
99
100 --- a/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
101 +++ b/arch/mips/include/asm/mach-ath79/ath79_spi_platform.h
102 @@ -16,8 +16,14 @@ struct ath79_spi_platform_data {
103 unsigned num_chipselect;
104 };
105
106 +enum ath79_spi_cs_type {
107 + ATH79_SPI_CS_TYPE_INTERNAL,
108 + ATH79_SPI_CS_TYPE_GPIO,
109 +};
110 +
111 struct ath79_spi_controller_data {
112 - unsigned gpio;
113 + enum ath79_spi_cs_type cs_type;
114 + unsigned cs_line;
115 };
116
117 #endif /* _ATH79_SPI_PLATFORM_H */
118 --- a/drivers/spi/spi-ath79.c
119 +++ b/drivers/spi/spi-ath79.c
120 @@ -35,6 +35,8 @@
121 #define ATH79_SPI_RRW_DELAY_FACTOR 12000
122 #define MHZ (1000 * 1000)
123
124 +#define ATH79_SPI_CS_LINE_MAX 2
125 +
126 struct ath79_spi {
127 struct spi_bitbang bitbang;
128 u32 ioc_base;
129 @@ -69,6 +71,7 @@ static void ath79_spi_chipselect(struct
130 {
131 struct ath79_spi *sp = ath79_spidev_to_sp(spi);
132 int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
133 + struct ath79_spi_controller_data *cdata = spi->controller_data;
134
135 if (is_active) {
136 /* set initial clock polarity */
137 @@ -80,20 +83,21 @@ static void ath79_spi_chipselect(struct
138 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
139 }
140
141 - if (spi->chip_select) {
142 - struct ath79_spi_controller_data *cdata = spi->controller_data;
143 -
144 - /* SPI is normally active-low */
145 - gpio_set_value(cdata->gpio, cs_high);
146 - } else {
147 + switch (cdata->cs_type) {
148 + case ATH79_SPI_CS_TYPE_INTERNAL:
149 if (cs_high)
150 - sp->ioc_base |= AR71XX_SPI_IOC_CS0;
151 + sp->ioc_base |= AR71XX_SPI_IOC_CS(cdata->cs_line);
152 else
153 - sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
154 + sp->ioc_base &= ~AR71XX_SPI_IOC_CS(cdata->cs_line);
155
156 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
157 - }
158 + break;
159
160 + case ATH79_SPI_CS_TYPE_GPIO:
161 + /* SPI is normally active-low */
162 + gpio_set_value(cdata->cs_line, cs_high);
163 + break;
164 + }
165 }
166
167 static void ath79_spi_enable(struct ath79_spi *sp)
168 @@ -120,24 +124,30 @@ static void ath79_spi_disable(struct ath
169 static int ath79_spi_setup_cs(struct spi_device *spi)
170 {
171 struct ath79_spi_controller_data *cdata;
172 + unsigned long flags;
173 int status;
174
175 cdata = spi->controller_data;
176 - if (spi->chip_select && !cdata)
177 + if (!cdata)
178 return -EINVAL;
179
180 status = 0;
181 - if (spi->chip_select) {
182 - unsigned long flags;
183 + switch (cdata->cs_type) {
184 + case ATH79_SPI_CS_TYPE_INTERNAL:
185 + if (cdata->cs_line > ATH79_SPI_CS_LINE_MAX)
186 + status = -EINVAL;
187 + break;
188
189 + case ATH79_SPI_CS_TYPE_GPIO:
190 flags = GPIOF_DIR_OUT;
191 if (spi->mode & SPI_CS_HIGH)
192 flags |= GPIOF_INIT_HIGH;
193 else
194 flags |= GPIOF_INIT_LOW;
195
196 - status = gpio_request_one(cdata->gpio, flags,
197 + status = gpio_request_one(cdata->cs_line, flags,
198 dev_name(&spi->dev));
199 + break;
200 }
201
202 return status;
203 @@ -145,9 +155,15 @@ static int ath79_spi_setup_cs(struct spi
204
205 static void ath79_spi_cleanup_cs(struct spi_device *spi)
206 {
207 - if (spi->chip_select) {
208 - struct ath79_spi_controller_data *cdata = spi->controller_data;
209 - gpio_free(cdata->gpio);
210 + struct ath79_spi_controller_data *cdata = spi->controller_data;
211 +
212 + switch (cdata->cs_type) {
213 + case ATH79_SPI_CS_TYPE_INTERNAL:
214 + /* nothing to do */
215 + break;
216 + case ATH79_SPI_CS_TYPE_GPIO:
217 + gpio_free(cdata->cs_line);
218 + break;
219 }
220 }
221
222 @@ -215,6 +231,10 @@ static __devinit int ath79_spi_probe(str
223 unsigned long rate;
224 int ret;
225
226 + pdata = pdev->dev.platform_data;
227 + if (!pdata)
228 + return -EINVAL;
229 +
230 master = spi_alloc_master(&pdev->dev, sizeof(*sp));
231 if (master == NULL) {
232 dev_err(&pdev->dev, "failed to allocate spi master\n");
233 @@ -224,17 +244,10 @@ static __devinit int ath79_spi_probe(str
234 sp = spi_master_get_devdata(master);
235 platform_set_drvdata(pdev, sp);
236
237 - pdata = pdev->dev.platform_data;
238 -
239 master->setup = ath79_spi_setup;
240 master->cleanup = ath79_spi_cleanup;
241 - if (pdata) {
242 - master->bus_num = pdata->bus_num;
243 - master->num_chipselect = pdata->num_chipselect;
244 - } else {
245 - master->bus_num = -1;
246 - master->num_chipselect = 1;
247 - }
248 + master->bus_num = pdata->bus_num;
249 + master->num_chipselect = pdata->num_chipselect;
250
251 sp->bitbang.master = spi_master_get(master);
252 sp->bitbang.chipselect = ath79_spi_chipselect;