target/linux/brcm63xx/patches-3.14/327-MIPS-BCM63XX-allow-setting-affinity-for-IPIC.patch

   1 From 23493b47d8caaa59b18627a01bf443c3b50bb530 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Fri, 26 Apr 2013 12:06:03 +0200
   4 Subject: [PATCH 10/10] MIPS: BCM63XX: allow setting affinity for IPIC
   5
   6 Wire up the set_affinity call for the internal PIC if booting on
   7 a cpu supporting it.
   8 Affinity is kept to boot cpu as default.
   9
  10 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  11 ---
  12  arch/mips/bcm63xx/irq.c | 46 ++++++++++++++++++++++++++++++++++++++++------
  13  1 file changed, 40 insertions(+), 6 deletions(-)
  14
  15 --- a/arch/mips/bcm63xx/irq.c
  16 +++ b/arch/mips/bcm63xx/irq.c
  17 @@ -32,7 +32,7 @@ static unsigned int ext_irq_count;
  18  static unsigned int ext_irq_start, ext_irq_end;
  19  static unsigned int ext_irq_cfg_reg1, ext_irq_cfg_reg2;
  20  static void (*internal_irq_mask)(struct irq_data *d);
  21 -static void (*internal_irq_unmask)(struct irq_data *d);
  22 +static void (*internal_irq_unmask)(struct irq_data *d, const struct cpumask *m);
  23
  24
  25  static inline u32 get_ext_irq_perf_reg(int irq)
  26 @@ -51,6 +51,20 @@ static inline void handle_internal(int i
  27                 do_IRQ(intbit + IRQ_INTERNAL_BASE);
  28  }
  29
  30 +static inline int enable_irq_for_cpu(int cpu, struct irq_data *d,
  31 +                                    const struct cpumask *m)
  32 +{
  33 +       bool enable = cpu_online(cpu);
  34 +
  35 +#ifdef CONFIG_SMP
  36 +       if (m)
  37 +               enable &= cpu_isset(cpu, *m);
  38 +       else if (irqd_affinity_was_set(d))
  39 +               enable &= cpu_isset(cpu, *d->affinity);
  40 +#endif
  41 +       return enable;
  42 +}
  43 +
  44  /*
  45   * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not
  46   * prioritize any interrupt relatively to another. the static counter
  47 @@ -117,7 +131,8 @@ static void __internal_irq_mask_##width(
  48         spin_unlock_irqrestore(&ipic_lock, flags);                      \
  49  }                                                                      \
  50                                                                         \
  51 -static void __internal_irq_unmask_##width(struct irq_data *d)          \
  52 +static void __internal_irq_unmask_##width(struct irq_data *d,          \
  53 +                                         const struct cpumask *m)      \
  54  {                                                                      \
  55         u32 val;                                                        \
  56         unsigned irq = d->irq - IRQ_INTERNAL_BASE;                      \
  57 @@ -132,7 +147,7 @@ static void __internal_irq_unmask_##widt
  58                         break;                                          \
  59                                                                         \
  60                 val = bcm_readl(irq_mask_addr[cpu] + reg * sizeof(u32));\
  61 -               if (cpu_online(cpu))                                    \
  62 +               if (enable_irq_for_cpu(cpu, d, m))                      \
  63                         val |= (1 << bit);                              \
  64                 else                                                    \
  65                         val &= ~(1 << bit);                             \
  66 @@ -189,7 +204,7 @@ static void bcm63xx_internal_irq_mask(st
  67
  68  static void bcm63xx_internal_irq_unmask(struct irq_data *d)
  69  {
  70 -       internal_irq_unmask(d);
  71 +       internal_irq_unmask(d, NULL);
  72  }
  73
  74  /*
  75 @@ -237,7 +252,8 @@ static void bcm63xx_external_irq_unmask(
  76         spin_unlock_irqrestore(&epic_lock, flags);
  77
  78         if (is_ext_irq_cascaded)
  79 -               internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start));
  80 +               internal_irq_unmask(irq_get_irq_data(irq + ext_irq_start),
  81 +                                   NULL);
  82  }
  83
  84  static void bcm63xx_external_irq_clear(struct irq_data *d)
  85 @@ -356,6 +372,18 @@ static int bcm63xx_external_irq_set_type
  86         return IRQ_SET_MASK_OK_NOCOPY;
  87  }
  88
  89 +#ifdef CONFIG_SMP
  90 +static int bcm63xx_internal_set_affinity(struct irq_data *data,
  91 +                                        const struct cpumask *dest,
  92 +                                        bool force)
  93 +{
  94 +       if (!irqd_irq_disabled(data))
  95 +               internal_irq_unmask(data, dest);
  96 +
  97 +       return 0;
  98 +}
  99 +#endif
 100 +
 101  static struct irq_chip bcm63xx_internal_irq_chip = {
 102         .name           = "bcm63xx_ipic",
 103         .irq_mask       = bcm63xx_internal_irq_mask,
 104 @@ -523,7 +551,13 @@ void __init arch_init_irq(void)
 105
 106         setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
 107  #ifdef CONFIG_SMP
 108 -       if (is_ext_irq_cascaded)
 109 +       if (is_ext_irq_cascaded) {
 110                 setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
 111 +               bcm63xx_internal_irq_chip.irq_set_affinity =
 112 +                       bcm63xx_internal_set_affinity;
 113 +
 114 +               cpumask_clear(irq_default_affinity);
 115 +               cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
 116 +       }
 117  #endif
 118  }