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mvsw61xx: reset phys on probe to enable switch ports on clearfog pro
[openwrt/staging/mkresin.git] / target / linux / generic / files / drivers / net / phy / mvsw61xx.c
1 /*
2 * Marvell 88E61xx switch driver
3 *
4 * Copyright (c) 2014 Claudio Leite <leitec@staticky.com>
5 * Copyright (c) 2014 Nikita Nazarenko <nnazarenko@radiofid.com>
6 *
7 * Based on code (c) 2008 Felix Fietkau <nbd@nbd.name>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License v2 as published by the
11 * Free Software Foundation
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/list.h>
18 #include <linux/mii.h>
19 #include <linux/phy.h>
20 #include <linux/of.h>
21 #include <linux/of_mdio.h>
22 #include <linux/delay.h>
23 #include <linux/switch.h>
24 #include <linux/device.h>
25 #include <linux/platform_device.h>
26
27 #include "mvsw61xx.h"
28
29 MODULE_DESCRIPTION("Marvell 88E61xx Switch driver");
30 MODULE_AUTHOR("Claudio Leite <leitec@staticky.com>");
31 MODULE_AUTHOR("Nikita Nazarenko <nnazarenko@radiofid.com>");
32 MODULE_LICENSE("GPL v2");
33 MODULE_ALIAS("platform:mvsw61xx");
34
35 /*
36 * Register access is done through direct or indirect addressing,
37 * depending on how the switch is physically connected.
38 *
39 * Direct addressing: all port and global registers directly
40 * accessible via an address/register pair
41 *
42 * Indirect addressing: switch is mapped at a single address,
43 * port and global registers accessible via a single command/data
44 * register pair
45 */
46
47 static int
48 mvsw61xx_wait_mask_raw(struct mii_bus *bus, int addr,
49 int reg, u16 mask, u16 val)
50 {
51 int i = 100;
52 u16 r;
53
54 do {
55 r = bus->read(bus, addr, reg);
56 if ((r & mask) == val)
57 return 0;
58 } while (--i > 0);
59
60 return -ETIMEDOUT;
61 }
62
63 static u16
64 r16(struct mii_bus *bus, bool indirect, int base_addr, int addr, int reg)
65 {
66 u16 ind_addr;
67
68 if (!indirect)
69 return bus->read(bus, addr, reg);
70
71 /* Indirect read: First, make sure switch is free */
72 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
73 MV_INDIRECT_INPROGRESS, 0);
74
75 /* Load address and request read */
76 ind_addr = MV_INDIRECT_READ | (addr << MV_INDIRECT_ADDR_S) | reg;
77 bus->write(bus, base_addr, MV_INDIRECT_REG_CMD,
78 ind_addr);
79
80 /* Wait until it's ready */
81 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
82 MV_INDIRECT_INPROGRESS, 0);
83
84 /* Read the requested data */
85 return bus->read(bus, base_addr, MV_INDIRECT_REG_DATA);
86 }
87
88 static void
89 w16(struct mii_bus *bus, bool indirect, int base_addr, int addr,
90 int reg, u16 val)
91 {
92 u16 ind_addr;
93
94 if (!indirect) {
95 bus->write(bus, addr, reg, val);
96 return;
97 }
98
99 /* Indirect write: First, make sure switch is free */
100 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
101 MV_INDIRECT_INPROGRESS, 0);
102
103 /* Load the data to be written */
104 bus->write(bus, base_addr, MV_INDIRECT_REG_DATA, val);
105
106 /* Wait again for switch to be free */
107 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
108 MV_INDIRECT_INPROGRESS, 0);
109
110 /* Load address, and issue write command */
111 ind_addr = MV_INDIRECT_WRITE | (addr << MV_INDIRECT_ADDR_S) | reg;
112 bus->write(bus, base_addr, MV_INDIRECT_REG_CMD,
113 ind_addr);
114 }
115
116 /* swconfig support */
117
118 static inline u16
119 sr16(struct switch_dev *dev, int addr, int reg)
120 {
121 struct mvsw61xx_state *state = get_state(dev);
122
123 return r16(state->bus, state->is_indirect, state->base_addr, addr, reg);
124 }
125
126 static inline void
127 sw16(struct switch_dev *dev, int addr, int reg, u16 val)
128 {
129 struct mvsw61xx_state *state = get_state(dev);
130
131 w16(state->bus, state->is_indirect, state->base_addr, addr, reg, val);
132 }
133
134 static int
135 mvsw61xx_wait_mask_s(struct switch_dev *dev, int addr,
136 int reg, u16 mask, u16 val)
137 {
138 int i = 100;
139 u16 r;
140
141 do {
142 r = sr16(dev, addr, reg) & mask;
143 if (r == val)
144 return 0;
145 } while (--i > 0);
146
147 return -ETIMEDOUT;
148 }
149
150 static int
151 mvsw61xx_mdio_read(struct switch_dev *dev, int addr, int reg)
152 {
153 sw16(dev, MV_GLOBAL2REG(SMI_OP),
154 MV_INDIRECT_READ | (addr << MV_INDIRECT_ADDR_S) | reg);
155
156 if (mvsw61xx_wait_mask_s(dev, MV_GLOBAL2REG(SMI_OP),
157 MV_INDIRECT_INPROGRESS, 0) < 0)
158 return -ETIMEDOUT;
159
160 return sr16(dev, MV_GLOBAL2REG(SMI_DATA));
161 }
162
163 static int
164 mvsw61xx_mdio_write(struct switch_dev *dev, int addr, int reg, u16 val)
165 {
166 sw16(dev, MV_GLOBAL2REG(SMI_DATA), val);
167
168 sw16(dev, MV_GLOBAL2REG(SMI_OP),
169 MV_INDIRECT_WRITE | (addr << MV_INDIRECT_ADDR_S) | reg);
170
171 return mvsw61xx_wait_mask_s(dev, MV_GLOBAL2REG(SMI_OP),
172 MV_INDIRECT_INPROGRESS, 0) < 0;
173 }
174
175 static int
176 mvsw61xx_get_port_mask(struct switch_dev *dev,
177 const struct switch_attr *attr, struct switch_val *val)
178 {
179 struct mvsw61xx_state *state = get_state(dev);
180 char *buf = state->buf;
181 int port, len, i;
182 u16 reg;
183
184 port = val->port_vlan;
185 reg = sr16(dev, MV_PORTREG(VLANMAP, port)) & MV_PORTS_MASK;
186
187 len = sprintf(buf, "0x%04x: ", reg);
188
189 for (i = 0; i < MV_PORTS; i++) {
190 if (reg & (1 << i))
191 len += sprintf(buf + len, "%d ", i);
192 else if (i == port)
193 len += sprintf(buf + len, "(%d) ", i);
194 }
195
196 val->value.s = buf;
197
198 return 0;
199 }
200
201 static int
202 mvsw61xx_get_port_qmode(struct switch_dev *dev,
203 const struct switch_attr *attr, struct switch_val *val)
204 {
205 struct mvsw61xx_state *state = get_state(dev);
206
207 val->value.i = state->ports[val->port_vlan].qmode;
208
209 return 0;
210 }
211
212 static int
213 mvsw61xx_set_port_qmode(struct switch_dev *dev,
214 const struct switch_attr *attr, struct switch_val *val)
215 {
216 struct mvsw61xx_state *state = get_state(dev);
217
218 state->ports[val->port_vlan].qmode = val->value.i;
219
220 return 0;
221 }
222
223 static int
224 mvsw61xx_get_port_pvid(struct switch_dev *dev, int port, int *val)
225 {
226 struct mvsw61xx_state *state = get_state(dev);
227
228 *val = state->ports[port].pvid;
229
230 return 0;
231 }
232
233 static int
234 mvsw61xx_set_port_pvid(struct switch_dev *dev, int port, int val)
235 {
236 struct mvsw61xx_state *state = get_state(dev);
237
238 if (val < 0 || val >= MV_VLANS)
239 return -EINVAL;
240
241 state->ports[port].pvid = (u16)val;
242
243 return 0;
244 }
245
246 static int
247 mvsw61xx_get_port_link(struct switch_dev *dev, int port,
248 struct switch_port_link *link)
249 {
250 u16 status, speed;
251
252 status = sr16(dev, MV_PORTREG(STATUS, port));
253
254 link->link = status & MV_PORT_STATUS_LINK;
255 if (!link->link)
256 return 0;
257
258 link->duplex = status & MV_PORT_STATUS_FDX;
259
260 speed = (status & MV_PORT_STATUS_SPEED_MASK) >>
261 MV_PORT_STATUS_SPEED_SHIFT;
262
263 switch (speed) {
264 case MV_PORT_STATUS_SPEED_10:
265 link->speed = SWITCH_PORT_SPEED_10;
266 break;
267 case MV_PORT_STATUS_SPEED_100:
268 link->speed = SWITCH_PORT_SPEED_100;
269 break;
270 case MV_PORT_STATUS_SPEED_1000:
271 link->speed = SWITCH_PORT_SPEED_1000;
272 break;
273 }
274
275 return 0;
276 }
277
278 static int mvsw61xx_get_vlan_ports(struct switch_dev *dev,
279 struct switch_val *val)
280 {
281 struct mvsw61xx_state *state = get_state(dev);
282 int i, j, mode, vno;
283
284 vno = val->port_vlan;
285
286 if (vno <= 0 || vno >= dev->vlans)
287 return -EINVAL;
288
289 for (i = 0, j = 0; i < dev->ports; i++) {
290 if (state->vlans[vno].mask & (1 << i)) {
291 val->value.ports[j].id = i;
292
293 mode = (state->vlans[vno].port_mode >> (i * 4)) & 0xf;
294 if (mode == MV_VTUCTL_EGRESS_TAGGED)
295 val->value.ports[j].flags =
296 (1 << SWITCH_PORT_FLAG_TAGGED);
297 else
298 val->value.ports[j].flags = 0;
299
300 j++;
301 }
302 }
303
304 val->len = j;
305
306 return 0;
307 }
308
309 static int mvsw61xx_set_vlan_ports(struct switch_dev *dev,
310 struct switch_val *val)
311 {
312 struct mvsw61xx_state *state = get_state(dev);
313 int i, mode, pno, vno;
314
315 vno = val->port_vlan;
316
317 if (vno <= 0 || vno >= dev->vlans)
318 return -EINVAL;
319
320 state->vlans[vno].mask = 0;
321 state->vlans[vno].port_mode = 0;
322 state->vlans[vno].port_sstate = 0;
323
324 if(state->vlans[vno].vid == 0)
325 state->vlans[vno].vid = vno;
326
327 for (i = 0; i < val->len; i++) {
328 pno = val->value.ports[i].id;
329
330 state->vlans[vno].mask |= (1 << pno);
331 if (val->value.ports[i].flags &
332 (1 << SWITCH_PORT_FLAG_TAGGED))
333 mode = MV_VTUCTL_EGRESS_TAGGED;
334 else
335 mode = MV_VTUCTL_EGRESS_UNTAGGED;
336
337 state->vlans[vno].port_mode |= mode << (pno * 4);
338 state->vlans[vno].port_sstate |=
339 MV_STUCTL_STATE_FORWARDING << (pno * 4 + 2);
340 }
341
342 /*
343 * DISCARD is nonzero, so it must be explicitly
344 * set on ports not in the VLAN.
345 */
346 for (i = 0; i < dev->ports; i++)
347 if (!(state->vlans[vno].mask & (1 << i)))
348 state->vlans[vno].port_mode |=
349 MV_VTUCTL_DISCARD << (i * 4);
350
351 return 0;
352 }
353
354 static int mvsw61xx_get_vlan_port_based(struct switch_dev *dev,
355 const struct switch_attr *attr, struct switch_val *val)
356 {
357 struct mvsw61xx_state *state = get_state(dev);
358 int vno = val->port_vlan;
359
360 if (vno <= 0 || vno >= dev->vlans)
361 return -EINVAL;
362
363 if (state->vlans[vno].port_based)
364 val->value.i = 1;
365 else
366 val->value.i = 0;
367
368 return 0;
369 }
370
371 static int mvsw61xx_set_vlan_port_based(struct switch_dev *dev,
372 const struct switch_attr *attr, struct switch_val *val)
373 {
374 struct mvsw61xx_state *state = get_state(dev);
375 int vno = val->port_vlan;
376
377 if (vno <= 0 || vno >= dev->vlans)
378 return -EINVAL;
379
380 if (val->value.i == 1)
381 state->vlans[vno].port_based = true;
382 else
383 state->vlans[vno].port_based = false;
384
385 return 0;
386 }
387
388 static int mvsw61xx_get_vid(struct switch_dev *dev,
389 const struct switch_attr *attr, struct switch_val *val)
390 {
391 struct mvsw61xx_state *state = get_state(dev);
392 int vno = val->port_vlan;
393
394 if (vno <= 0 || vno >= dev->vlans)
395 return -EINVAL;
396
397 val->value.i = state->vlans[vno].vid;
398
399 return 0;
400 }
401
402 static int mvsw61xx_set_vid(struct switch_dev *dev,
403 const struct switch_attr *attr, struct switch_val *val)
404 {
405 struct mvsw61xx_state *state = get_state(dev);
406 int vno = val->port_vlan;
407
408 if (vno <= 0 || vno >= dev->vlans)
409 return -EINVAL;
410
411 state->vlans[vno].vid = val->value.i;
412
413 return 0;
414 }
415
416 static int mvsw61xx_get_enable_vlan(struct switch_dev *dev,
417 const struct switch_attr *attr, struct switch_val *val)
418 {
419 struct mvsw61xx_state *state = get_state(dev);
420
421 val->value.i = state->vlan_enabled;
422
423 return 0;
424 }
425
426 static int mvsw61xx_set_enable_vlan(struct switch_dev *dev,
427 const struct switch_attr *attr, struct switch_val *val)
428 {
429 struct mvsw61xx_state *state = get_state(dev);
430
431 state->vlan_enabled = val->value.i;
432
433 return 0;
434 }
435
436 static int mvsw61xx_vtu_program(struct switch_dev *dev)
437 {
438 struct mvsw61xx_state *state = get_state(dev);
439 u16 v1, v2, s1, s2;
440 int i;
441
442 /* Flush */
443 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
444 MV_VTUOP_INPROGRESS, 0);
445 sw16(dev, MV_GLOBALREG(VTU_OP),
446 MV_VTUOP_INPROGRESS | MV_VTUOP_PURGE);
447
448 /* Write VLAN table */
449 for (i = 1; i < dev->vlans; i++) {
450 if (state->vlans[i].mask == 0 ||
451 state->vlans[i].vid == 0 ||
452 state->vlans[i].port_based == true)
453 continue;
454
455 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
456 MV_VTUOP_INPROGRESS, 0);
457
458 /* Write per-VLAN port state into STU */
459 s1 = (u16) (state->vlans[i].port_sstate & 0xffff);
460 s2 = (u16) ((state->vlans[i].port_sstate >> 16) & 0xffff);
461
462 sw16(dev, MV_GLOBALREG(VTU_VID), MV_VTU_VID_VALID);
463 sw16(dev, MV_GLOBALREG(VTU_SID), i);
464 sw16(dev, MV_GLOBALREG(VTU_DATA1), s1);
465 sw16(dev, MV_GLOBALREG(VTU_DATA2), s2);
466 sw16(dev, MV_GLOBALREG(VTU_DATA3), 0);
467
468 sw16(dev, MV_GLOBALREG(VTU_OP),
469 MV_VTUOP_INPROGRESS | MV_VTUOP_STULOAD);
470 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
471 MV_VTUOP_INPROGRESS, 0);
472
473 /* Write VLAN information into VTU */
474 v1 = (u16) (state->vlans[i].port_mode & 0xffff);
475 v2 = (u16) ((state->vlans[i].port_mode >> 16) & 0xffff);
476
477 sw16(dev, MV_GLOBALREG(VTU_VID),
478 MV_VTU_VID_VALID | state->vlans[i].vid);
479 sw16(dev, MV_GLOBALREG(VTU_SID), i);
480 sw16(dev, MV_GLOBALREG(VTU_FID), i);
481 sw16(dev, MV_GLOBALREG(VTU_DATA1), v1);
482 sw16(dev, MV_GLOBALREG(VTU_DATA2), v2);
483 sw16(dev, MV_GLOBALREG(VTU_DATA3), 0);
484
485 sw16(dev, MV_GLOBALREG(VTU_OP),
486 MV_VTUOP_INPROGRESS | MV_VTUOP_LOAD);
487 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
488 MV_VTUOP_INPROGRESS, 0);
489 }
490
491 return 0;
492 }
493
494 static void mvsw61xx_vlan_port_config(struct switch_dev *dev, int vno)
495 {
496 struct mvsw61xx_state *state = get_state(dev);
497 int i, mode;
498
499 for (i = 0; i < dev->ports; i++) {
500 if (!(state->vlans[vno].mask & (1 << i)))
501 continue;
502
503 mode = (state->vlans[vno].port_mode >> (i * 4)) & 0xf;
504
505 if(mode != MV_VTUCTL_EGRESS_TAGGED)
506 state->ports[i].pvid = state->vlans[vno].vid;
507
508 if (state->vlans[vno].port_based) {
509 state->ports[i].mask |= state->vlans[vno].mask;
510 state->ports[i].fdb = vno;
511 }
512 else
513 state->ports[i].qmode = MV_8021Q_MODE_SECURE;
514 }
515 }
516
517 static int mvsw61xx_update_state(struct switch_dev *dev)
518 {
519 struct mvsw61xx_state *state = get_state(dev);
520 int i;
521 u16 reg;
522
523 if (!state->registered)
524 return -EINVAL;
525
526 /*
527 * Set 802.1q-only mode if vlan_enabled is true.
528 *
529 * Without this, even if 802.1q is enabled for
530 * a port/VLAN, it still depends on the port-based
531 * VLAN mask being set.
532 *
533 * With this setting, port-based VLANs are still
534 * functional, provided the VID is not in the VTU.
535 */
536 reg = sr16(dev, MV_GLOBAL2REG(SDET_POLARITY));
537
538 if (state->vlan_enabled)
539 reg |= MV_8021Q_VLAN_ONLY;
540 else
541 reg &= ~MV_8021Q_VLAN_ONLY;
542
543 sw16(dev, MV_GLOBAL2REG(SDET_POLARITY), reg);
544
545 /*
546 * Set port-based VLAN masks on each port
547 * based only on VLAN definitions known to
548 * the driver (i.e. in state).
549 *
550 * This means any pre-existing port mapping is
551 * wiped out once our driver is initialized.
552 */
553 for (i = 0; i < dev->ports; i++) {
554 state->ports[i].mask = 0;
555 state->ports[i].qmode = MV_8021Q_MODE_DISABLE;
556 }
557
558 for (i = 0; i < dev->vlans; i++)
559 mvsw61xx_vlan_port_config(dev, i);
560
561 for (i = 0; i < dev->ports; i++) {
562 reg = sr16(dev, MV_PORTREG(VLANID, i)) & ~MV_PVID_MASK;
563 reg |= state->ports[i].pvid;
564 sw16(dev, MV_PORTREG(VLANID, i), reg);
565
566 state->ports[i].mask &= ~(1 << i);
567
568 /* set default forwarding DB number and port mask */
569 reg = sr16(dev, MV_PORTREG(CONTROL1, i)) & ~MV_FDB_HI_MASK;
570 reg |= (state->ports[i].fdb >> MV_FDB_HI_SHIFT) &
571 MV_FDB_HI_MASK;
572 sw16(dev, MV_PORTREG(CONTROL1, i), reg);
573
574 reg = ((state->ports[i].fdb & 0xf) << MV_FDB_LO_SHIFT) |
575 state->ports[i].mask;
576 sw16(dev, MV_PORTREG(VLANMAP, i), reg);
577
578 reg = sr16(dev, MV_PORTREG(CONTROL2, i)) &
579 ~MV_8021Q_MODE_MASK;
580 reg |= state->ports[i].qmode << MV_8021Q_MODE_SHIFT;
581 sw16(dev, MV_PORTREG(CONTROL2, i), reg);
582 }
583
584 mvsw61xx_vtu_program(dev);
585
586 return 0;
587 }
588
589 static int mvsw61xx_apply(struct switch_dev *dev)
590 {
591 return mvsw61xx_update_state(dev);
592 }
593
594 static int _mvsw61xx_reset(struct switch_dev *dev, bool full)
595 {
596 struct mvsw61xx_state *state = get_state(dev);
597 int i;
598 u16 reg;
599
600 /* Disable all ports before reset */
601 for (i = 0; i < dev->ports; i++) {
602 reg = sr16(dev, MV_PORTREG(CONTROL, i)) &
603 ~MV_PORTCTRL_FORWARDING;
604 sw16(dev, MV_PORTREG(CONTROL, i), reg);
605 }
606
607 reg = sr16(dev, MV_GLOBALREG(CONTROL)) | MV_CONTROL_RESET;
608
609 sw16(dev, MV_GLOBALREG(CONTROL), reg);
610 if (mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(CONTROL),
611 MV_CONTROL_RESET, 0) < 0)
612 return -ETIMEDOUT;
613
614 for (i = 0; i < dev->ports; i++) {
615 state->ports[i].fdb = 0;
616 state->ports[i].qmode = 0;
617 state->ports[i].mask = 0;
618 state->ports[i].pvid = 0;
619
620 /* Force flow control off */
621 reg = sr16(dev, MV_PORTREG(PHYCTL, i)) & ~MV_PHYCTL_FC_MASK;
622 reg |= MV_PHYCTL_FC_DISABLE;
623 sw16(dev, MV_PORTREG(PHYCTL, i), reg);
624
625 /* Set port association vector */
626 sw16(dev, MV_PORTREG(ASSOC, i), (1 << i));
627
628 /* power up phys */
629 if (full && i < 5) {
630 mvsw61xx_mdio_write(dev, i, MII_MV_SPEC_CTRL,
631 MV_SPEC_MDI_CROSS_AUTO |
632 MV_SPEC_ENERGY_DETECT |
633 MV_SPEC_DOWNSHIFT_COUNTER);
634 mvsw61xx_mdio_write(dev, i, MII_BMCR, BMCR_RESET |
635 BMCR_ANENABLE | BMCR_FULLDPLX |
636 BMCR_SPEED1000);
637 }
638 }
639
640 for (i = 0; i < dev->vlans; i++) {
641 state->vlans[i].port_based = false;
642 state->vlans[i].mask = 0;
643 state->vlans[i].vid = 0;
644 state->vlans[i].port_mode = 0;
645 state->vlans[i].port_sstate = 0;
646 }
647
648 state->vlan_enabled = 0;
649
650 mvsw61xx_update_state(dev);
651
652 /* Re-enable ports */
653 for (i = 0; i < dev->ports; i++) {
654 reg = sr16(dev, MV_PORTREG(CONTROL, i)) |
655 MV_PORTCTRL_FORWARDING;
656 sw16(dev, MV_PORTREG(CONTROL, i), reg);
657 }
658
659 return 0;
660 }
661
662 static int mvsw61xx_reset(struct switch_dev *dev)
663 {
664 return _mvsw61xx_reset(dev, false);
665 }
666
667 enum {
668 MVSW61XX_ENABLE_VLAN,
669 };
670
671 enum {
672 MVSW61XX_VLAN_PORT_BASED,
673 MVSW61XX_VLAN_ID,
674 };
675
676 enum {
677 MVSW61XX_PORT_MASK,
678 MVSW61XX_PORT_QMODE,
679 };
680
681 static const struct switch_attr mvsw61xx_global[] = {
682 [MVSW61XX_ENABLE_VLAN] = {
683 .id = MVSW61XX_ENABLE_VLAN,
684 .type = SWITCH_TYPE_INT,
685 .name = "enable_vlan",
686 .description = "Enable 802.1q VLAN support",
687 .get = mvsw61xx_get_enable_vlan,
688 .set = mvsw61xx_set_enable_vlan,
689 },
690 };
691
692 static const struct switch_attr mvsw61xx_vlan[] = {
693 [MVSW61XX_VLAN_PORT_BASED] = {
694 .id = MVSW61XX_VLAN_PORT_BASED,
695 .type = SWITCH_TYPE_INT,
696 .name = "port_based",
697 .description = "Use port-based (non-802.1q) VLAN only",
698 .get = mvsw61xx_get_vlan_port_based,
699 .set = mvsw61xx_set_vlan_port_based,
700 },
701 [MVSW61XX_VLAN_ID] = {
702 .id = MVSW61XX_VLAN_ID,
703 .type = SWITCH_TYPE_INT,
704 .name = "vid",
705 .description = "Get/set VLAN ID",
706 .get = mvsw61xx_get_vid,
707 .set = mvsw61xx_set_vid,
708 },
709 };
710
711 static const struct switch_attr mvsw61xx_port[] = {
712 [MVSW61XX_PORT_MASK] = {
713 .id = MVSW61XX_PORT_MASK,
714 .type = SWITCH_TYPE_STRING,
715 .description = "Port-based VLAN mask",
716 .name = "mask",
717 .get = mvsw61xx_get_port_mask,
718 .set = NULL,
719 },
720 [MVSW61XX_PORT_QMODE] = {
721 .id = MVSW61XX_PORT_QMODE,
722 .type = SWITCH_TYPE_INT,
723 .description = "802.1q mode: 0=off/1=fallback/2=check/3=secure",
724 .name = "qmode",
725 .get = mvsw61xx_get_port_qmode,
726 .set = mvsw61xx_set_port_qmode,
727 },
728 };
729
730 static const struct switch_dev_ops mvsw61xx_ops = {
731 .attr_global = {
732 .attr = mvsw61xx_global,
733 .n_attr = ARRAY_SIZE(mvsw61xx_global),
734 },
735 .attr_vlan = {
736 .attr = mvsw61xx_vlan,
737 .n_attr = ARRAY_SIZE(mvsw61xx_vlan),
738 },
739 .attr_port = {
740 .attr = mvsw61xx_port,
741 .n_attr = ARRAY_SIZE(mvsw61xx_port),
742 },
743 .get_port_link = mvsw61xx_get_port_link,
744 .get_port_pvid = mvsw61xx_get_port_pvid,
745 .set_port_pvid = mvsw61xx_set_port_pvid,
746 .get_vlan_ports = mvsw61xx_get_vlan_ports,
747 .set_vlan_ports = mvsw61xx_set_vlan_ports,
748 .apply_config = mvsw61xx_apply,
749 .reset_switch = mvsw61xx_reset,
750 };
751
752 /* end swconfig stuff */
753
754 static int mvsw61xx_probe(struct platform_device *pdev)
755 {
756 struct mvsw61xx_state *state;
757 struct device_node *np = pdev->dev.of_node;
758 struct device_node *mdio;
759 char *model_str;
760 u32 val;
761 int err;
762
763 state = kzalloc(sizeof(*state), GFP_KERNEL);
764 if (!state)
765 return -ENOMEM;
766
767 mdio = of_parse_phandle(np, "mii-bus", 0);
768 if (!mdio) {
769 dev_err(&pdev->dev, "Couldn't get MII bus handle\n");
770 err = -ENODEV;
771 goto out_err;
772 }
773
774 state->bus = of_mdio_find_bus(mdio);
775 if (!state->bus) {
776 dev_err(&pdev->dev, "Couldn't find MII bus from handle\n");
777 err = -ENODEV;
778 goto out_err;
779 }
780
781 state->is_indirect = of_property_read_bool(np, "is-indirect");
782
783 if (state->is_indirect) {
784 if (of_property_read_u32(np, "reg", &val)) {
785 dev_err(&pdev->dev, "Switch address not specified\n");
786 err = -ENODEV;
787 goto out_err;
788 }
789
790 state->base_addr = val;
791 } else {
792 state->base_addr = MV_BASE;
793 }
794
795 state->model = r16(state->bus, state->is_indirect, state->base_addr,
796 MV_PORTREG(IDENT, 0)) & MV_IDENT_MASK;
797
798 switch(state->model) {
799 case MV_IDENT_VALUE_6171:
800 model_str = MV_IDENT_STR_6171;
801 break;
802 case MV_IDENT_VALUE_6172:
803 model_str = MV_IDENT_STR_6172;
804 break;
805 case MV_IDENT_VALUE_6176:
806 model_str = MV_IDENT_STR_6176;
807 break;
808 default:
809 dev_err(&pdev->dev, "No compatible switch found at 0x%02x\n",
810 state->base_addr);
811 err = -ENODEV;
812 goto out_err;
813 }
814
815 platform_set_drvdata(pdev, state);
816 dev_info(&pdev->dev, "Found %s at %s:%02x\n", model_str,
817 state->bus->id, state->base_addr);
818
819 dev_info(&pdev->dev, "Using %sdirect addressing\n",
820 (state->is_indirect ? "in" : ""));
821
822 if (of_property_read_u32(np, "cpu-port-0", &val)) {
823 dev_err(&pdev->dev, "CPU port not set\n");
824 err = -ENODEV;
825 goto out_err;
826 }
827
828 state->cpu_port0 = val;
829
830 if (!of_property_read_u32(np, "cpu-port-1", &val))
831 state->cpu_port1 = val;
832 else
833 state->cpu_port1 = -1;
834
835 state->dev.vlans = MV_VLANS;
836 state->dev.cpu_port = state->cpu_port0;
837 state->dev.ports = MV_PORTS;
838 state->dev.name = model_str;
839 state->dev.ops = &mvsw61xx_ops;
840 state->dev.alias = dev_name(&pdev->dev);
841
842 _mvsw61xx_reset(&state->dev, true);
843
844 err = register_switch(&state->dev, NULL);
845 if (err < 0)
846 goto out_err;
847
848 state->registered = true;
849
850 return 0;
851 out_err:
852 kfree(state);
853 return err;
854 }
855
856 static int
857 mvsw61xx_remove(struct platform_device *pdev)
858 {
859 struct mvsw61xx_state *state = platform_get_drvdata(pdev);
860
861 if (state->registered)
862 unregister_switch(&state->dev);
863
864 kfree(state);
865
866 return 0;
867 }
868
869 static const struct of_device_id mvsw61xx_match[] = {
870 { .compatible = "marvell,88e6171" },
871 { .compatible = "marvell,88e6172" },
872 { .compatible = "marvell,88e6176" },
873 { }
874 };
875 MODULE_DEVICE_TABLE(of, mvsw61xx_match);
876
877 static struct platform_driver mvsw61xx_driver = {
878 .probe = mvsw61xx_probe,
879 .remove = mvsw61xx_remove,
880 .driver = {
881 .name = "mvsw61xx",
882 .of_match_table = of_match_ptr(mvsw61xx_match),
883 .owner = THIS_MODULE,
884 },
885 };
886
887 static int __init mvsw61xx_module_init(void)
888 {
889 return platform_driver_register(&mvsw61xx_driver);
890 }
891 late_initcall(mvsw61xx_module_init);
892
893 static void __exit mvsw61xx_module_exit(void)
894 {
895 platform_driver_unregister(&mvsw61xx_driver);
896 }
897 module_exit(mvsw61xx_module_exit);
Staging tree of Mathias Kresin