target/linux/ipq40xx/patches-4.14/050-0002-mtd-nand-qcom-add-command-elements-in-BAM-transactio.patch

   1 From 8c4cdce8b1ab044a2ee1d86d5a086f67e32b3c10 Mon Sep 17 00:00:00 2001
   2 From: Abhishek Sahu <absahu@codeaurora.org>
   3 Date: Mon, 25 Sep 2017 13:21:25 +0530
   4 Subject: [PATCH 2/7] mtd: nand: qcom: add command elements in BAM transaction
   5
   6 All the QPIC register read/write through BAM DMA requires
   7 command descriptor which contains the array of command elements.
   8
   9 Reviewed-by: Archit Taneja <architt@codeaurora.org>
  10 Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
  11 Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
  12 ---
  13  drivers/mtd/nand/qcom_nandc.c | 19 ++++++++++++++++++-
  14  1 file changed, 18 insertions(+), 1 deletion(-)
  15
  16 --- a/drivers/mtd/nand/qcom_nandc.c
  17 +++ b/drivers/mtd/nand/qcom_nandc.c
  18 @@ -22,6 +22,7 @@
  19  #include <linux/of.h>
  20  #include <linux/of_device.h>
  21  #include <linux/delay.h>
  22 +#include <linux/dma/qcom_bam_dma.h>
  23
  24  /* NANDc reg offsets */
  25  #define        NAND_FLASH_CMD                  0x00
  26 @@ -199,6 +200,7 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
  27   */
  28  #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
  29
  30 +#define QPIC_PER_CW_CMD_ELEMENTS       32
  31  #define QPIC_PER_CW_CMD_SGL            32
  32  #define QPIC_PER_CW_DATA_SGL           8
  33
  34 @@ -221,8 +223,13 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
  35  /*
  36   * This data type corresponds to the BAM transaction which will be used for all
  37   * NAND transfers.
  38 + * @bam_ce - the array of BAM command elements
  39   * @cmd_sgl - sgl for NAND BAM command pipe
  40   * @data_sgl - sgl for NAND BAM consumer/producer pipe
  41 + * @bam_ce_pos - the index in bam_ce which is available for next sgl
  42 + * @bam_ce_start - the index in bam_ce which marks the start position ce
  43 + *                for current sgl. It will be used for size calculation
  44 + *                for current sgl
  45   * @cmd_sgl_pos - current index in command sgl.
  46   * @cmd_sgl_start - start index in command sgl.
  47   * @tx_sgl_pos - current index in data sgl for tx.
  48 @@ -231,8 +238,11 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_
  49   * @rx_sgl_start - start index in data sgl for rx.
  50   */
  51  struct bam_transaction {
  52 +       struct bam_cmd_element *bam_ce;
  53         struct scatterlist *cmd_sgl;
  54         struct scatterlist *data_sgl;
  55 +       u32 bam_ce_pos;
  56 +       u32 bam_ce_start;
  57         u32 cmd_sgl_pos;
  58         u32 cmd_sgl_start;
  59         u32 tx_sgl_pos;
  60 @@ -462,7 +472,8 @@ alloc_bam_transaction(struct qcom_nand_c
  61
  62         bam_txn_size =
  63                 sizeof(*bam_txn) + num_cw *
  64 -               ((sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
  65 +               ((sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS) +
  66 +               (sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL) +
  67                 (sizeof(*bam_txn->data_sgl) * QPIC_PER_CW_DATA_SGL));
  68
  69         bam_txn_buf = devm_kzalloc(nandc->dev, bam_txn_size, GFP_KERNEL);
  70 @@ -472,6 +483,10 @@ alloc_bam_transaction(struct qcom_nand_c
  71         bam_txn = bam_txn_buf;
  72         bam_txn_buf += sizeof(*bam_txn);
  73
  74 +       bam_txn->bam_ce = bam_txn_buf;
  75 +       bam_txn_buf +=
  76 +               sizeof(*bam_txn->bam_ce) * QPIC_PER_CW_CMD_ELEMENTS * num_cw;
  77 +
  78         bam_txn->cmd_sgl = bam_txn_buf;
  79         bam_txn_buf +=
  80                 sizeof(*bam_txn->cmd_sgl) * QPIC_PER_CW_CMD_SGL * num_cw;
  81 @@ -489,6 +504,8 @@ static void clear_bam_transaction(struct
  82         if (!nandc->props->is_bam)
  83                 return;
  84
  85 +       bam_txn->bam_ce_pos = 0;
  86 +       bam_txn->bam_ce_start = 0;
  87         bam_txn->cmd_sgl_pos = 0;
  88         bam_txn->cmd_sgl_start = 0;
  89         bam_txn->tx_sgl_pos = 0;