dnsmasq: full: disable ipset support by default
[openwrt/staging/mkresin.git] / target / linux / ipq40xx / patches-4.14 / 088-0004-i2c-qup-remove-redundant-variables-for-BAM-SG-count.patch
1 From 6d5f37f166bb07b04b4d42e9d1f5427b7931cd3c Mon Sep 17 00:00:00 2001
2 From: Abhishek Sahu <absahu@codeaurora.org>
3 Date: Mon, 12 Mar 2018 18:44:53 +0530
4 Subject: [PATCH 04/13] i2c: qup: remove redundant variables for BAM SG count
5
6 The rx_nents and tx_nents are redundant. rx_buf and tx_buf can
7 be used for total number of SG entries. Since rx_buf and tx_buf
8 give the impression that it is buffer instead of count so rename
9 it to tx_cnt and rx_cnt for giving it more meaningful variable
10 name.
11
12 Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
13 Reviewed-by: Austin Christ <austinwc@codeaurora.org>
14 Reviewed-by: Andy Gross <andy.gross@linaro.org>
15 Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
16 ---
17 drivers/i2c/busses/i2c-qup.c | 42 ++++++++++++++++--------------------
18 1 file changed, 18 insertions(+), 24 deletions(-)
19
20 --- a/drivers/i2c/busses/i2c-qup.c
21 +++ b/drivers/i2c/busses/i2c-qup.c
22 @@ -683,8 +683,8 @@ static int qup_i2c_bam_do_xfer(struct qu
23 struct dma_async_tx_descriptor *txd, *rxd = NULL;
24 int ret = 0, idx = 0, limit = QUP_READ_LIMIT;
25 dma_cookie_t cookie_rx, cookie_tx;
26 - u32 rx_nents = 0, tx_nents = 0, len, blocks, rem;
27 - u32 i, tlen, tx_len, tx_buf = 0, rx_buf = 0, off = 0;
28 + u32 len, blocks, rem;
29 + u32 i, tlen, tx_len, tx_cnt = 0, rx_cnt = 0, off = 0;
30 u8 *tags;
31
32 while (idx < num) {
33 @@ -698,9 +698,6 @@ static int qup_i2c_bam_do_xfer(struct qu
34 rem = msg->len - (blocks - 1) * limit;
35
36 if (msg->flags & I2C_M_RD) {
37 - rx_nents += (blocks * 2) + 1;
38 - tx_nents += 1;
39 -
40 while (qup->blk.pos < blocks) {
41 tlen = (i == (blocks - 1)) ? rem : limit;
42 tags = &qup->start_tag.start[off + len];
43 @@ -708,14 +705,14 @@ static int qup_i2c_bam_do_xfer(struct qu
44 qup->blk.data_len -= tlen;
45
46 /* scratch buf to read the start and len tags */
47 - ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
48 + ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
49 &qup->brx.tag.start[0],
50 2, qup, DMA_FROM_DEVICE);
51
52 if (ret)
53 return ret;
54
55 - ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
56 + ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
57 &msg->buf[limit * i],
58 tlen, qup,
59 DMA_FROM_DEVICE);
60 @@ -725,7 +722,7 @@ static int qup_i2c_bam_do_xfer(struct qu
61 i++;
62 qup->blk.pos = i;
63 }
64 - ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
65 + ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++],
66 &qup->start_tag.start[off],
67 len, qup, DMA_TO_DEVICE);
68 if (ret)
69 @@ -733,28 +730,26 @@ static int qup_i2c_bam_do_xfer(struct qu
70
71 off += len;
72 /* scratch buf to read the BAM EOT and FLUSH tags */
73 - ret = qup_sg_set_buf(&qup->brx.sg[rx_buf++],
74 + ret = qup_sg_set_buf(&qup->brx.sg[rx_cnt++],
75 &qup->brx.tag.start[0],
76 2, qup, DMA_FROM_DEVICE);
77 if (ret)
78 return ret;
79 } else {
80 - tx_nents += (blocks * 2);
81 -
82 while (qup->blk.pos < blocks) {
83 tlen = (i == (blocks - 1)) ? rem : limit;
84 tags = &qup->start_tag.start[off + tx_len];
85 len = qup_i2c_set_tags(tags, qup, msg, 1);
86 qup->blk.data_len -= tlen;
87
88 - ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
89 + ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++],
90 tags, len,
91 qup, DMA_TO_DEVICE);
92 if (ret)
93 return ret;
94
95 tx_len += len;
96 - ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
97 + ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++],
98 &msg->buf[limit * i],
99 tlen, qup, DMA_TO_DEVICE);
100 if (ret)
101 @@ -766,26 +761,25 @@ static int qup_i2c_bam_do_xfer(struct qu
102
103 if (idx == (num - 1)) {
104 len = 1;
105 - if (rx_nents) {
106 + if (rx_cnt) {
107 qup->btx.tag.start[0] =
108 QUP_BAM_INPUT_EOT;
109 len++;
110 }
111 qup->btx.tag.start[len - 1] =
112 QUP_BAM_FLUSH_STOP;
113 - ret = qup_sg_set_buf(&qup->btx.sg[tx_buf++],
114 + ret = qup_sg_set_buf(&qup->btx.sg[tx_cnt++],
115 &qup->btx.tag.start[0],
116 len, qup, DMA_TO_DEVICE);
117 if (ret)
118 return ret;
119 - tx_nents += 1;
120 }
121 }
122 idx++;
123 msg++;
124 }
125
126 - txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_nents,
127 + txd = dmaengine_prep_slave_sg(qup->btx.dma, qup->btx.sg, tx_cnt,
128 DMA_MEM_TO_DEV,
129 DMA_PREP_INTERRUPT | DMA_PREP_FENCE);
130 if (!txd) {
131 @@ -794,7 +788,7 @@ static int qup_i2c_bam_do_xfer(struct qu
132 goto desc_err;
133 }
134
135 - if (!rx_nents) {
136 + if (!rx_cnt) {
137 txd->callback = qup_i2c_bam_cb;
138 txd->callback_param = qup;
139 }
140 @@ -807,9 +801,9 @@ static int qup_i2c_bam_do_xfer(struct qu
141
142 dma_async_issue_pending(qup->btx.dma);
143
144 - if (rx_nents) {
145 + if (rx_cnt) {
146 rxd = dmaengine_prep_slave_sg(qup->brx.dma, qup->brx.sg,
147 - rx_nents, DMA_DEV_TO_MEM,
148 + rx_cnt, DMA_DEV_TO_MEM,
149 DMA_PREP_INTERRUPT);
150 if (!rxd) {
151 dev_err(qup->dev, "failed to get rx desc\n");
152 @@ -844,7 +838,7 @@ static int qup_i2c_bam_do_xfer(struct qu
153 goto desc_err;
154 }
155
156 - if (rx_nents)
157 + if (rx_cnt)
158 writel(QUP_BAM_INPUT_EOT,
159 qup->base + QUP_OUT_FIFO_BASE);
160
161 @@ -862,10 +856,10 @@ static int qup_i2c_bam_do_xfer(struct qu
162 }
163
164 desc_err:
165 - dma_unmap_sg(qup->dev, qup->btx.sg, tx_nents, DMA_TO_DEVICE);
166 + dma_unmap_sg(qup->dev, qup->btx.sg, tx_cnt, DMA_TO_DEVICE);
167
168 - if (rx_nents)
169 - dma_unmap_sg(qup->dev, qup->brx.sg, rx_nents,
170 + if (rx_cnt)
171 + dma_unmap_sg(qup->dev, qup->brx.sg, rx_cnt,
172 DMA_FROM_DEVICE);
173
174 return ret;