target/linux/ipq40xx/patches-4.14/101-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch

   1 From patchwork Mon Jan 29 05:11:16 2018
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   5 Subject: [02/15] ARM: dts: ipq4019: Add a few peripheral nodes
   6 From: Sricharan R <sricharan@codeaurora.org>
   7 X-Patchwork-Id: 10189263
   8 Message-Id: <1517202689-14212-3-git-send-email-sricharan@codeaurora.org>
   9 To: robh+dt@kernel.org, robh@kernel.org, mark.rutland@arm.com,
  10  linux@armlinux.org.uk, andy.gross@linaro.org, david.brown@linaro.org,
  11  catalin.marinas@arm.com, will.deacon@arm.com, sboyd@codeaurora.org,
  12  bjorn.andersson@linaro.org, devicetree@vger.kernel.org,
  13  linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
  14  linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org
  15 Cc: sricharan@codeaurora.org
  16 Date: Mon, 29 Jan 2018 10:41:16 +0530
  17
  18 Now with the driver updates for some peripherals being there,
  19 add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
  20 peripheral support.
  21
  22 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  23 ---
  24  arch/arm/boot/dts/qcom-ipq4019.dtsi | 134 ++++++++++++++++++++++++++++++++++++
  25  1 file changed, 134 insertions(+)
  26
  27 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
  28 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
  29 @@ -25,7 +25,9 @@
  30
  31         aliases {
  32                 spi0 = &spi_0;
  33 +               spi1 = &spi_1;
  34                 i2c0 = &i2c_0;
  35 +               i2c1 = &i2c_1;
  36         };
  37
  38         cpus {
  39 @@ -190,6 +192,22 @@
  40                         clock-names = "core", "iface";
  41                         #address-cells = <1>;
  42                         #size-cells = <0>;
  43 +                       dmas = <&blsp_dma 5>, <&blsp_dma 4>;
  44 +                       dma-names = "rx", "tx";
  45 +                       status = "disabled";
  46 +               };
  47 +
  48 +               spi_1: spi@78b6000 { /* BLSP1 QUP2 */
  49 +                       compatible = "qcom,spi-qup-v2.2.1";
  50 +                       reg = <0x78b6000 0x600>;
  51 +                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
  52 +                       clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
  53 +                               <&gcc GCC_BLSP1_AHB_CLK>;
  54 +                       clock-names = "core", "iface";
  55 +                       #address-cells = <1>;
  56 +                       #size-cells = <0>;
  57 +                       dmas = <&blsp_dma 7>, <&blsp_dma 6>;
  58 +                       dma-names = "rx", "tx";
  59                         status = "disabled";
  60                 };
  61
  62 @@ -202,9 +220,24 @@
  63                         clock-names = "iface", "core";
  64                         #address-cells = <1>;
  65                         #size-cells = <0>;
  66 +                       dmas = <&blsp_dma 9>, <&blsp_dma 8>;
  67 +                       dma-names = "rx", "tx";
  68                         status = "disabled";
  69                 };
  70
  71 +               i2c_1: i2c@78b8000 { /* BLSP1 QUP4 */
  72 +                       compatible = "qcom,i2c-qup-v2.2.1";
  73 +                       reg = <0x78b8000 0x600>;
  74 +                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
  75 +                       clocks = <&gcc GCC_BLSP1_AHB_CLK>,
  76 +                                <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
  77 +                       clock-names = "iface", "core";
  78 +                       #address-cells = <1>;
  79 +                       #size-cells = <0>;
  80 +                       dmas = <&blsp_dma 11>, <&blsp_dma 10>;
  81 +                       dma-names = "rx", "tx";
  82 +                       status = "disabled";
  83 +               };
  84
  85                 cryptobam: dma@8e04000 {
  86                         compatible = "qcom,bam-v1.7.0";
  87 @@ -311,6 +344,101 @@
  88                         reg = <0x4ab000 0x4>;
  89                 };
  90
  91 +               pcie0: pci@40000000 {
  92 +                       compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
  93 +                       reg =  <0x40000000 0xf1d
  94 +                               0x40000f20 0xa8
  95 +                               0x80000 0x2000
  96 +                               0x40100000 0x1000>;
  97 +                       reg-names = "dbi", "elbi", "parf", "config";
  98 +                       device_type = "pci";
  99 +                       linux,pci-domain = <0>;
 100 +                       bus-range = <0x00 0xff>;
 101 +                       num-lanes = <1>;
 102 +                       #address-cells = <3>;
 103 +                       #size-cells = <2>;
 104 +
 105 +                       ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
 106 +                                 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
 107 +
 108 +                       interrupts = <GIC_SPI 141 IRQ_TYPE_NONE>;
 109 +                       interrupt-names = "msi";
 110 +                       #interrupt-cells = <1>;
 111 +                       interrupt-map-mask = <0 0 0 0x7>;
 112 +                       interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 113 +                                       <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 114 +                                       <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 115 +                                       <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 116 +                       clocks = <&gcc GCC_PCIE_AHB_CLK>,
 117 +                                <&gcc GCC_PCIE_AXI_M_CLK>,
 118 +                                <&gcc GCC_PCIE_AXI_S_CLK>;
 119 +                       clock-names = "aux",
 120 +                                     "master_bus",
 121 +                                     "slave_bus";
 122 +
 123 +                       resets = <&gcc PCIE_AXI_M_ARES>,
 124 +                                <&gcc PCIE_AXI_S_ARES>,
 125 +                                <&gcc PCIE_PIPE_ARES>,
 126 +                                <&gcc PCIE_AXI_M_VMIDMT_ARES>,
 127 +                                <&gcc PCIE_AXI_S_XPU_ARES>,
 128 +                                <&gcc PCIE_PARF_XPU_ARES>,
 129 +                                <&gcc PCIE_PHY_ARES>,
 130 +                                <&gcc PCIE_AXI_M_STICKY_ARES>,
 131 +                                <&gcc PCIE_PIPE_STICKY_ARES>,
 132 +                                <&gcc PCIE_PWR_ARES>,
 133 +                                <&gcc PCIE_AHB_ARES>,
 134 +                                <&gcc PCIE_PHY_AHB_ARES>;
 135 +                       reset-names = "axi_m",
 136 +                                     "axi_s",
 137 +                                     "pipe",
 138 +                                     "axi_m_vmid",
 139 +                                     "axi_s_xpu",
 140 +                                     "parf",
 141 +                                     "phy",
 142 +                                     "axi_m_sticky",
 143 +                                     "pipe_sticky",
 144 +                                     "pwr",
 145 +                                     "ahb",
 146 +                                     "phy_ahb";
 147 +
 148 +                       status = "disabled";
 149 +               };
 150 +
 151 +               qpic_bam: dma@7984000 {
 152 +                       compatible = "qcom,bam-v1.7.0";
 153 +                       reg = <0x7984000 0x1a000>;
 154 +                       interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 155 +                       clocks = <&gcc GCC_QPIC_CLK>;
 156 +                       clock-names = "bam_clk";
 157 +                       #dma-cells = <1>;
 158 +                       qcom,ee = <0>;
 159 +                       status = "disabled";
 160 +               };
 161 +
 162 +               nand: qpic-nand@79b0000 {
 163 +                       compatible = "qcom,ipq4019-nand";
 164 +                       reg = <0x79b0000 0x1000>;
 165 +                       #address-cells = <1>;
 166 +                       #size-cells = <0>;
 167 +                       clocks = <&gcc GCC_QPIC_CLK>,
 168 +                                <&gcc GCC_QPIC_AHB_CLK>;
 169 +                       clock-names = "core", "aon";
 170 +
 171 +                       dmas = <&qpic_bam 0>,
 172 +                              <&qpic_bam 1>,
 173 +                              <&qpic_bam 2>;
 174 +                       dma-names = "tx", "rx", "cmd";
 175 +                       status = "disabled";
 176 +
 177 +                       nand@0 {
 178 +                               reg = <0>;
 179 +
 180 +                               nand-ecc-strength = <4>;
 181 +                               nand-ecc-step-size = <512>;
 182 +                               nand-bus-width = <8>;
 183 +                       };
 184 +               };
 185 +
 186                 wifi0: wifi@a000000 {
 187                         compatible = "qcom,ipq4019-wifi";
 188                         reg = <0xa000000 0x200000>;