target/linux/lantiq/files-4.14/arch/mips/boot/dts/EASY80920.dtsi

   1 #include "vr9.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
   5
   6 / {
   7         compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9";
   8
   9         chosen {
  10                 bootargs = "console=ttyLTQ0,115200";
  11         };
  12
  13         aliases {
  14                 led-boot = &power;
  15                 led-failsafe = &power;
  16                 led-running = &power;
  17                 led-upgrade = &power;
  18
  19                 led-usb = &led_usb1;
  20                 led-usb2 = &led_usb2;
  21         };
  22
  23         memory@0 {
  24                 device_type = "memory";
  25                 reg = <0x0 0x4000000>;
  26         };
  27
  28         gpio-keys-polled {
  29                 compatible = "gpio-keys-polled";
  30                 poll-interval = <100>;
  31 /*              reset {
  32                         label = "reset";
  33                         gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
  34                         linux,code = <KEY_RESTART>;
  35                 };*/
  36                 paging {
  37                         label = "paging";
  38                         gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
  39                         linux,code = <KEY_PHONE>;
  40                 };
  41         };
  42
  43         gpio-leds {
  44                 compatible = "gpio-leds";
  45
  46                 power: power {
  47                         label = "easy80920:green:power";
  48                         gpios = <&stp 9 GPIO_ACTIVE_HIGH>;
  49                         default-state = "keep";
  50                 };
  51                 warning {
  52                         label = "easy80920:green:warning";
  53                         gpios = <&stp 22 GPIO_ACTIVE_HIGH>;
  54                 };
  55                 fxs1 {
  56                         label = "easy80920:green:fxs1";
  57                         gpios = <&stp 21 GPIO_ACTIVE_HIGH>;
  58                 };
  59                 fxs2 {
  60                         label = "easy80920:green:fxs2";
  61                         gpios = <&stp 20 GPIO_ACTIVE_HIGH>;
  62                 };
  63                 fxo {
  64                         label = "easy80920:green:fxo";
  65                         gpios = <&stp 19 GPIO_ACTIVE_HIGH>;
  66                 };
  67                 led_usb1: usb1 {
  68                         label = "easy80920:green:usb1";
  69                         gpios = <&stp 18 GPIO_ACTIVE_HIGH>;
  70                 };
  71                 led_usb2: usb2 {
  72                         label = "easy80920:green:usb2";
  73                         gpios = <&stp 15 GPIO_ACTIVE_HIGH>;
  74                 };
  75                 sd {
  76                         label = "easy80920:green:sd";
  77                         gpios = <&stp 14 GPIO_ACTIVE_HIGH>;
  78                 };
  79                 wps {
  80                         label = "easy80920:green:wps";
  81                         gpios = <&stp 12 GPIO_ACTIVE_HIGH>;
  82                 };
  83         };
  84
  85         usb_vbus: regulator-usb-vbus {
  86                 compatible = "regulator-fixed";
  87
  88                 regulator-name = "USB_VBUS";
  89
  90                 regulator-min-microvolt = <5000000>;
  91                 regulator-max-microvolt = <5000000>;
  92
  93                 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
  94                 enable-active-high;
  95         };
  96 };
  97
  98 &eth0 {
  99         lan: interface@0 {
 100                 compatible = "lantiq,xrx200-pdi";
 101                 #address-cells = <1>;
 102                 #size-cells = <0>;
 103                 reg = <0>;
 104                 lantiq,switch;
 105
 106                 ethernet@4 {
 107                         compatible = "lantiq,xrx200-pdi-port";
 108                         reg = <4>;
 109                         phy-mode = "gmii";
 110                         phy-handle = <&phy13>;
 111                 };
 112                 ethernet@2 {
 113                         compatible = "lantiq,xrx200-pdi-port";
 114                         reg = <2>;
 115                         phy-mode = "gmii";
 116                         phy-handle = <&phy11>;
 117                 };
 118                 ethernet@1 {
 119                         compatible = "lantiq,xrx200-pdi-port";
 120                         reg = <1>;
 121                         phy-mode = "rgmii";
 122                         phy-handle = <&phy1>;
 123                 };
 124                 ethernet@0 {
 125                         compatible = "lantiq,xrx200-pdi-port";
 126                         reg = <0>;
 127                         phy-mode = "rgmii";
 128                         phy-handle = <&phy0>;
 129                 };
 130         };
 131
 132         wan: interface@1 {
 133                 compatible = "lantiq,xrx200-pdi";
 134                 #address-cells = <1>;
 135                 #size-cells = <0>;
 136                 reg = <1>;
 137                 lantiq,wan;
 138
 139                 ethernet@5 {
 140                         compatible = "lantiq,xrx200-pdi-port";
 141                         reg = <5>;
 142                         phy-mode = "rgmii";
 143                         phy-handle = <&phy5>;
 144                 };
 145         };
 146
 147         mdio {
 148                 #address-cells = <1>;
 149                 #size-cells = <0>;
 150                 compatible = "lantiq,xrx200-mdio";
 151
 152                 phy0: ethernet-phy@0 {
 153                         reg = <0x0>;
 154                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 155                 };
 156                 phy1: ethernet-phy@1 {
 157                         reg = <0x1>;
 158                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 159                 };
 160                 phy5: ethernet-phy@5 {
 161                         reg = <0x5>;
 162                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 163                 };
 164                 phy11: ethernet-phy@11 {
 165                         reg = <0x11>;
 166                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 167                 };
 168                 phy13: ethernet-phy@13 {
 169                         reg = <0x13>;
 170                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 171                 };
 172         };
 173 };
 174
 175 &gphy0 {
 176         lantiq,gphy-mode = <GPHY_MODE_GE>;
 177 };
 178
 179 &gphy1 {
 180         lantiq,gphy-mode = <GPHY_MODE_GE>;
 181 };
 182
 183 &gpio {
 184         pinctrl-names = "default";
 185         pinctrl-0 = <&state_default>;
 186
 187         state_default: pinmux {
 188                 exin3 {
 189                         lantiq,groups = "exin3";
 190                         lantiq,function = "exin";
 191                 };
 192                 stp {
 193                         lantiq,groups = "stp";
 194                         lantiq,function = "stp";
 195                 };
 196                 nand {
 197                         lantiq,groups = "nand cle", "nand ale",
 198                                         "nand rd", "nand rdy";
 199                         lantiq,function = "ebu";
 200                 };
 201                 mdio {
 202                         lantiq,groups = "mdio";
 203                         lantiq,function = "mdio";
 204                 };
 205                 pci {
 206                         lantiq,groups = "gnt1", "req1";
 207                         lantiq,function = "pci";
 208                 };
 209                 conf_out {
 210                         lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
 211                                         "io4", "io5", "io6", /* stp */
 212                                         "io21",
 213                                         "io33";
 214                         lantiq,open-drain;
 215                         lantiq,pull = <0>;
 216                         lantiq,output = <1>;
 217                 };
 218                 pcie-rst {
 219                         lantiq,pins = "io38";
 220                         lantiq,pull = <0>;
 221                         lantiq,output = <1>;
 222                 };
 223                 conf_in {
 224                         lantiq,pins = "io39", /* exin3 */
 225                                         "io48"; /* nand rdy */
 226                         lantiq,pull = <2>;
 227                 };
 228         };
 229         pins_spi_default: pins_spi_default {
 230                 spi_in {
 231                         lantiq,groups = "spi_di";
 232                         lantiq,function = "spi";
 233                 };
 234                 spi_out {
 235                         lantiq,groups = "spi_do", "spi_clk",
 236                                 "spi_cs4";
 237                         lantiq,function = "spi";
 238                         lantiq,output = <1>;
 239                 };
 240         };
 241 };
 242
 243 &spi {
 244         pinctrl-names = "default";
 245         pinctrl-0 = <&pins_spi_default>;
 246
 247         status = "okay";
 248
 249         m25p80@4 {
 250                 compatible = "jedec,spi-nor";
 251                 reg = <4>;
 252                 spi-max-frequency = <1000000>;
 253
 254                 partitions {
 255                         compatible = "fixed-partitions";
 256                         #address-cells = <1>;
 257                         #size-cells = <1>;
 258
 259                         partition@0 {
 260                                 reg = <0x0 0x20000>;
 261                                 label = "SPI (RO) U-Boot Image";
 262                                 read-only;
 263                         };
 264
 265                         partition@20000 {
 266                                 reg = <0x20000 0x10000>;
 267                                 label = "ENV_MAC";
 268                                 read-only;
 269                         };
 270
 271                         partition@30000 {
 272                                 reg = <0x30000 0x10000>;
 273                                 label = "DPF";
 274                                 read-only;
 275                         };
 276
 277                         partition@40000 {
 278                                 reg = <0x40000 0x10000>;
 279                                 label = "NVRAM";
 280                                 read-only;
 281                         };
 282
 283                         partition@500000 {
 284                                 reg = <0x50000 0x003a0000>;
 285                                 label = "kernel";
 286                         };
 287                 };
 288         };
 289 };
 290
 291 &stp {
 292         status = "okay";
 293
 294         lantiq,shadow = <0xffff>;
 295         lantiq,groups = <0x7>;
 296         lantiq,dsl = <0x3>;
 297         lantiq,phy1 = <0x7>;
 298         lantiq,phy2 = <0x7>;
 299         /* lantiq,rising; */
 300 };
 301
 302 &usb_phy0 {
 303         status = "okay";
 304 };
 305
 306 &usb0 {
 307         status = "okay";
 308         vbus-supply = <&usb_vbus>;
 309 };