target/linux/lantiq/files-4.14/arch/mips/boot/dts/EASY80920.dtsi

   1 #include "vr9.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
   5
   6 / {
   7         compatible = "lantiq,easy80920", "lantiq,xway", "lantiq,vr9";
   8
   9         chosen {
  10                 bootargs = "console=ttyLTQ0,115200";
  11         };
  12
  13         aliases {
  14                 led-boot = &power;
  15                 led-failsafe = &power;
  16                 led-running = &power;
  17                 led-upgrade = &power;
  18
  19                 led-usb = &led_usb1;
  20                 led-usb2 = &led_usb2;
  21         };
  22
  23         memory@0 {
  24                 device_type = "memory";
  25                 reg = <0x0 0x4000000>;
  26         };
  27
  28         gpio-keys-polled {
  29                 compatible = "gpio-keys-polled";
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32                 poll-interval = <100>;
  33 /*              reset {
  34                         label = "reset";
  35                         gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
  36                         linux,code = <KEY_RESTART>;
  37                 };*/
  38                 paging {
  39                         label = "paging";
  40                         gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
  41                         linux,code = <KEY_PHONE>;
  42                 };
  43         };
  44
  45         gpio-leds {
  46                 compatible = "gpio-leds";
  47
  48                 power: power {
  49                         label = "easy80920:green:power";
  50                         gpios = <&stp 9 GPIO_ACTIVE_HIGH>;
  51                         default-state = "keep";
  52                 };
  53                 warning {
  54                         label = "easy80920:green:warning";
  55                         gpios = <&stp 22 GPIO_ACTIVE_HIGH>;
  56                 };
  57                 fxs1 {
  58                         label = "easy80920:green:fxs1";
  59                         gpios = <&stp 21 GPIO_ACTIVE_HIGH>;
  60                 };
  61                 fxs2 {
  62                         label = "easy80920:green:fxs2";
  63                         gpios = <&stp 20 GPIO_ACTIVE_HIGH>;
  64                 };
  65                 fxo {
  66                         label = "easy80920:green:fxo";
  67                         gpios = <&stp 19 GPIO_ACTIVE_HIGH>;
  68                 };
  69                 led_usb1: usb1 {
  70                         label = "easy80920:green:usb1";
  71                         gpios = <&stp 18 GPIO_ACTIVE_HIGH>;
  72                 };
  73                 led_usb2: usb2 {
  74                         label = "easy80920:green:usb2";
  75                         gpios = <&stp 15 GPIO_ACTIVE_HIGH>;
  76                 };
  77                 sd {
  78                         label = "easy80920:green:sd";
  79                         gpios = <&stp 14 GPIO_ACTIVE_HIGH>;
  80                 };
  81                 wps {
  82                         label = "easy80920:green:wps";
  83                         gpios = <&stp 12 GPIO_ACTIVE_HIGH>;
  84                 };
  85         };
  86
  87         usb_vbus: regulator-usb-vbus {
  88                 compatible = "regulator-fixed";
  89
  90                 regulator-name = "USB_VBUS";
  91
  92                 regulator-min-microvolt = <5000000>;
  93                 regulator-max-microvolt = <5000000>;
  94
  95                 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
  96                 enable-active-high;
  97         };
  98 };
  99
 100 &eth0 {
 101         lan: interface@0 {
 102                 compatible = "lantiq,xrx200-pdi";
 103                 #address-cells = <1>;
 104                 #size-cells = <0>;
 105                 reg = <0>;
 106                 lantiq,switch;
 107
 108                 ethernet@4 {
 109                         compatible = "lantiq,xrx200-pdi-port";
 110                         reg = <4>;
 111                         phy-mode = "gmii";
 112                         phy-handle = <&phy13>;
 113                 };
 114                 ethernet@2 {
 115                         compatible = "lantiq,xrx200-pdi-port";
 116                         reg = <2>;
 117                         phy-mode = "gmii";
 118                         phy-handle = <&phy11>;
 119                 };
 120                 ethernet@1 {
 121                         compatible = "lantiq,xrx200-pdi-port";
 122                         reg = <1>;
 123                         phy-mode = "rgmii";
 124                         phy-handle = <&phy1>;
 125                 };
 126                 ethernet@0 {
 127                         compatible = "lantiq,xrx200-pdi-port";
 128                         reg = <0>;
 129                         phy-mode = "rgmii";
 130                         phy-handle = <&phy0>;
 131                 };
 132         };
 133
 134         wan: interface@1 {
 135                 compatible = "lantiq,xrx200-pdi";
 136                 #address-cells = <1>;
 137                 #size-cells = <0>;
 138                 reg = <1>;
 139                 lantiq,wan;
 140
 141                 ethernet@5 {
 142                         compatible = "lantiq,xrx200-pdi-port";
 143                         reg = <5>;
 144                         phy-mode = "rgmii";
 145                         phy-handle = <&phy5>;
 146                 };
 147         };
 148
 149         mdio {
 150                 #address-cells = <1>;
 151                 #size-cells = <0>;
 152                 compatible = "lantiq,xrx200-mdio";
 153
 154                 phy0: ethernet-phy@0 {
 155                         reg = <0x0>;
 156                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 157                 };
 158                 phy1: ethernet-phy@1 {
 159                         reg = <0x1>;
 160                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 161                 };
 162                 phy5: ethernet-phy@5 {
 163                         reg = <0x5>;
 164                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 165                 };
 166                 phy11: ethernet-phy@11 {
 167                         reg = <0x11>;
 168                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 169                 };
 170                 phy13: ethernet-phy@13 {
 171                         reg = <0x13>;
 172                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
 173                 };
 174         };
 175 };
 176
 177 &gphy0 {
 178         lantiq,gphy-mode = <GPHY_MODE_GE>;
 179 };
 180
 181 &gphy1 {
 182         lantiq,gphy-mode = <GPHY_MODE_GE>;
 183 };
 184
 185 &gpio {
 186         pinctrl-names = "default";
 187         pinctrl-0 = <&state_default>;
 188
 189         state_default: pinmux {
 190                 exin3 {
 191                         lantiq,groups = "exin3";
 192                         lantiq,function = "exin";
 193                 };
 194                 stp {
 195                         lantiq,groups = "stp";
 196                         lantiq,function = "stp";
 197                 };
 198                 nand {
 199                         lantiq,groups = "nand cle", "nand ale",
 200                                         "nand rd", "nand rdy";
 201                         lantiq,function = "ebu";
 202                 };
 203                 mdio {
 204                         lantiq,groups = "mdio";
 205                         lantiq,function = "mdio";
 206                 };
 207                 pci {
 208                         lantiq,groups = "gnt1", "req1";
 209                         lantiq,function = "pci";
 210                 };
 211                 conf_out {
 212                         lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
 213                                         "io4", "io5", "io6", /* stp */
 214                                         "io21",
 215                                         "io33";
 216                         lantiq,open-drain;
 217                         lantiq,pull = <0>;
 218                         lantiq,output = <1>;
 219                 };
 220                 pcie-rst {
 221                         lantiq,pins = "io38";
 222                         lantiq,pull = <0>;
 223                         lantiq,output = <1>;
 224                 };
 225                 conf_in {
 226                         lantiq,pins = "io39", /* exin3 */
 227                                         "io48"; /* nand rdy */
 228                         lantiq,pull = <2>;
 229                 };
 230         };
 231         pins_spi_default: pins_spi_default {
 232                 spi_in {
 233                         lantiq,groups = "spi_di";
 234                         lantiq,function = "spi";
 235                 };
 236                 spi_out {
 237                         lantiq,groups = "spi_do", "spi_clk",
 238                                 "spi_cs4";
 239                         lantiq,function = "spi";
 240                         lantiq,output = <1>;
 241                 };
 242         };
 243 };
 244
 245 &spi {
 246         pinctrl-names = "default";
 247         pinctrl-0 = <&pins_spi_default>;
 248
 249         status = "okay";
 250
 251         m25p80@4 {
 252                 #address-cells = <1>;
 253                 #size-cells = <1>;
 254                 compatible = "jedec,spi-nor";
 255                 reg = <4>;
 256                 spi-max-frequency = <1000000>;
 257
 258                 partitions {
 259                         compatible = "fixed-partitions";
 260                         #address-cells = <1>;
 261                         #size-cells = <1>;
 262
 263                         partition@0 {
 264                                 reg = <0x0 0x20000>;
 265                                 label = "SPI (RO) U-Boot Image";
 266                                 read-only;
 267                         };
 268
 269                         partition@20000 {
 270                                 reg = <0x20000 0x10000>;
 271                                 label = "ENV_MAC";
 272                                 read-only;
 273                         };
 274
 275                         partition@30000 {
 276                                 reg = <0x30000 0x10000>;
 277                                 label = "DPF";
 278                                 read-only;
 279                         };
 280
 281                         partition@40000 {
 282                                 reg = <0x40000 0x10000>;
 283                                 label = "NVRAM";
 284                                 read-only;
 285                         };
 286
 287                         partition@500000 {
 288                                 reg = <0x50000 0x003a0000>;
 289                                 label = "kernel";
 290                         };
 291                 };
 292         };
 293 };
 294
 295 &stp {
 296         status = "okay";
 297
 298         lantiq,shadow = <0xffff>;
 299         lantiq,groups = <0x7>;
 300         lantiq,dsl = <0x3>;
 301         lantiq,phy1 = <0x7>;
 302         lantiq,phy2 = <0x7>;
 303         /* lantiq,rising; */
 304 };
 305
 306 &usb_phy0 {
 307         status = "okay";
 308 };
 309
 310 &usb0 {
 311         status = "okay";
 312         vbus-supply = <&usb_vbus>;
 313 };