target/linux/lantiq/files-4.14/arch/mips/boot/dts/VR200.dtsi

   1 #include "vr9.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
   5
   6 / {
   7         memory@0 {
   8                 device_type = "memory";
   9                 reg = <0x0 0x7f00000>;
  10         };
  11
  12         usb_vbus: regulator-usb-vbus {
  13                 compatible = "regulator-fixed";
  14
  15                 regulator-name = "USB_VBUS";
  16
  17                 regulator-min-microvolt = <5000000>;
  18                 regulator-max-microvolt = <5000000>;
  19
  20                 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
  21                 enable-active-high;
  22         };
  23 };
  24
  25 &eth0 {
  26         lan: interface@0 {
  27                 compatible = "lantiq,xrx200-pdi";
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30                 reg = <0>;
  31                 mtd-mac-address = <&romfile 0xf100>;
  32                 lantiq,switch;
  33
  34                 ethernet@0 {
  35                         compatible = "lantiq,xrx200-pdi-port";
  36                         reg = <0>;
  37                         phy-mode = "rgmii";
  38                         phy-handle = <&phy0>;
  39                         // gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
  40                 };
  41                 ethernet@5 {
  42                         compatible = "lantiq,xrx200-pdi-port";
  43                         reg = <5>;
  44                         phy-mode = "rgmii";
  45                         phy-handle = <&phy5>;
  46                 };
  47                 ethernet@2 {
  48                         compatible = "lantiq,xrx200-pdi-port";
  49                         reg = <2>;
  50                         phy-mode = "gmii";
  51                         phy-handle = <&phy11>;
  52                 };
  53                 ethernet@3 {
  54                         compatible = "lantiq,xrx200-pdi-port";
  55                         reg = <4>;
  56                         phy-mode = "gmii";
  57                         phy-handle = <&phy13>;
  58                 };
  59         };
  60
  61         mdio@0 {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64                 compatible = "lantiq,xrx200-mdio";
  65                 reg = <0>;
  66
  67                 phy0: ethernet-phy@0 {
  68                         reg = <0x0>;
  69                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  70                 };
  71                 phy5: ethernet-phy@5 {
  72                         reg = <0x5>;
  73                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  74                 };
  75                 phy11: ethernet-phy@11 {
  76                         reg = <0x11>;
  77                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  78                 };
  79                 phy13: ethernet-phy@13 {
  80                         reg = <0x13>;
  81                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  82                 };
  83         };
  84 };
  85
  86 &gphy0 {
  87         lantiq,gphy-mode = <GPHY_MODE_GE>;
  88 };
  89
  90 &gphy1 {
  91         lantiq,gphy-mode = <GPHY_MODE_GE>;
  92 };
  93
  94 &gpio {
  95         pinctrl-names = "default";
  96         pinctrl-0 = <&state_default>;
  97
  98         state_default: pinmux {
  99                 mdio {
 100                         lantiq,groups = "mdio";
 101                         lantiq,function = "mdio";
 102                 };
 103                 gphy-leds {
 104                         lantiq,groups = "gphy0 led1", "gphy1 led1";
 105                         lantiq,function = "gphy";
 106                         lantiq,pull = <2>;
 107                         lantiq,open-drain = <0>;
 108                         lantiq,output = <1>;
 109                 };
 110                 phy-rst {
 111                         lantiq,pins = "io42";
 112                         lantiq,pull = <0>;
 113                         lantiq,open-drain = <0>;
 114                         lantiq,output = <1>;
 115                 };
 116                 pcie-rst {
 117                         lantiq,pins = "io38";
 118                         lantiq,pull = <0>;
 119                         lantiq,output = <1>;
 120                 };
 121         };
 122         pins_spi_default: pins_spi_default {
 123                 spi_in {
 124                         lantiq,groups = "spi_di";
 125                         lantiq,function = "spi";
 126                 };
 127                 spi_out {
 128                         lantiq,groups = "spi_do", "spi_clk",
 129                                 "spi_cs4";
 130                         lantiq,function = "spi";
 131                         lantiq,output = <1>;
 132                 };
 133         };
 134 };
 135
 136 &pci0 {
 137         status = "okay";
 138         gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
 139 };
 140
 141 &spi {
 142         status = "okay";
 143
 144         pinctrl-names = "default";
 145         pinctrl-0 = <&pins_spi_default>;
 146
 147         m25p80@4 {
 148                 #address-cells = <1>;
 149                 #size-cells = <1>;
 150                 compatible = "jedec,spi-nor";
 151                 reg = <4 0>;
 152                 spi-max-frequency = <33250000>;
 153                 m25p,fast-read;
 154
 155                 partitions {
 156                         compatible = "fixed-partitions";
 157                         #address-cells = <1>;
 158                         #size-cells = <1>;
 159
 160                         partition@0 {
 161                                 reg = <0x0 0x20000>;
 162                                 label = "u-boot";
 163                                 read-only;
 164                         };
 165
 166                         partition@20000 {
 167                                 reg = <0x20000 0xf90000>;
 168                                 label = "firmware";
 169                         };
 170
 171                         partition@fb0000 {
 172                                 reg = <0xfb0000 0x10000>;
 173                                 label = "radioDECT";
 174                                 read-only;
 175                         };
 176
 177                         partition@fc0000 {
 178                                 reg = <0xfc0000 0x10000>;
 179                                 label = "config";
 180                                 read-only;
 181                         };
 182
 183                         romfile: partition@fd0000 {
 184                                 reg = <0xfd0000 0x10000>;
 185                                 label = "romfile";
 186                                 read-only;
 187                         };
 188
 189                         partition@fe0000 {
 190                                 reg = <0xfe0000 0x10000>;
 191                                 label = "rom";
 192                                 read-only;
 193                         };
 194
 195                         partition@ff0000 {
 196                                 reg = <0xff0000 0x10000>;
 197                                 label = "radio";
 198                                 read-only;
 199                         };
 200                 };
 201         };
 202 };
 203
 204 &usb_phy0 {
 205         status = "okay";
 206 };
 207
 208 &usb_phy1 {
 209         status = "okay";
 210 };
 211
 212 &usb0 {
 213         status = "okay";
 214         vbus-supply = <&usb_vbus>;
 215 };
 216
 217 &usb1 {
 218         status = "okay";
 219         vbus-supply = <&usb_vbus>;
 220 };