target/linux/lantiq/files-4.14/arch/mips/boot/dts/VR200.dtsi

   1 #include "vr9.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
   5
   6 / {
   7         memory@0 {
   8                 reg = <0x0 0x7f00000>;
   9         };
  10
  11         usb_vbus: regulator-usb-vbus {
  12                 compatible = "regulator-fixed";
  13
  14                 regulator-name = "USB_VBUS";
  15
  16                 regulator-min-microvolt = <5000000>;
  17                 regulator-max-microvolt = <5000000>;
  18
  19                 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
  20                 enable-active-high;
  21         };
  22 };
  23
  24 &eth0 {
  25         lan: interface@0 {
  26                 compatible = "lantiq,xrx200-pdi";
  27                 #address-cells = <1>;
  28                 #size-cells = <0>;
  29                 reg = <0>;
  30                 mtd-mac-address = <&romfile 0xf100>;
  31                 lantiq,switch;
  32
  33                 ethernet@0 {
  34                         compatible = "lantiq,xrx200-pdi-port";
  35                         reg = <0>;
  36                         phy-mode = "rgmii";
  37                         phy-handle = <&phy0>;
  38                         // gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
  39                 };
  40                 ethernet@5 {
  41                         compatible = "lantiq,xrx200-pdi-port";
  42                         reg = <5>;
  43                         phy-mode = "rgmii";
  44                         phy-handle = <&phy5>;
  45                 };
  46                 ethernet@2 {
  47                         compatible = "lantiq,xrx200-pdi-port";
  48                         reg = <2>;
  49                         phy-mode = "gmii";
  50                         phy-handle = <&phy11>;
  51                 };
  52                 ethernet@3 {
  53                         compatible = "lantiq,xrx200-pdi-port";
  54                         reg = <4>;
  55                         phy-mode = "gmii";
  56                         phy-handle = <&phy13>;
  57                 };
  58         };
  59
  60         mdio@0 {
  61                 #address-cells = <1>;
  62                 #size-cells = <0>;
  63                 compatible = "lantiq,xrx200-mdio";
  64                 reg = <0>;
  65
  66                 phy0: ethernet-phy@0 {
  67                         reg = <0x0>;
  68                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  69                 };
  70                 phy5: ethernet-phy@5 {
  71                         reg = <0x5>;
  72                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  73                 };
  74                 phy11: ethernet-phy@11 {
  75                         reg = <0x11>;
  76                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  77                 };
  78                 phy13: ethernet-phy@13 {
  79                         reg = <0x13>;
  80                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  81                 };
  82         };
  83 };
  84
  85 &gphy0 {
  86         lantiq,gphy-mode = <GPHY_MODE_GE>;
  87 };
  88
  89 &gphy1 {
  90         lantiq,gphy-mode = <GPHY_MODE_GE>;
  91 };
  92
  93 &gpio {
  94         pinctrl-names = "default";
  95         pinctrl-0 = <&state_default>;
  96
  97         state_default: pinmux {
  98                 mdio {
  99                         lantiq,groups = "mdio";
 100                         lantiq,function = "mdio";
 101                 };
 102                 gphy-leds {
 103                         lantiq,groups = "gphy0 led1", "gphy1 led1";
 104                         lantiq,function = "gphy";
 105                         lantiq,pull = <2>;
 106                         lantiq,open-drain = <0>;
 107                         lantiq,output = <1>;
 108                 };
 109                 phy-rst {
 110                         lantiq,pins = "io42";
 111                         lantiq,pull = <0>;
 112                         lantiq,open-drain = <0>;
 113                         lantiq,output = <1>;
 114                 };
 115                 pcie-rst {
 116                         lantiq,pins = "io38";
 117                         lantiq,pull = <0>;
 118                         lantiq,output = <1>;
 119                 };
 120         };
 121         pins_spi_default: pins_spi_default {
 122                 spi_in {
 123                         lantiq,groups = "spi_di";
 124                         lantiq,function = "spi";
 125                 };
 126                 spi_out {
 127                         lantiq,groups = "spi_do", "spi_clk",
 128                                 "spi_cs4";
 129                         lantiq,function = "spi";
 130                         lantiq,output = <1>;
 131                 };
 132         };
 133 };
 134
 135 &pci0 {
 136         status = "okay";
 137         gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
 138 };
 139
 140 &spi {
 141         status = "okay";
 142
 143         pinctrl-names = "default";
 144         pinctrl-0 = <&pins_spi_default>;
 145
 146         m25p80@4 {
 147                 #address-cells = <1>;
 148                 #size-cells = <1>;
 149                 compatible = "jedec,spi-nor";
 150                 reg = <4 0>;
 151                 spi-max-frequency = <33250000>;
 152                 m25p,fast-read;
 153
 154                 partitions {
 155                         compatible = "fixed-partitions";
 156                         #address-cells = <1>;
 157                         #size-cells = <1>;
 158
 159                         partition@0 {
 160                                 reg = <0x0 0x20000>;
 161                                 label = "u-boot";
 162                                 read-only;
 163                         };
 164
 165                         partition@20000 {
 166                                 reg = <0x20000 0xf90000>;
 167                                 label = "firmware";
 168                         };
 169
 170                         partition@fb0000 {
 171                                 reg = <0xfb0000 0x10000>;
 172                                 label = "radioDECT";
 173                                 read-only;
 174                         };
 175
 176                         partition@fc0000 {
 177                                 reg = <0xfc0000 0x10000>;
 178                                 label = "config";
 179                                 read-only;
 180                         };
 181
 182                         romfile: partition@fd0000 {
 183                                 reg = <0xfd0000 0x10000>;
 184                                 label = "romfile";
 185                                 read-only;
 186                         };
 187
 188                         partition@fe0000 {
 189                                 reg = <0xfe0000 0x10000>;
 190                                 label = "rom";
 191                                 read-only;
 192                         };
 193
 194                         partition@ff0000 {
 195                                 reg = <0xff0000 0x10000>;
 196                                 label = "radio";
 197                                 read-only;
 198                         };
 199                 };
 200         };
 201 };
 202
 203 &usb_phy0 {
 204         status = "okay";
 205 };
 206
 207 &usb_phy1 {
 208         status = "okay";
 209 };
 210
 211 &usb0 {
 212         status = "okay";
 213         vbus-supply = <&usb_vbus>;
 214 };
 215
 216 &usb1 {
 217         status = "okay";
 218         vbus-supply = <&usb_vbus>;
 219 };