target/linux/lantiq/patches-4.14/0090-spi-lantiq-ssc-add-support-for-Lantiq-SSC-SPI-contro.patch

   1 From 941ab0bc001fe24e5f8ce88eed27f2a1b89f3e20 Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Tue, 14 Feb 2017 00:31:11 +0100
   4 Subject: spi: lantiq-ssc: add support for Lantiq SSC SPI controller
   5
   6 This driver supports the Lantiq SSC SPI controller in master
   7 mode. This controller is found on Intel (former Lantiq) SoCs like
   8 the Danube, Falcon, xRX200, xRX300.
   9
  10 The hardware uses two hardware FIFOs one for received and one for
  11 transferred bytes. When the driver writes data into the transmit FIFO
  12 the complete word is taken from the FIFO into a shift register. The
  13 data from this shift register is then written to the wire. This driver
  14 uses the interrupts signaling the status of the FIFOs and not the shift
  15 register. It is also possible to use the interrupts for the shift
  16 register, but they will send a signal after every word. When using the
  17 interrupts for the shift register we get a signal when the last word is
  18 written into the shift register and not when it is written to the wire.
  19 After all FIFOs are empty the driver busy waits till the hardware is
  20 not busy any more and returns the transfer status.
  21
  22 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  23 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
  24 Signed-off-by: Mark Brown <broonie@kernel.org>
  25 ---
  26  .../devicetree/bindings/spi/spi-lantiq-ssc.txt     |  29 +
  27  drivers/spi/Kconfig                                |   8 +
  28  drivers/spi/Makefile                               |   1 +
  29  drivers/spi/spi-lantiq-ssc.c                       | 983 +++++++++++++++++++++
  30  4 files changed, 1021 insertions(+)
  31  create mode 100644 Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
  32  create mode 100644 drivers/spi/spi-lantiq-ssc.c
  33
  34 --- /dev/null
  35 +++ b/Documentation/devicetree/bindings/spi/spi-lantiq-ssc.txt
  36 @@ -0,0 +1,29 @@
  37 +Lantiq Synchronous Serial Controller (SSC) SPI master driver
  38 +
  39 +Required properties:
  40 +- compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi"
  41 +- #address-cells: see spi-bus.txt
  42 +- #size-cells: see spi-bus.txt
  43 +- reg: address and length of the spi master registers
  44 +- interrupts: should contain the "spi_rx", "spi_tx" and "spi_err" interrupt.
  45 +
  46 +
  47 +Optional properties:
  48 +- clocks: spi clock phandle
  49 +- num-cs: see spi-bus.txt, set to 8 if unset
  50 +- base-cs: the number of the first chip select, set to 1 if unset.
  51 +
  52 +Example:
  53 +
  54 +
  55 +spi: spi@E100800 {
  56 +       compatible = "lantiq,xrx200-spi", "lantiq,xrx100-spi";
  57 +       reg = <0xE100800 0x100>;
  58 +       interrupt-parent = <&icu0>;
  59 +       interrupts = <22 23 24>;
  60 +       interrupt-names = "spi_rx", "spi_tx", "spi_err";
  61 +       #address-cells = <1>;
  62 +       #size-cells = <1>;
  63 +       num-cs = <6>;
  64 +       base-cs = <1>;
  65 +};
  66 --- a/drivers/spi/Kconfig
  67 +++ b/drivers/spi/Kconfig
  68 @@ -403,6 +403,14 @@ config SPI_NUC900
  69         help
  70           SPI driver for Nuvoton NUC900 series ARM SoCs
  71
  72 +config SPI_LANTIQ_SSC
  73 +       tristate "Lantiq SSC SPI controller"
  74 +       depends on LANTIQ
  75 +       help
  76 +         This driver supports the Lantiq SSC SPI controller in master
  77 +         mode. This controller is found on Intel (former Lantiq) SoCs like
  78 +         the Danube, Falcon, xRX200, xRX300.
  79 +
  80  config SPI_OC_TINY
  81         tristate "OpenCores tiny SPI"
  82         depends on GPIOLIB || COMPILE_TEST
  83 --- a/drivers/spi/Makefile
  84 +++ b/drivers/spi/Makefile
  85 @@ -47,6 +47,7 @@ obj-$(CONFIG_SPI_FSL_SPI)             += spi-fsl-sp
  86  obj-$(CONFIG_SPI_GPIO)                 += spi-gpio.o
  87  obj-$(CONFIG_SPI_IMG_SPFI)             += spi-img-spfi.o
  88  obj-$(CONFIG_SPI_IMX)                  += spi-imx.o
  89 +obj-$(CONFIG_SPI_LANTIQ_SSC)           += spi-lantiq-ssc.o
  90  obj-$(CONFIG_SPI_JCORE)                        += spi-jcore.o
  91  obj-$(CONFIG_SPI_LM70_LLP)             += spi-lm70llp.o
  92  obj-$(CONFIG_SPI_LP8841_RTC)           += spi-lp8841-rtc.o
  93 --- /dev/null
  94 +++ b/drivers/spi/spi-lantiq-ssc.c
  95 @@ -0,0 +1,983 @@
  96 +/*
  97 + * Copyright (C) 2011-2015 Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
  98 + * Copyright (C) 2016 Hauke Mehrtens <hauke@hauke-m.de>
  99 + *
 100 + * This program is free software; you can distribute it and/or modify it
 101 + * under the terms of the GNU General Public License (Version 2) as
 102 + * published by the Free Software Foundation.
 103 + */
 104 +
 105 +#include <linux/kernel.h>
 106 +#include <linux/module.h>
 107 +#include <linux/of_device.h>
 108 +#include <linux/clk.h>
 109 +#include <linux/io.h>
 110 +#include <linux/delay.h>
 111 +#include <linux/interrupt.h>
 112 +#include <linux/sched.h>
 113 +#include <linux/completion.h>
 114 +#include <linux/spinlock.h>
 115 +#include <linux/err.h>
 116 +#include <linux/gpio.h>
 117 +#include <linux/pm_runtime.h>
 118 +#include <linux/spi/spi.h>
 119 +
 120 +#ifdef CONFIG_LANTIQ
 121 +#include <lantiq_soc.h>
 122 +#endif
 123 +
 124 +#define SPI_RX_IRQ_NAME                "spi_rx"
 125 +#define SPI_TX_IRQ_NAME                "spi_tx"
 126 +#define SPI_ERR_IRQ_NAME       "spi_err"
 127 +#define SPI_FRM_IRQ_NAME       "spi_frm"
 128 +
 129 +#define SPI_CLC                        0x00
 130 +#define SPI_PISEL              0x04
 131 +#define SPI_ID                 0x08
 132 +#define SPI_CON                        0x10
 133 +#define SPI_STAT               0x14
 134 +#define SPI_WHBSTATE           0x18
 135 +#define SPI_TB                 0x20
 136 +#define SPI_RB                 0x24
 137 +#define SPI_RXFCON             0x30
 138 +#define SPI_TXFCON             0x34
 139 +#define SPI_FSTAT              0x38
 140 +#define SPI_BRT                        0x40
 141 +#define SPI_BRSTAT             0x44
 142 +#define SPI_SFCON              0x60
 143 +#define SPI_SFSTAT             0x64
 144 +#define SPI_GPOCON             0x70
 145 +#define SPI_GPOSTAT            0x74
 146 +#define SPI_FPGO               0x78
 147 +#define SPI_RXREQ              0x80
 148 +#define SPI_RXCNT              0x84
 149 +#define SPI_DMACON             0xec
 150 +#define SPI_IRNEN              0xf4
 151 +#define SPI_IRNICR             0xf8
 152 +#define SPI_IRNCR              0xfc
 153 +
 154 +#define SPI_CLC_SMC_S          16      /* Clock divider for sleep mode */
 155 +#define SPI_CLC_SMC_M          (0xFF << SPI_CLC_SMC_S)
 156 +#define SPI_CLC_RMC_S          8       /* Clock divider for normal run mode */
 157 +#define SPI_CLC_RMC_M          (0xFF << SPI_CLC_RMC_S)
 158 +#define SPI_CLC_DISS           BIT(1)  /* Disable status bit */
 159 +#define SPI_CLC_DISR           BIT(0)  /* Disable request bit */
 160 +
 161 +#define SPI_ID_TXFS_S          24      /* Implemented TX FIFO size */
 162 +#define SPI_ID_TXFS_M          (0x3F << SPI_ID_TXFS_S)
 163 +#define SPI_ID_RXFS_S          16      /* Implemented RX FIFO size */
 164 +#define SPI_ID_RXFS_M          (0x3F << SPI_ID_RXFS_S)
 165 +#define SPI_ID_MOD_S           8       /* Module ID */
 166 +#define SPI_ID_MOD_M           (0xff << SPI_ID_MOD_S)
 167 +#define SPI_ID_CFG_S           5       /* DMA interface support */
 168 +#define SPI_ID_CFG_M           (1 << SPI_ID_CFG_S)
 169 +#define SPI_ID_REV_M           0x1F    /* Hardware revision number */
 170 +
 171 +#define SPI_CON_BM_S           16      /* Data width selection */
 172 +#define SPI_CON_BM_M           (0x1F << SPI_CON_BM_S)
 173 +#define SPI_CON_EM             BIT(24) /* Echo mode */
 174 +#define SPI_CON_IDLE           BIT(23) /* Idle bit value */
 175 +#define SPI_CON_ENBV           BIT(22) /* Enable byte valid control */
 176 +#define SPI_CON_RUEN           BIT(12) /* Receive underflow error enable */
 177 +#define SPI_CON_TUEN           BIT(11) /* Transmit underflow error enable */
 178 +#define SPI_CON_AEN            BIT(10) /* Abort error enable */
 179 +#define SPI_CON_REN            BIT(9)  /* Receive overflow error enable */
 180 +#define SPI_CON_TEN            BIT(8)  /* Transmit overflow error enable */
 181 +#define SPI_CON_LB             BIT(7)  /* Loopback control */
 182 +#define SPI_CON_PO             BIT(6)  /* Clock polarity control */
 183 +#define SPI_CON_PH             BIT(5)  /* Clock phase control */
 184 +#define SPI_CON_HB             BIT(4)  /* Heading control */
 185 +#define SPI_CON_RXOFF          BIT(1)  /* Switch receiver off */
 186 +#define SPI_CON_TXOFF          BIT(0)  /* Switch transmitter off */
 187 +
 188 +#define SPI_STAT_RXBV_S                28
 189 +#define SPI_STAT_RXBV_M                (0x7 << SPI_STAT_RXBV_S)
 190 +#define SPI_STAT_BSY           BIT(13) /* Busy flag */
 191 +#define SPI_STAT_RUE           BIT(12) /* Receive underflow error flag */
 192 +#define SPI_STAT_TUE           BIT(11) /* Transmit underflow error flag */
 193 +#define SPI_STAT_AE            BIT(10) /* Abort error flag */
 194 +#define SPI_STAT_RE            BIT(9)  /* Receive error flag */
 195 +#define SPI_STAT_TE            BIT(8)  /* Transmit error flag */
 196 +#define SPI_STAT_ME            BIT(7)  /* Mode error flag */
 197 +#define SPI_STAT_MS            BIT(1)  /* Master/slave select bit */
 198 +#define SPI_STAT_EN            BIT(0)  /* Enable bit */
 199 +#define SPI_STAT_ERRORS                (SPI_STAT_ME | SPI_STAT_TE | SPI_STAT_RE | \
 200 +                                SPI_STAT_AE | SPI_STAT_TUE | SPI_STAT_RUE)
 201 +
 202 +#define SPI_WHBSTATE_SETTUE    BIT(15) /* Set transmit underflow error flag */
 203 +#define SPI_WHBSTATE_SETAE     BIT(14) /* Set abort error flag */
 204 +#define SPI_WHBSTATE_SETRE     BIT(13) /* Set receive error flag */
 205 +#define SPI_WHBSTATE_SETTE     BIT(12) /* Set transmit error flag */
 206 +#define SPI_WHBSTATE_CLRTUE    BIT(11) /* Clear transmit underflow error flag */
 207 +#define SPI_WHBSTATE_CLRAE     BIT(10) /* Clear abort error flag */
 208 +#define SPI_WHBSTATE_CLRRE     BIT(9)  /* Clear receive error flag */
 209 +#define SPI_WHBSTATE_CLRTE     BIT(8)  /* Clear transmit error flag */
 210 +#define SPI_WHBSTATE_SETME     BIT(7)  /* Set mode error flag */
 211 +#define SPI_WHBSTATE_CLRME     BIT(6)  /* Clear mode error flag */
 212 +#define SPI_WHBSTATE_SETRUE    BIT(5)  /* Set receive underflow error flag */
 213 +#define SPI_WHBSTATE_CLRRUE    BIT(4)  /* Clear receive underflow error flag */
 214 +#define SPI_WHBSTATE_SETMS     BIT(3)  /* Set master select bit */
 215 +#define SPI_WHBSTATE_CLRMS     BIT(2)  /* Clear master select bit */
 216 +#define SPI_WHBSTATE_SETEN     BIT(1)  /* Set enable bit (operational mode) */
 217 +#define SPI_WHBSTATE_CLREN     BIT(0)  /* Clear enable bit (config mode */
 218 +#define SPI_WHBSTATE_CLR_ERRORS        (SPI_WHBSTATE_CLRRUE | SPI_WHBSTATE_CLRME | \
 219 +                                SPI_WHBSTATE_CLRTE | SPI_WHBSTATE_CLRRE | \
 220 +                                SPI_WHBSTATE_CLRAE | SPI_WHBSTATE_CLRTUE)
 221 +
 222 +#define SPI_RXFCON_RXFITL_S    8       /* FIFO interrupt trigger level */
 223 +#define SPI_RXFCON_RXFITL_M    (0x3F << SPI_RXFCON_RXFITL_S)
 224 +#define SPI_RXFCON_RXFLU       BIT(1)  /* FIFO flush */
 225 +#define SPI_RXFCON_RXFEN       BIT(0)  /* FIFO enable */
 226 +
 227 +#define SPI_TXFCON_TXFITL_S    8       /* FIFO interrupt trigger level */
 228 +#define SPI_TXFCON_TXFITL_M    (0x3F << SPI_TXFCON_TXFITL_S)
 229 +#define SPI_TXFCON_TXFLU       BIT(1)  /* FIFO flush */
 230 +#define SPI_TXFCON_TXFEN       BIT(0)  /* FIFO enable */
 231 +
 232 +#define SPI_FSTAT_RXFFL_S      0
 233 +#define SPI_FSTAT_RXFFL_M      (0x3f << SPI_FSTAT_RXFFL_S)
 234 +#define SPI_FSTAT_TXFFL_S      8
 235 +#define SPI_FSTAT_TXFFL_M      (0x3f << SPI_FSTAT_TXFFL_S)
 236 +
 237 +#define SPI_GPOCON_ISCSBN_S    8
 238 +#define SPI_GPOCON_INVOUTN_S   0
 239 +
 240 +#define SPI_FGPO_SETOUTN_S     8
 241 +#define SPI_FGPO_CLROUTN_S     0
 242 +
 243 +#define SPI_RXREQ_RXCNT_M      0xFFFF  /* Receive count value */
 244 +#define SPI_RXCNT_TODO_M       0xFFFF  /* Recevie to-do value */
 245 +
 246 +#define SPI_IRNEN_TFI          BIT(4)  /* TX finished interrupt */
 247 +#define SPI_IRNEN_F            BIT(3)  /* Frame end interrupt request */
 248 +#define SPI_IRNEN_E            BIT(2)  /* Error end interrupt request */
 249 +#define SPI_IRNEN_T_XWAY       BIT(1)  /* Transmit end interrupt request */
 250 +#define SPI_IRNEN_R_XWAY       BIT(0)  /* Receive end interrupt request */
 251 +#define SPI_IRNEN_R_XRX                BIT(1)  /* Transmit end interrupt request */
 252 +#define SPI_IRNEN_T_XRX                BIT(0)  /* Receive end interrupt request */
 253 +#define SPI_IRNEN_ALL          0x1F
 254 +
 255 +struct lantiq_ssc_hwcfg {
 256 +       unsigned int irnen_r;
 257 +       unsigned int irnen_t;
 258 +};
 259 +
 260 +struct lantiq_ssc_spi {
 261 +       struct spi_master               *master;
 262 +       struct device                   *dev;
 263 +       void __iomem                    *regbase;
 264 +       struct clk                      *spi_clk;
 265 +       struct clk                      *fpi_clk;
 266 +       const struct lantiq_ssc_hwcfg   *hwcfg;
 267 +
 268 +       spinlock_t                      lock;
 269 +       struct workqueue_struct         *wq;
 270 +       struct work_struct              work;
 271 +
 272 +       const u8                        *tx;
 273 +       u8                              *rx;
 274 +       unsigned int                    tx_todo;
 275 +       unsigned int                    rx_todo;
 276 +       unsigned int                    bits_per_word;
 277 +       unsigned int                    speed_hz;
 278 +       unsigned int                    tx_fifo_size;
 279 +       unsigned int                    rx_fifo_size;
 280 +       unsigned int                    base_cs;
 281 +};
 282 +
 283 +static u32 lantiq_ssc_readl(const struct lantiq_ssc_spi *spi, u32 reg)
 284 +{
 285 +       return __raw_readl(spi->regbase + reg);
 286 +}
 287 +
 288 +static void lantiq_ssc_writel(const struct lantiq_ssc_spi *spi, u32 val,
 289 +                             u32 reg)
 290 +{
 291 +       __raw_writel(val, spi->regbase + reg);
 292 +}
 293 +
 294 +static void lantiq_ssc_maskl(const struct lantiq_ssc_spi *spi, u32 clr,
 295 +                            u32 set, u32 reg)
 296 +{
 297 +       u32 val = __raw_readl(spi->regbase + reg);
 298 +
 299 +       val &= ~clr;
 300 +       val |= set;
 301 +       __raw_writel(val, spi->regbase + reg);
 302 +}
 303 +
 304 +static unsigned int tx_fifo_level(const struct lantiq_ssc_spi *spi)
 305 +{
 306 +       u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT);
 307 +
 308 +       return (fstat & SPI_FSTAT_TXFFL_M) >> SPI_FSTAT_TXFFL_S;
 309 +}
 310 +
 311 +static unsigned int rx_fifo_level(const struct lantiq_ssc_spi *spi)
 312 +{
 313 +       u32 fstat = lantiq_ssc_readl(spi, SPI_FSTAT);
 314 +
 315 +       return fstat & SPI_FSTAT_RXFFL_M;
 316 +}
 317 +
 318 +static unsigned int tx_fifo_free(const struct lantiq_ssc_spi *spi)
 319 +{
 320 +       return spi->tx_fifo_size - tx_fifo_level(spi);
 321 +}
 322 +
 323 +static void rx_fifo_reset(const struct lantiq_ssc_spi *spi)
 324 +{
 325 +       u32 val = spi->rx_fifo_size << SPI_RXFCON_RXFITL_S;
 326 +
 327 +       val |= SPI_RXFCON_RXFEN | SPI_RXFCON_RXFLU;
 328 +       lantiq_ssc_writel(spi, val, SPI_RXFCON);
 329 +}
 330 +
 331 +static void tx_fifo_reset(const struct lantiq_ssc_spi *spi)
 332 +{
 333 +       u32 val = 1 << SPI_TXFCON_TXFITL_S;
 334 +
 335 +       val |= SPI_TXFCON_TXFEN | SPI_TXFCON_TXFLU;
 336 +       lantiq_ssc_writel(spi, val, SPI_TXFCON);
 337 +}
 338 +
 339 +static void rx_fifo_flush(const struct lantiq_ssc_spi *spi)
 340 +{
 341 +       lantiq_ssc_maskl(spi, 0, SPI_RXFCON_RXFLU, SPI_RXFCON);
 342 +}
 343 +
 344 +static void tx_fifo_flush(const struct lantiq_ssc_spi *spi)
 345 +{
 346 +       lantiq_ssc_maskl(spi, 0, SPI_TXFCON_TXFLU, SPI_TXFCON);
 347 +}
 348 +
 349 +static void hw_enter_config_mode(const struct lantiq_ssc_spi *spi)
 350 +{
 351 +       lantiq_ssc_writel(spi, SPI_WHBSTATE_CLREN, SPI_WHBSTATE);
 352 +}
 353 +
 354 +static void hw_enter_active_mode(const struct lantiq_ssc_spi *spi)
 355 +{
 356 +       lantiq_ssc_writel(spi, SPI_WHBSTATE_SETEN, SPI_WHBSTATE);
 357 +}
 358 +
 359 +static void hw_setup_speed_hz(const struct lantiq_ssc_spi *spi,
 360 +                             unsigned int max_speed_hz)
 361 +{
 362 +       u32 spi_clk, brt;
 363 +
 364 +       /*
 365 +        * SPI module clock is derived from FPI bus clock dependent on
 366 +        * divider value in CLC.RMS which is always set to 1.
 367 +        *
 368 +        *                 f_SPI
 369 +        * baudrate = --------------
 370 +        *             2 * (BR + 1)
 371 +        */
 372 +       spi_clk = clk_get_rate(spi->fpi_clk) / 2;
 373 +
 374 +       if (max_speed_hz > spi_clk)
 375 +               brt = 0;
 376 +       else
 377 +               brt = spi_clk / max_speed_hz - 1;
 378 +
 379 +       if (brt > 0xFFFF)
 380 +               brt = 0xFFFF;
 381 +
 382 +       dev_dbg(spi->dev, "spi_clk %u, max_speed_hz %u, brt %u\n",
 383 +               spi_clk, max_speed_hz, brt);
 384 +
 385 +       lantiq_ssc_writel(spi, brt, SPI_BRT);
 386 +}
 387 +
 388 +static void hw_setup_bits_per_word(const struct lantiq_ssc_spi *spi,
 389 +                                  unsigned int bits_per_word)
 390 +{
 391 +       u32 bm;
 392 +
 393 +       /* CON.BM value = bits_per_word - 1 */
 394 +       bm = (bits_per_word - 1) << SPI_CON_BM_S;
 395 +
 396 +       lantiq_ssc_maskl(spi, SPI_CON_BM_M, bm, SPI_CON);
 397 +}
 398 +
 399 +static void hw_setup_clock_mode(const struct lantiq_ssc_spi *spi,
 400 +                               unsigned int mode)
 401 +{
 402 +       u32 con_set = 0, con_clr = 0;
 403 +
 404 +       /*
 405 +        * SPI mode mapping in CON register:
 406 +        * Mode CPOL CPHA CON.PO CON.PH
 407 +        *  0    0    0      0      1
 408 +        *  1    0    1      0      0
 409 +        *  2    1    0      1      1
 410 +        *  3    1    1      1      0
 411 +        */
 412 +       if (mode & SPI_CPHA)
 413 +               con_clr |= SPI_CON_PH;
 414 +       else
 415 +               con_set |= SPI_CON_PH;
 416 +
 417 +       if (mode & SPI_CPOL)
 418 +               con_set |= SPI_CON_PO | SPI_CON_IDLE;
 419 +       else
 420 +               con_clr |= SPI_CON_PO | SPI_CON_IDLE;
 421 +
 422 +       /* Set heading control */
 423 +       if (mode & SPI_LSB_FIRST)
 424 +               con_clr |= SPI_CON_HB;
 425 +       else
 426 +               con_set |= SPI_CON_HB;
 427 +
 428 +       /* Set loopback mode */
 429 +       if (mode & SPI_LOOP)
 430 +               con_set |= SPI_CON_LB;
 431 +       else
 432 +               con_clr |= SPI_CON_LB;
 433 +
 434 +       lantiq_ssc_maskl(spi, con_clr, con_set, SPI_CON);
 435 +}
 436 +
 437 +static void lantiq_ssc_hw_init(const struct lantiq_ssc_spi *spi)
 438 +{
 439 +       const struct lantiq_ssc_hwcfg *hwcfg = spi->hwcfg;
 440 +
 441 +       /*
 442 +        * Set clock divider for run mode to 1 to
 443 +        * run at same frequency as FPI bus
 444 +        */
 445 +       lantiq_ssc_writel(spi, 1 << SPI_CLC_RMC_S, SPI_CLC);
 446 +
 447 +       /* Put controller into config mode */
 448 +       hw_enter_config_mode(spi);
 449 +
 450 +       /* Clear error flags */
 451 +       lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE);
 452 +
 453 +       /* Enable error checking, disable TX/RX */
 454 +       lantiq_ssc_writel(spi, SPI_CON_RUEN | SPI_CON_AEN | SPI_CON_TEN |
 455 +               SPI_CON_REN | SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON);
 456 +
 457 +       /* Setup default SPI mode */
 458 +       hw_setup_bits_per_word(spi, spi->bits_per_word);
 459 +       hw_setup_clock_mode(spi, SPI_MODE_0);
 460 +
 461 +       /* Enable master mode and clear error flags */
 462 +       lantiq_ssc_writel(spi, SPI_WHBSTATE_SETMS | SPI_WHBSTATE_CLR_ERRORS,
 463 +                              SPI_WHBSTATE);
 464 +
 465 +       /* Reset GPIO/CS registers */
 466 +       lantiq_ssc_writel(spi, 0, SPI_GPOCON);
 467 +       lantiq_ssc_writel(spi, 0xFF00, SPI_FPGO);
 468 +
 469 +       /* Enable and flush FIFOs */
 470 +       rx_fifo_reset(spi);
 471 +       tx_fifo_reset(spi);
 472 +
 473 +       /* Enable interrupts */
 474 +       lantiq_ssc_writel(spi, hwcfg->irnen_t | hwcfg->irnen_r | SPI_IRNEN_E,
 475 +                         SPI_IRNEN);
 476 +}
 477 +
 478 +static int lantiq_ssc_setup(struct spi_device *spidev)
 479 +{
 480 +       struct spi_master *master = spidev->master;
 481 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 482 +       unsigned int cs = spidev->chip_select;
 483 +       u32 gpocon;
 484 +
 485 +       /* GPIOs are used for CS */
 486 +       if (gpio_is_valid(spidev->cs_gpio))
 487 +               return 0;
 488 +
 489 +       dev_dbg(spi->dev, "using internal chipselect %u\n", cs);
 490 +
 491 +       if (cs < spi->base_cs) {
 492 +               dev_err(spi->dev,
 493 +                       "chipselect %i too small (min %i)\n", cs, spi->base_cs);
 494 +               return -EINVAL;
 495 +       }
 496 +
 497 +       /* set GPO pin to CS mode */
 498 +       gpocon = 1 << ((cs - spi->base_cs) + SPI_GPOCON_ISCSBN_S);
 499 +
 500 +       /* invert GPO pin */
 501 +       if (spidev->mode & SPI_CS_HIGH)
 502 +               gpocon |= 1 << (cs - spi->base_cs);
 503 +
 504 +       lantiq_ssc_maskl(spi, 0, gpocon, SPI_GPOCON);
 505 +
 506 +       return 0;
 507 +}
 508 +
 509 +static int lantiq_ssc_prepare_message(struct spi_master *master,
 510 +                                     struct spi_message *message)
 511 +{
 512 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 513 +
 514 +       hw_enter_config_mode(spi);
 515 +       hw_setup_clock_mode(spi, message->spi->mode);
 516 +       hw_enter_active_mode(spi);
 517 +
 518 +       return 0;
 519 +}
 520 +
 521 +static void hw_setup_transfer(struct lantiq_ssc_spi *spi,
 522 +                             struct spi_device *spidev, struct spi_transfer *t)
 523 +{
 524 +       unsigned int speed_hz = t->speed_hz;
 525 +       unsigned int bits_per_word = t->bits_per_word;
 526 +       u32 con;
 527 +
 528 +       if (bits_per_word != spi->bits_per_word ||
 529 +               speed_hz != spi->speed_hz) {
 530 +               hw_enter_config_mode(spi);
 531 +               hw_setup_speed_hz(spi, speed_hz);
 532 +               hw_setup_bits_per_word(spi, bits_per_word);
 533 +               hw_enter_active_mode(spi);
 534 +
 535 +               spi->speed_hz = speed_hz;
 536 +               spi->bits_per_word = bits_per_word;
 537 +       }
 538 +
 539 +       /* Configure transmitter and receiver */
 540 +       con = lantiq_ssc_readl(spi, SPI_CON);
 541 +       if (t->tx_buf)
 542 +               con &= ~SPI_CON_TXOFF;
 543 +       else
 544 +               con |= SPI_CON_TXOFF;
 545 +
 546 +       if (t->rx_buf)
 547 +               con &= ~SPI_CON_RXOFF;
 548 +       else
 549 +               con |= SPI_CON_RXOFF;
 550 +
 551 +       lantiq_ssc_writel(spi, con, SPI_CON);
 552 +}
 553 +
 554 +static int lantiq_ssc_unprepare_message(struct spi_master *master,
 555 +                                       struct spi_message *message)
 556 +{
 557 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 558 +
 559 +       flush_workqueue(spi->wq);
 560 +
 561 +       /* Disable transmitter and receiver while idle */
 562 +       lantiq_ssc_maskl(spi, 0, SPI_CON_TXOFF | SPI_CON_RXOFF, SPI_CON);
 563 +
 564 +       return 0;
 565 +}
 566 +
 567 +static void tx_fifo_write(struct lantiq_ssc_spi *spi)
 568 +{
 569 +       const u8 *tx8;
 570 +       const u16 *tx16;
 571 +       const u32 *tx32;
 572 +       u32 data;
 573 +       unsigned int tx_free = tx_fifo_free(spi);
 574 +
 575 +       while (spi->tx_todo && tx_free) {
 576 +               switch (spi->bits_per_word) {
 577 +               case 2 ... 8:
 578 +                       tx8 = spi->tx;
 579 +                       data = *tx8;
 580 +                       spi->tx_todo--;
 581 +                       spi->tx++;
 582 +                       break;
 583 +               case 16:
 584 +                       tx16 = (u16 *) spi->tx;
 585 +                       data = *tx16;
 586 +                       spi->tx_todo -= 2;
 587 +                       spi->tx += 2;
 588 +                       break;
 589 +               case 32:
 590 +                       tx32 = (u32 *) spi->tx;
 591 +                       data = *tx32;
 592 +                       spi->tx_todo -= 4;
 593 +                       spi->tx += 4;
 594 +                       break;
 595 +               default:
 596 +                       WARN_ON(1);
 597 +                       data = 0;
 598 +                       break;
 599 +               }
 600 +
 601 +               lantiq_ssc_writel(spi, data, SPI_TB);
 602 +               tx_free--;
 603 +       }
 604 +}
 605 +
 606 +static void rx_fifo_read_full_duplex(struct lantiq_ssc_spi *spi)
 607 +{
 608 +       u8 *rx8;
 609 +       u16 *rx16;
 610 +       u32 *rx32;
 611 +       u32 data;
 612 +       unsigned int rx_fill = rx_fifo_level(spi);
 613 +
 614 +       while (rx_fill) {
 615 +               data = lantiq_ssc_readl(spi, SPI_RB);
 616 +
 617 +               switch (spi->bits_per_word) {
 618 +               case 2 ... 8:
 619 +                       rx8 = spi->rx;
 620 +                       *rx8 = data;
 621 +                       spi->rx_todo--;
 622 +                       spi->rx++;
 623 +                       break;
 624 +               case 16:
 625 +                       rx16 = (u16 *) spi->rx;
 626 +                       *rx16 = data;
 627 +                       spi->rx_todo -= 2;
 628 +                       spi->rx += 2;
 629 +                       break;
 630 +               case 32:
 631 +                       rx32 = (u32 *) spi->rx;
 632 +                       *rx32 = data;
 633 +                       spi->rx_todo -= 4;
 634 +                       spi->rx += 4;
 635 +                       break;
 636 +               default:
 637 +                       WARN_ON(1);
 638 +                       break;
 639 +               }
 640 +
 641 +               rx_fill--;
 642 +       }
 643 +}
 644 +
 645 +static void rx_fifo_read_half_duplex(struct lantiq_ssc_spi *spi)
 646 +{
 647 +       u32 data, *rx32;
 648 +       u8 *rx8;
 649 +       unsigned int rxbv, shift;
 650 +       unsigned int rx_fill = rx_fifo_level(spi);
 651 +
 652 +       /*
 653 +        * In RX-only mode the bits per word value is ignored by HW. A value
 654 +        * of 32 is used instead. Thus all 4 bytes per FIFO must be read.
 655 +        * If remaining RX bytes are less than 4, the FIFO must be read
 656 +        * differently. The amount of received and valid bytes is indicated
 657 +        * by STAT.RXBV register value.
 658 +        */
 659 +       while (rx_fill) {
 660 +               if (spi->rx_todo < 4)  {
 661 +                       rxbv = (lantiq_ssc_readl(spi, SPI_STAT) &
 662 +                               SPI_STAT_RXBV_M) >> SPI_STAT_RXBV_S;
 663 +                       data = lantiq_ssc_readl(spi, SPI_RB);
 664 +
 665 +                       shift = (rxbv - 1) * 8;
 666 +                       rx8 = spi->rx;
 667 +
 668 +                       while (rxbv) {
 669 +                               *rx8++ = (data >> shift) & 0xFF;
 670 +                               rxbv--;
 671 +                               shift -= 8;
 672 +                               spi->rx_todo--;
 673 +                               spi->rx++;
 674 +                       }
 675 +               } else {
 676 +                       data = lantiq_ssc_readl(spi, SPI_RB);
 677 +                       rx32 = (u32 *) spi->rx;
 678 +
 679 +                       *rx32++ = data;
 680 +                       spi->rx_todo -= 4;
 681 +                       spi->rx += 4;
 682 +               }
 683 +               rx_fill--;
 684 +       }
 685 +}
 686 +
 687 +static void rx_request(struct lantiq_ssc_spi *spi)
 688 +{
 689 +       unsigned int rxreq, rxreq_max;
 690 +
 691 +       /*
 692 +        * To avoid receive overflows at high clocks it is better to request
 693 +        * only the amount of bytes that fits into all FIFOs. This value
 694 +        * depends on the FIFO size implemented in hardware.
 695 +        */
 696 +       rxreq = spi->rx_todo;
 697 +       rxreq_max = spi->rx_fifo_size * 4;
 698 +       if (rxreq > rxreq_max)
 699 +               rxreq = rxreq_max;
 700 +
 701 +       lantiq_ssc_writel(spi, rxreq, SPI_RXREQ);
 702 +}
 703 +
 704 +static irqreturn_t lantiq_ssc_xmit_interrupt(int irq, void *data)
 705 +{
 706 +       struct lantiq_ssc_spi *spi = data;
 707 +
 708 +       if (spi->tx) {
 709 +               if (spi->rx && spi->rx_todo)
 710 +                       rx_fifo_read_full_duplex(spi);
 711 +
 712 +               if (spi->tx_todo)
 713 +                       tx_fifo_write(spi);
 714 +               else if (!tx_fifo_level(spi))
 715 +                       goto completed;
 716 +       } else if (spi->rx) {
 717 +               if (spi->rx_todo) {
 718 +                       rx_fifo_read_half_duplex(spi);
 719 +
 720 +                       if (spi->rx_todo)
 721 +                               rx_request(spi);
 722 +                       else
 723 +                               goto completed;
 724 +               } else {
 725 +                       goto completed;
 726 +               }
 727 +       }
 728 +
 729 +       return IRQ_HANDLED;
 730 +
 731 +completed:
 732 +       queue_work(spi->wq, &spi->work);
 733 +
 734 +       return IRQ_HANDLED;
 735 +}
 736 +
 737 +static irqreturn_t lantiq_ssc_err_interrupt(int irq, void *data)
 738 +{
 739 +       struct lantiq_ssc_spi *spi = data;
 740 +       u32 stat = lantiq_ssc_readl(spi, SPI_STAT);
 741 +
 742 +       if (!(stat & SPI_STAT_ERRORS))
 743 +               return IRQ_NONE;
 744 +
 745 +       if (stat & SPI_STAT_RUE)
 746 +               dev_err(spi->dev, "receive underflow error\n");
 747 +       if (stat & SPI_STAT_TUE)
 748 +               dev_err(spi->dev, "transmit underflow error\n");
 749 +       if (stat & SPI_STAT_AE)
 750 +               dev_err(spi->dev, "abort error\n");
 751 +       if (stat & SPI_STAT_RE)
 752 +               dev_err(spi->dev, "receive overflow error\n");
 753 +       if (stat & SPI_STAT_TE)
 754 +               dev_err(spi->dev, "transmit overflow error\n");
 755 +       if (stat & SPI_STAT_ME)
 756 +               dev_err(spi->dev, "mode error\n");
 757 +
 758 +       /* Clear error flags */
 759 +       lantiq_ssc_maskl(spi, 0, SPI_WHBSTATE_CLR_ERRORS, SPI_WHBSTATE);
 760 +
 761 +       /* set bad status so it can be retried */
 762 +       if (spi->master->cur_msg)
 763 +               spi->master->cur_msg->status = -EIO;
 764 +       queue_work(spi->wq, &spi->work);
 765 +
 766 +       return IRQ_HANDLED;
 767 +}
 768 +
 769 +static int transfer_start(struct lantiq_ssc_spi *spi, struct spi_device *spidev,
 770 +                         struct spi_transfer *t)
 771 +{
 772 +       unsigned long flags;
 773 +
 774 +       spin_lock_irqsave(&spi->lock, flags);
 775 +
 776 +       spi->tx = t->tx_buf;
 777 +       spi->rx = t->rx_buf;
 778 +
 779 +       if (t->tx_buf) {
 780 +               spi->tx_todo = t->len;
 781 +
 782 +               /* initially fill TX FIFO */
 783 +               tx_fifo_write(spi);
 784 +       }
 785 +
 786 +       if (spi->rx) {
 787 +               spi->rx_todo = t->len;
 788 +
 789 +               /* start shift clock in RX-only mode */
 790 +               if (!spi->tx)
 791 +                       rx_request(spi);
 792 +       }
 793 +
 794 +       spin_unlock_irqrestore(&spi->lock, flags);
 795 +
 796 +       return t->len;
 797 +}
 798 +
 799 +/*
 800 + * The driver only gets an interrupt when the FIFO is empty, but there
 801 + * is an additional shift register from which the data is written to
 802 + * the wire. We get the last interrupt when the controller starts to
 803 + * write the last word to the wire, not when it is finished. Do busy
 804 + * waiting till it finishes.
 805 + */
 806 +static void lantiq_ssc_bussy_work(struct work_struct *work)
 807 +{
 808 +       struct lantiq_ssc_spi *spi;
 809 +       unsigned long long timeout = 8LL * 1000LL;
 810 +       unsigned long end;
 811 +
 812 +       spi = container_of(work, typeof(*spi), work);
 813 +
 814 +       do_div(timeout, spi->speed_hz);
 815 +       timeout += timeout + 100; /* some tolerance */
 816 +
 817 +       end = jiffies + msecs_to_jiffies(timeout);
 818 +       do {
 819 +               u32 stat = lantiq_ssc_readl(spi, SPI_STAT);
 820 +
 821 +               if (!(stat & SPI_STAT_BSY)) {
 822 +                       spi_finalize_current_transfer(spi->master);
 823 +                       return;
 824 +               }
 825 +
 826 +               cond_resched();
 827 +       } while (!time_after_eq(jiffies, end));
 828 +
 829 +       if (spi->master->cur_msg)
 830 +               spi->master->cur_msg->status = -EIO;
 831 +       spi_finalize_current_transfer(spi->master);
 832 +}
 833 +
 834 +static void lantiq_ssc_handle_err(struct spi_master *master,
 835 +                                 struct spi_message *message)
 836 +{
 837 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 838 +
 839 +       /* flush FIFOs on timeout */
 840 +       rx_fifo_flush(spi);
 841 +       tx_fifo_flush(spi);
 842 +}
 843 +
 844 +static void lantiq_ssc_set_cs(struct spi_device *spidev, bool enable)
 845 +{
 846 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(spidev->master);
 847 +       unsigned int cs = spidev->chip_select;
 848 +       u32 fgpo;
 849 +
 850 +       if (!!(spidev->mode & SPI_CS_HIGH) == enable)
 851 +               fgpo = (1 << (cs - spi->base_cs));
 852 +       else
 853 +               fgpo = (1 << (cs - spi->base_cs + SPI_FGPO_SETOUTN_S));
 854 +
 855 +       lantiq_ssc_writel(spi, fgpo, SPI_FPGO);
 856 +}
 857 +
 858 +static int lantiq_ssc_transfer_one(struct spi_master *master,
 859 +                                  struct spi_device *spidev,
 860 +                                  struct spi_transfer *t)
 861 +{
 862 +       struct lantiq_ssc_spi *spi = spi_master_get_devdata(master);
 863 +
 864 +       hw_setup_transfer(spi, spidev, t);
 865 +
 866 +       return transfer_start(spi, spidev, t);
 867 +}
 868 +
 869 +static const struct lantiq_ssc_hwcfg lantiq_ssc_xway = {
 870 +       .irnen_r = SPI_IRNEN_R_XWAY,
 871 +       .irnen_t = SPI_IRNEN_T_XWAY,
 872 +};
 873 +
 874 +static const struct lantiq_ssc_hwcfg lantiq_ssc_xrx = {
 875 +       .irnen_r = SPI_IRNEN_R_XRX,
 876 +       .irnen_t = SPI_IRNEN_T_XRX,
 877 +};
 878 +
 879 +static const struct of_device_id lantiq_ssc_match[] = {
 880 +       { .compatible = "lantiq,ase-spi", .data = &lantiq_ssc_xway, },
 881 +       { .compatible = "lantiq,falcon-spi", .data = &lantiq_ssc_xrx, },
 882 +       { .compatible = "lantiq,xrx100-spi", .data = &lantiq_ssc_xrx, },
 883 +       {},
 884 +};
 885 +MODULE_DEVICE_TABLE(of, lantiq_ssc_match);
 886 +
 887 +static int lantiq_ssc_probe(struct platform_device *pdev)
 888 +{
 889 +       struct device *dev = &pdev->dev;
 890 +       struct spi_master *master;
 891 +       struct resource *res;
 892 +       struct lantiq_ssc_spi *spi;
 893 +       const struct lantiq_ssc_hwcfg *hwcfg;
 894 +       const struct of_device_id *match;
 895 +       int err, rx_irq, tx_irq, err_irq;
 896 +       u32 id, supports_dma, revision;
 897 +       unsigned int num_cs;
 898 +
 899 +       match = of_match_device(lantiq_ssc_match, dev);
 900 +       if (!match) {
 901 +               dev_err(dev, "no device match\n");
 902 +               return -EINVAL;
 903 +       }
 904 +       hwcfg = match->data;
 905 +
 906 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 907 +       if (!res) {
 908 +               dev_err(dev, "failed to get resources\n");
 909 +               return -ENXIO;
 910 +       }
 911 +
 912 +       rx_irq = platform_get_irq_byname(pdev, SPI_RX_IRQ_NAME);
 913 +       if (rx_irq < 0) {
 914 +               dev_err(dev, "failed to get %s\n", SPI_RX_IRQ_NAME);
 915 +               return -ENXIO;
 916 +       }
 917 +
 918 +       tx_irq = platform_get_irq_byname(pdev, SPI_TX_IRQ_NAME);
 919 +       if (tx_irq < 0) {
 920 +               dev_err(dev, "failed to get %s\n", SPI_TX_IRQ_NAME);
 921 +               return -ENXIO;
 922 +       }
 923 +
 924 +       err_irq = platform_get_irq_byname(pdev, SPI_ERR_IRQ_NAME);
 925 +       if (err_irq < 0) {
 926 +               dev_err(dev, "failed to get %s\n", SPI_ERR_IRQ_NAME);
 927 +               return -ENXIO;
 928 +       }
 929 +
 930 +       master = spi_alloc_master(dev, sizeof(struct lantiq_ssc_spi));
 931 +       if (!master)
 932 +               return -ENOMEM;
 933 +
 934 +       spi = spi_master_get_devdata(master);
 935 +       spi->master = master;
 936 +       spi->dev = dev;
 937 +       spi->hwcfg = hwcfg;
 938 +       platform_set_drvdata(pdev, spi);
 939 +
 940 +       spi->regbase = devm_ioremap_resource(dev, res);
 941 +       if (IS_ERR(spi->regbase)) {
 942 +               err = PTR_ERR(spi->regbase);
 943 +               goto err_master_put;
 944 +       }
 945 +
 946 +       err = devm_request_irq(dev, rx_irq, lantiq_ssc_xmit_interrupt,
 947 +                              0, SPI_RX_IRQ_NAME, spi);
 948 +       if (err)
 949 +               goto err_master_put;
 950 +
 951 +       err = devm_request_irq(dev, tx_irq, lantiq_ssc_xmit_interrupt,
 952 +                              0, SPI_TX_IRQ_NAME, spi);
 953 +       if (err)
 954 +               goto err_master_put;
 955 +
 956 +       err = devm_request_irq(dev, err_irq, lantiq_ssc_err_interrupt,
 957 +                              0, SPI_ERR_IRQ_NAME, spi);
 958 +       if (err)
 959 +               goto err_master_put;
 960 +
 961 +       spi->spi_clk = devm_clk_get(dev, "gate");
 962 +       if (IS_ERR(spi->spi_clk)) {
 963 +               err = PTR_ERR(spi->spi_clk);
 964 +               goto err_master_put;
 965 +       }
 966 +       err = clk_prepare_enable(spi->spi_clk);
 967 +       if (err)
 968 +               goto err_master_put;
 969 +
 970 +       /*
 971 +        * Use the old clk_get_fpi() function on Lantiq platform, till it
 972 +        * supports common clk.
 973 +        */
 974 +#if defined(CONFIG_LANTIQ) && !defined(CONFIG_COMMON_CLK)
 975 +       spi->fpi_clk = clk_get_fpi();
 976 +#else
 977 +       spi->fpi_clk = clk_get(dev, "freq");
 978 +#endif
 979 +       if (IS_ERR(spi->fpi_clk)) {
 980 +               err = PTR_ERR(spi->fpi_clk);
 981 +               goto err_clk_disable;
 982 +       }
 983 +
 984 +       num_cs = 8;
 985 +       of_property_read_u32(pdev->dev.of_node, "num-cs", &num_cs);
 986 +
 987 +       spi->base_cs = 1;
 988 +       of_property_read_u32(pdev->dev.of_node, "base-cs", &spi->base_cs);
 989 +
 990 +       spin_lock_init(&spi->lock);
 991 +       spi->bits_per_word = 8;
 992 +       spi->speed_hz = 0;
 993 +
 994 +       master->dev.of_node = pdev->dev.of_node;
 995 +       master->num_chipselect = num_cs;
 996 +       master->setup = lantiq_ssc_setup;
 997 +       master->set_cs = lantiq_ssc_set_cs;
 998 +       master->handle_err = lantiq_ssc_handle_err;
 999 +       master->prepare_message = lantiq_ssc_prepare_message;
1000 +       master->unprepare_message = lantiq_ssc_unprepare_message;
1001 +       master->transfer_one = lantiq_ssc_transfer_one;
1002 +       master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH |
1003 +                               SPI_LOOP;
1004 +       master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 8) |
1005 +                                    SPI_BPW_MASK(16) | SPI_BPW_MASK(32);
1006 +
1007 +       spi->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1008 +       if (!spi->wq) {
1009 +               err = -ENOMEM;
1010 +               goto err_clk_put;
1011 +       }
1012 +       INIT_WORK(&spi->work, lantiq_ssc_bussy_work);
1013 +
1014 +       id = lantiq_ssc_readl(spi, SPI_ID);
1015 +       spi->tx_fifo_size = (id & SPI_ID_TXFS_M) >> SPI_ID_TXFS_S;
1016 +       spi->rx_fifo_size = (id & SPI_ID_RXFS_M) >> SPI_ID_RXFS_S;
1017 +       supports_dma = (id & SPI_ID_CFG_M) >> SPI_ID_CFG_S;
1018 +       revision = id & SPI_ID_REV_M;
1019 +
1020 +       lantiq_ssc_hw_init(spi);
1021 +
1022 +       dev_info(dev,
1023 +               "Lantiq SSC SPI controller (Rev %i, TXFS %u, RXFS %u, DMA %u)\n",
1024 +               revision, spi->tx_fifo_size, spi->rx_fifo_size, supports_dma);
1025 +
1026 +       err = devm_spi_register_master(dev, master);
1027 +       if (err) {
1028 +               dev_err(dev, "failed to register spi_master\n");
1029 +               goto err_wq_destroy;
1030 +       }
1031 +
1032 +       return 0;
1033 +
1034 +err_wq_destroy:
1035 +       destroy_workqueue(spi->wq);
1036 +err_clk_put:
1037 +       clk_put(spi->fpi_clk);
1038 +err_clk_disable:
1039 +       clk_disable_unprepare(spi->spi_clk);
1040 +err_master_put:
1041 +       spi_master_put(master);
1042 +
1043 +       return err;
1044 +}
1045 +
1046 +static int lantiq_ssc_remove(struct platform_device *pdev)
1047 +{
1048 +       struct lantiq_ssc_spi *spi = platform_get_drvdata(pdev);
1049 +
1050 +       lantiq_ssc_writel(spi, 0, SPI_IRNEN);
1051 +       lantiq_ssc_writel(spi, 0, SPI_CLC);
1052 +       rx_fifo_flush(spi);
1053 +       tx_fifo_flush(spi);
1054 +       hw_enter_config_mode(spi);
1055 +
1056 +       destroy_workqueue(spi->wq);
1057 +       clk_disable_unprepare(spi->spi_clk);
1058 +       clk_put(spi->fpi_clk);
1059 +
1060 +       return 0;
1061 +}
1062 +
1063 +static struct platform_driver lantiq_ssc_driver = {
1064 +       .probe = lantiq_ssc_probe,
1065 +       .remove = lantiq_ssc_remove,
1066 +       .driver = {
1067 +               .name = "spi-lantiq-ssc",
1068 +               .owner = THIS_MODULE,
1069 +               .of_match_table = lantiq_ssc_match,
1070 +       },
1071 +};
1072 +module_platform_driver(lantiq_ssc_driver);
1073 +
1074 +MODULE_DESCRIPTION("Lantiq SSC SPI controller driver");
1075 +MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@gmail.com>");
1076 +MODULE_AUTHOR("Hauke Mehrtens <hauke@hauke-m.de>");
1077 +MODULE_LICENSE("GPL");
1078 +MODULE_ALIAS("platform:spi-lantiq-ssc");