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dnsmasq: full: disable ipset support by default
[openwrt/staging/mkresin.git] / target / linux / lantiq / patches-5.4 / 0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch
1 From fb0c9601f4414c39ff68e26b88681bef0bb04954 Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Mon, 22 Oct 2012 12:22:23 +0200
4 Subject: NET: MIPS: lantiq: adds xrx200 ethernet and switch driver
5
6 ---
7 drivers/net/ethernet/Kconfig | 8 +-
8 drivers/net/ethernet/Makefile | 1 +
9 drivers/net/ethernet/lantiq_pce.h | 163 +++
10 drivers/net/ethernet/lantiq_xrx200_legacy.c | 1798 +++++++++++++++++++++++++++++++
11 drivers/net/ethernet/lantiq_xrx200_legacy.h | 1328 +++++++++++++++++++++++
12 5 files changed, 3297 insertions(+), 1 deletion(-)
13 create mode 100644 drivers/net/ethernet/lantiq_pce.h
14 create mode 100644 drivers/net/ethernet/lantiq_xrx200_legacy.c
15 create mode 100644 drivers/net/ethernet/lantiq_xrx200_legacy.h
16
17 --- a/drivers/net/ethernet/Kconfig
18 +++ b/drivers/net/ethernet/Kconfig
19 @@ -108,7 +108,13 @@ config LANTIQ_ETOP
20 tristate "Lantiq SoC ETOP driver"
21 depends on SOC_TYPE_XWAY
22 ---help---
23 - Support for the MII0 inside the Lantiq SoC
24 + Support for the MII0 inside the Lantiq ADSL SoC
25 +
26 +config LANTIQ_XRX200_LEGACY
27 + tristate "Lantiq SoC XRX200 driver"
28 + depends on SOC_TYPE_XWAY
29 + ---help---
30 + Support for the MII0 inside the Lantiq VDSL SoC
31
32 config LANTIQ_XRX200
33 tristate "Lantiq / Intel xRX200 PMAC network driver"
34 --- a/drivers/net/ethernet/Makefile
35 +++ b/drivers/net/ethernet/Makefile
36 @@ -51,6 +51,7 @@ obj-$(CONFIG_JME) += jme.o
37 obj-$(CONFIG_KORINA) += korina.o
38 obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
39 obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o
40 +obj-$(CONFIG_LANTIQ_XRX200_LEGACY) += lantiq_xrx200_legacy.o
41 obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
42 obj-$(CONFIG_NET_VENDOR_MEDIATEK) += mediatek/
43 obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
44 --- /dev/null
45 +++ b/drivers/net/ethernet/lantiq_pce.h
46 @@ -0,0 +1,163 @@
47 +/*
48 + * This program is free software; you can redistribute it and/or modify it
49 + * under the terms of the GNU General Public License version 2 as published
50 + * by the Free Software Foundation.
51 + *
52 + * This program is distributed in the hope that it will be useful,
53 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
54 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
55 + * GNU General Public License for more details.
56 + *
57 + * You should have received a copy of the GNU General Public License
58 + * along with this program; if not, write to the Free Software
59 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
60 + *
61 + * Copyright (C) 2010 Lantiq Deutschland GmbH
62 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
63 + *
64 + * PCE microcode extracted from UGW5.2 switch api
65 + */
66 +
67 +/* Switch API Micro Code V0.3 */
68 +enum {
69 + OUT_MAC0 = 0,
70 + OUT_MAC1,
71 + OUT_MAC2,
72 + OUT_MAC3,
73 + OUT_MAC4,
74 + OUT_MAC5,
75 + OUT_ETHTYP,
76 + OUT_VTAG0,
77 + OUT_VTAG1,
78 + OUT_ITAG0,
79 + OUT_ITAG1, /*10 */
80 + OUT_ITAG2,
81 + OUT_ITAG3,
82 + OUT_IP0,
83 + OUT_IP1,
84 + OUT_IP2,
85 + OUT_IP3,
86 + OUT_SIP0,
87 + OUT_SIP1,
88 + OUT_SIP2,
89 + OUT_SIP3, /*20*/
90 + OUT_SIP4,
91 + OUT_SIP5,
92 + OUT_SIP6,
93 + OUT_SIP7,
94 + OUT_DIP0,
95 + OUT_DIP1,
96 + OUT_DIP2,
97 + OUT_DIP3,
98 + OUT_DIP4,
99 + OUT_DIP5, /*30*/
100 + OUT_DIP6,
101 + OUT_DIP7,
102 + OUT_SESID,
103 + OUT_PROT,
104 + OUT_APP0,
105 + OUT_APP1,
106 + OUT_IGMP0,
107 + OUT_IGMP1,
108 + OUT_IPOFF, /*39*/
109 + OUT_NONE = 63
110 +};
111 +
112 +/* parser's microcode length type */
113 +#define INSTR 0
114 +#define IPV6 1
115 +#define LENACCU 2
116 +
117 +/* parser's microcode flag type */
118 +enum {
119 + FLAG_ITAG = 0,
120 + FLAG_VLAN,
121 + FLAG_SNAP,
122 + FLAG_PPPOE,
123 + FLAG_IPV6,
124 + FLAG_IPV6FL,
125 + FLAG_IPV4,
126 + FLAG_IGMP,
127 + FLAG_TU,
128 + FLAG_HOP,
129 + FLAG_NN1, /*10 */
130 + FLAG_NN2,
131 + FLAG_END,
132 + FLAG_NO, /*13*/
133 +};
134 +
135 +/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */
136 +#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \
137 + { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }}
138 +struct pce_microcode {
139 + unsigned short val[4];
140 +/* unsigned short val_2;
141 + unsigned short val_1;
142 + unsigned short val_0;*/
143 +} pce_microcode[] = {
144 + /* value mask ns fields L type flags ipv4_len */
145 + MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
146 + MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
147 + MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
148 + MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
149 + MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
150 + MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
151 + MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
152 + MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
153 + MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0),
154 + MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
155 + MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
156 + MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0),
157 + MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0),
158 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
159 + MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0),
160 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
161 + MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0),
162 + MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0),
163 + MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0),
164 + MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0),
165 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
166 + MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1),
167 + MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0),
168 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
169 + MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0),
170 + MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0),
171 + MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0),
172 + MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
173 + MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
174 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0),
175 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0),
176 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0),
177 + MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
178 + MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0),
179 + MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0),
180 + MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0),
181 + MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0),
182 + MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0),
183 + MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0),
184 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
185 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
186 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
187 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
188 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
189 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
190 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
191 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
192 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
193 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
194 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
195 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
196 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
197 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
198 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
199 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
200 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
201 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
202 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
203 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
204 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
205 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
206 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
207 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
208 + MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
209 +};
210 --- /dev/null
211 +++ b/drivers/net/ethernet/lantiq_xrx200_legacy.c
212 @@ -0,0 +1,1927 @@
213 +/*
214 + * This program is free software; you can redistribute it and/or modify it
215 + * under the terms of the GNU General Public License version 2 as published
216 + * by the Free Software Foundation.
217 + *
218 + * This program is distributed in the hope that it will be useful,
219 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
220 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
221 + * GNU General Public License for more details.
222 + *
223 + * You should have received a copy of the GNU General Public License
224 + * along with this program; if not, write to the Free Software
225 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
226 + *
227 + * Copyright (C) 2010 Lantiq Deutschland
228 + * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
229 + */
230 +
231 +#include <linux/switch.h>
232 +#include <linux/etherdevice.h>
233 +#include <linux/module.h>
234 +#include <linux/platform_device.h>
235 +#include <linux/interrupt.h>
236 +#include <linux/clk.h>
237 +#include <linux/if_vlan.h>
238 +#include <asm/delay.h>
239 +
240 +#include <linux/of_net.h>
241 +#include <linux/of_mdio.h>
242 +#include <linux/of_gpio.h>
243 +#include <linux/of_platform.h>
244 +
245 +#include <xway_dma.h>
246 +#include <lantiq_soc.h>
247 +
248 +#include "lantiq_pce.h"
249 +#include "lantiq_xrx200_legacy.h"
250 +
251 +#define SW_POLLING
252 +#define SW_ROUTING
253 +
254 +#ifdef SW_ROUTING
255 +#define XRX200_MAX_DEV 2
256 +#else
257 +#define XRX200_MAX_DEV 1
258 +#endif
259 +
260 +#define XRX200_MAX_VLAN 64
261 +#define XRX200_PCE_ACTVLAN_IDX 0x01
262 +#define XRX200_PCE_VLANMAP_IDX 0x02
263 +
264 +#define XRX200_MAX_PORT 7
265 +#define XRX200_MAX_DMA 8
266 +
267 +#define XRX200_HEADROOM 4
268 +
269 +#define XRX200_TX_TIMEOUT (10 * HZ)
270 +
271 +/* port type */
272 +#define XRX200_PORT_TYPE_PHY 1
273 +#define XRX200_PORT_TYPE_MAC 2
274 +
275 +/* DMA */
276 +#define XRX200_DMA_DATA_LEN 0x600
277 +#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0
278 +#define XRX200_DMA_RX 0
279 +#define XRX200_DMA_TX 1
280 +#define XRX200_DMA_TX_2 3
281 +#define XRX200_DMA_IS_TX(x) (x%2)
282 +#define XRX200_DMA_IS_RX(x) (!XRX200_DMA_IS_TX(x))
283 +
284 +/* fetch / store dma */
285 +#define FDMA_PCTRL0 0x2A00
286 +#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18))
287 +#define SDMA_PCTRL0 0x2F00
288 +#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18))
289 +
290 +/* buffer management */
291 +#define BM_PCFG0 0x200
292 +#define BM_PCFGx(x) (BM_PCFG0 + (x * 8))
293 +
294 +/* MDIO */
295 +#define MDIO_GLOB 0x0000
296 +#define MDIO_CTRL 0x0020
297 +#define MDIO_READ 0x0024
298 +#define MDIO_WRITE 0x0028
299 +#define MDIO_PHY0 0x0054
300 +#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned)))
301 +#define MDIO_CLK_CFG0 0x002C
302 +#define MDIO_CLK_CFG1 0x0030
303 +
304 +#define MDIO_GLOB_ENABLE 0x8000
305 +#define MDIO_BUSY BIT(12)
306 +#define MDIO_RD BIT(11)
307 +#define MDIO_WR BIT(10)
308 +#define MDIO_MASK 0x1f
309 +#define MDIO_ADDRSHIFT 5
310 +#define MDIO1_25MHZ 9
311 +
312 +#define MDIO_PHY_LINK_DOWN 0x4000
313 +#define MDIO_PHY_LINK_UP 0x2000
314 +
315 +#define MDIO_PHY_SPEED_M10 0x0000
316 +#define MDIO_PHY_SPEED_M100 0x0800
317 +#define MDIO_PHY_SPEED_G1 0x1000
318 +
319 +#define MDIO_PHY_FDUP_EN 0x0200
320 +#define MDIO_PHY_FDUP_DIS 0x0600
321 +
322 +#define MDIO_PHY_LINK_MASK 0x6000
323 +#define MDIO_PHY_SPEED_MASK 0x1800
324 +#define MDIO_PHY_FDUP_MASK 0x0600
325 +#define MDIO_PHY_ADDR_MASK 0x001f
326 +#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \
327 + MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK
328 +
329 +/* MII */
330 +#define MII_CFG(p) (p * 8)
331 +
332 +#define MII_CFG_EN BIT(14)
333 +
334 +#define MII_CFG_MODE_MIIP 0x0
335 +#define MII_CFG_MODE_MIIM 0x1
336 +#define MII_CFG_MODE_RMIIP 0x2
337 +#define MII_CFG_MODE_RMIIM 0x3
338 +#define MII_CFG_MODE_RGMII 0x4
339 +#define MII_CFG_MODE_MASK 0xf
340 +
341 +#define MII_CFG_RATE_M2P5 0x00
342 +#define MII_CFG_RATE_M25 0x10
343 +#define MII_CFG_RATE_M125 0x20
344 +#define MII_CFG_RATE_M50 0x30
345 +#define MII_CFG_RATE_AUTO 0x40
346 +#define MII_CFG_RATE_MASK 0x70
347 +
348 +/* cpu port mac */
349 +#define PMAC_HD_CTL 0x0000
350 +#define PMAC_RX_IPG 0x0024
351 +#define PMAC_EWAN 0x002c
352 +
353 +#define PMAC_IPG_MASK 0xf
354 +#define PMAC_HD_CTL_AS 0x0008
355 +#define PMAC_HD_CTL_AC 0x0004
356 +#define PMAC_HD_CTL_RC 0x0010
357 +#define PMAC_HD_CTL_RXSH 0x0040
358 +#define PMAC_HD_CTL_AST 0x0080
359 +#define PMAC_HD_CTL_RST 0x0100
360 +
361 +/* PCE */
362 +#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4))
363 +#define PCE_TBL_MASK 0x1120
364 +#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4))
365 +#define PCE_TBL_ADDR 0x1138
366 +#define PCE_TBL_CTRL 0x113c
367 +#define PCE_PMAP1 0x114c
368 +#define PCE_PMAP2 0x1150
369 +#define PCE_PMAP3 0x1154
370 +#define PCE_GCTRL_REG(x) (0x1158 + (x * 4))
371 +#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4))
372 +
373 +#define PCE_TBL_BUSY BIT(15)
374 +#define PCE_TBL_CFG_ADDR_MASK 0x1f
375 +#define PCE_TBL_CFG_ADWR 0x20
376 +#define PCE_TBL_CFG_ADWR_MASK 0x60
377 +#define PCE_INGRESS BIT(11)
378 +
379 +/* MAC */
380 +#define MAC_FLEN_REG (0x2314)
381 +#define MAC_CTRL_REG(p, x) (0x240c + (((p * 0xc) + x) * 4))
382 +
383 +/* buffer management */
384 +#define BM_PCFG(p) (0x200 + (p * 8))
385 +
386 +/* special tag in TX path header */
387 +#define SPID_SHIFT 24
388 +#define DPID_SHIFT 16
389 +#define DPID_ENABLE 1
390 +#define SPID_CPU_PORT 2
391 +#define PORT_MAP_SEL BIT(15)
392 +#define PORT_MAP_EN BIT(14)
393 +#define PORT_MAP_SHIFT 1
394 +#define PORT_MAP_MASK 0x3f
395 +
396 +#define SPPID_MASK 0x7
397 +#define SPPID_SHIFT 4
398 +
399 +/* MII regs not yet in linux */
400 +#define MDIO_DEVAD_NONE (-1)
401 +#define ADVERTIZE_MPD (1 << 10)
402 +
403 +struct xrx200_port {
404 + u8 num;
405 + u8 phy_addr;
406 + u16 flags;
407 + phy_interface_t phy_if;
408 +
409 + int link;
410 + int gpio;
411 + enum of_gpio_flags gpio_flags;
412 +
413 + struct phy_device *phydev;
414 + struct device_node *phy_node;
415 +};
416 +
417 +struct xrx200_chan {
418 + int idx;
419 + int refcount;
420 + int tx_free;
421 +
422 + struct net_device dummy_dev;
423 + struct net_device *devs[XRX200_MAX_DEV];
424 +
425 + struct tasklet_struct tasklet;
426 + struct napi_struct napi;
427 + struct ltq_dma_channel dma;
428 + struct sk_buff *skb[LTQ_DESC_NUM];
429 +
430 + spinlock_t lock;
431 +};
432 +
433 +struct xrx200_hw {
434 + struct clk *clk;
435 + struct mii_bus *mii_bus;
436 + u8 phy_addr[XRX200_MAX_PORT];
437 +
438 + struct xrx200_chan chan[XRX200_MAX_DMA];
439 + u16 vlan_vid[XRX200_MAX_VLAN];
440 + u16 vlan_port_map[XRX200_MAX_VLAN];
441 +
442 + struct net_device *devs[XRX200_MAX_DEV];
443 + int num_devs;
444 +
445 + int port_map[XRX200_MAX_PORT];
446 + unsigned short wan_map;
447 +
448 + struct switch_dev swdev;
449 +};
450 +
451 +struct xrx200_priv {
452 + struct net_device_stats stats;
453 + int id;
454 +
455 + struct xrx200_port port[XRX200_MAX_PORT];
456 + int num_port;
457 + bool wan;
458 + bool sw;
459 + unsigned short port_map;
460 + unsigned char mac[6];
461 +
462 + struct xrx200_hw *hw;
463 +};
464 +
465 +static __iomem void *xrx200_switch_membase;
466 +static __iomem void *xrx200_mii_membase;
467 +static __iomem void *xrx200_mdio_membase;
468 +static __iomem void *xrx200_pmac_membase;
469 +
470 +#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x))
471 +#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y))
472 +#define ltq_switch_w32_mask(x, y, z) \
473 + ltq_w32_mask(x, y, xrx200_switch_membase + (z))
474 +
475 +#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x))
476 +#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y))
477 +#define ltq_mdio_w32_mask(x, y, z) \
478 + ltq_w32_mask(x, y, xrx200_mdio_membase + (z))
479 +
480 +#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x))
481 +#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y))
482 +#define ltq_mii_w32_mask(x, y, z) \
483 + ltq_w32_mask(x, y, xrx200_mii_membase + (z))
484 +
485 +#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x))
486 +#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y))
487 +#define ltq_pmac_w32_mask(x, y, z) \
488 + ltq_w32_mask(x, y, xrx200_pmac_membase + (z))
489 +
490 +#define XRX200_GLOBAL_REGATTR(reg) \
491 + .id = reg, \
492 + .type = SWITCH_TYPE_INT, \
493 + .set = xrx200_set_global_attr, \
494 + .get = xrx200_get_global_attr
495 +
496 +#define XRX200_PORT_REGATTR(reg) \
497 + .id = reg, \
498 + .type = SWITCH_TYPE_INT, \
499 + .set = xrx200_set_port_attr, \
500 + .get = xrx200_get_port_attr
501 +
502 +static int xrx200sw_read_x(int reg, int x)
503 +{
504 + int value, mask, addr;
505 +
506 + addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x);
507 + value = ltq_switch_r32(addr);
508 + mask = (1 << xrx200sw_reg[reg].size) - 1;
509 + value = (value >> xrx200sw_reg[reg].shift);
510 +
511 + return (value & mask);
512 +}
513 +
514 +static int xrx200sw_read(int reg)
515 +{
516 + return xrx200sw_read_x(reg, 0);
517 +}
518 +
519 +static void xrx200sw_write_x(int value, int reg, int x)
520 +{
521 + int mask, addr;
522 +
523 + addr = xrx200sw_reg[reg].offset + (xrx200sw_reg[reg].mult * x);
524 + mask = (1 << xrx200sw_reg[reg].size) - 1;
525 + mask = (mask << xrx200sw_reg[reg].shift);
526 + value = (value << xrx200sw_reg[reg].shift) & mask;
527 +
528 + ltq_switch_w32_mask(mask, value, addr);
529 +}
530 +
531 +static void xrx200sw_write(int value, int reg)
532 +{
533 + xrx200sw_write_x(value, reg, 0);
534 +}
535 +
536 +struct xrx200_pce_table_entry {
537 + int index; // PCE_TBL_ADDR.ADDR = pData->table_index
538 + int table; // PCE_TBL_CTRL.ADDR = pData->table
539 + unsigned short key[8];
540 + unsigned short val[5];
541 + unsigned short mask;
542 + unsigned short type;
543 + unsigned short valid;
544 + unsigned short gmap;
545 +};
546 +
547 +static int xrx200_pce_table_entry_read(struct xrx200_pce_table_entry *tbl)
548 +{
549 + // wait until hardware is ready
550 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
551 +
552 + // prepare the table access:
553 + // PCE_TBL_ADDR.ADDR = pData->table_index
554 + xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR);
555 + // PCE_TBL_CTRL.ADDR = pData->table
556 + xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR);
557 +
558 + //(address-based read)
559 + xrx200sw_write(0, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD
560 +
561 + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access
562 +
563 + // wait until hardware is ready
564 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
565 +
566 + // read the keys
567 + tbl->key[7] = xrx200sw_read(XRX200_PCE_TBL_KEY_7);
568 + tbl->key[6] = xrx200sw_read(XRX200_PCE_TBL_KEY_6);
569 + tbl->key[5] = xrx200sw_read(XRX200_PCE_TBL_KEY_5);
570 + tbl->key[4] = xrx200sw_read(XRX200_PCE_TBL_KEY_4);
571 + tbl->key[3] = xrx200sw_read(XRX200_PCE_TBL_KEY_3);
572 + tbl->key[2] = xrx200sw_read(XRX200_PCE_TBL_KEY_2);
573 + tbl->key[1] = xrx200sw_read(XRX200_PCE_TBL_KEY_1);
574 + tbl->key[0] = xrx200sw_read(XRX200_PCE_TBL_KEY_0);
575 +
576 + // read the values
577 + tbl->val[4] = xrx200sw_read(XRX200_PCE_TBL_VAL_4);
578 + tbl->val[3] = xrx200sw_read(XRX200_PCE_TBL_VAL_3);
579 + tbl->val[2] = xrx200sw_read(XRX200_PCE_TBL_VAL_2);
580 + tbl->val[1] = xrx200sw_read(XRX200_PCE_TBL_VAL_1);
581 + tbl->val[0] = xrx200sw_read(XRX200_PCE_TBL_VAL_0);
582 +
583 + // read the mask
584 + tbl->mask = xrx200sw_read(XRX200_PCE_TBL_MASK_0);
585 + // read the type
586 + tbl->type = xrx200sw_read(XRX200_PCE_TBL_CTRL_TYPE);
587 + // read the valid flag
588 + tbl->valid = xrx200sw_read(XRX200_PCE_TBL_CTRL_VLD);
589 + // read the group map
590 + tbl->gmap = xrx200sw_read(XRX200_PCE_TBL_CTRL_GMAP);
591 +
592 + return 0;
593 +}
594 +
595 +static int xrx200_pce_table_entry_write(struct xrx200_pce_table_entry *tbl)
596 +{
597 + // wait until hardware is ready
598 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
599 +
600 + // prepare the table access:
601 + // PCE_TBL_ADDR.ADDR = pData->table_index
602 + xrx200sw_write(tbl->index, XRX200_PCE_TBL_ADDR_ADDR);
603 + // PCE_TBL_CTRL.ADDR = pData->table
604 + xrx200sw_write(tbl->table, XRX200_PCE_TBL_CTRL_ADDR);
605 +
606 + //(address-based write)
607 + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_OPMOD); // OPMOD_ADRD
608 +
609 + // read the keys
610 + xrx200sw_write(tbl->key[7], XRX200_PCE_TBL_KEY_7);
611 + xrx200sw_write(tbl->key[6], XRX200_PCE_TBL_KEY_6);
612 + xrx200sw_write(tbl->key[5], XRX200_PCE_TBL_KEY_5);
613 + xrx200sw_write(tbl->key[4], XRX200_PCE_TBL_KEY_4);
614 + xrx200sw_write(tbl->key[3], XRX200_PCE_TBL_KEY_3);
615 + xrx200sw_write(tbl->key[2], XRX200_PCE_TBL_KEY_2);
616 + xrx200sw_write(tbl->key[1], XRX200_PCE_TBL_KEY_1);
617 + xrx200sw_write(tbl->key[0], XRX200_PCE_TBL_KEY_0);
618 +
619 + // read the values
620 + xrx200sw_write(tbl->val[4], XRX200_PCE_TBL_VAL_4);
621 + xrx200sw_write(tbl->val[3], XRX200_PCE_TBL_VAL_3);
622 + xrx200sw_write(tbl->val[2], XRX200_PCE_TBL_VAL_2);
623 + xrx200sw_write(tbl->val[1], XRX200_PCE_TBL_VAL_1);
624 + xrx200sw_write(tbl->val[0], XRX200_PCE_TBL_VAL_0);
625 +
626 + // read the mask
627 + xrx200sw_write(tbl->mask, XRX200_PCE_TBL_MASK_0);
628 + // read the type
629 + xrx200sw_write(tbl->type, XRX200_PCE_TBL_CTRL_TYPE);
630 + // read the valid flag
631 + xrx200sw_write(tbl->valid, XRX200_PCE_TBL_CTRL_VLD);
632 + // read the group map
633 + xrx200sw_write(tbl->gmap, XRX200_PCE_TBL_CTRL_GMAP);
634 +
635 + xrx200sw_write(1, XRX200_PCE_TBL_CTRL_BAS); // start access
636 +
637 + // wait until hardware is ready
638 + while (xrx200sw_read(XRX200_PCE_TBL_CTRL_BAS)) {};
639 +
640 + return 0;
641 +}
642 +
643 +static void xrx200sw_fixup_pvids(void)
644 +{
645 + int index, p, portmap, untagged;
646 + struct xrx200_pce_table_entry tem;
647 + struct xrx200_pce_table_entry tev;
648 +
649 + portmap = 0;
650 + for (p = 0; p < XRX200_MAX_PORT; p++)
651 + portmap |= BIT(p);
652 +
653 + tem.table = XRX200_PCE_VLANMAP_IDX;
654 + tev.table = XRX200_PCE_ACTVLAN_IDX;
655 +
656 + for (index = XRX200_MAX_VLAN; index-- > 0;)
657 + {
658 + tev.index = index;
659 + xrx200_pce_table_entry_read(&tev);
660 +
661 + if (tev.valid == 0)
662 + continue;
663 +
664 + tem.index = index;
665 + xrx200_pce_table_entry_read(&tem);
666 +
667 + if (tem.val[0] == 0)
668 + continue;
669 +
670 + untagged = portmap & (tem.val[1] ^ tem.val[2]);
671 +
672 + for (p = 0; p < XRX200_MAX_PORT; p++)
673 + if (untagged & BIT(p))
674 + {
675 + portmap &= ~BIT(p);
676 + xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p);
677 + }
678 +
679 + for (p = 0; p < XRX200_MAX_PORT; p++)
680 + if (portmap & BIT(p))
681 + xrx200sw_write_x(index, XRX200_PCE_DEFPVID_PVID, p);
682 + }
683 +}
684 +
685 +// swconfig interface
686 +static void xrx200_hw_init(struct xrx200_hw *hw);
687 +
688 +// global
689 +static int xrx200sw_reset_switch(struct switch_dev *dev)
690 +{
691 + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
692 +
693 + xrx200_hw_init(hw);
694 +
695 + return 0;
696 +}
697 +
698 +static int xrx200_set_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
699 +{
700 + int p;
701 +
702 + if ((attr->max > 0) && (val->value.i > attr->max))
703 + return -EINVAL;
704 +
705 + for (p = 0; p < XRX200_MAX_PORT; p++) {
706 + xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VEMR, p);
707 + xrx200sw_write_x(val->value.i, XRX200_PCE_VCTRL_VIMR, p);
708 + }
709 +
710 + xrx200sw_write(val->value.i, XRX200_PCE_GCTRL_0_VLAN);
711 + return 0;
712 +}
713 +
714 +static int xrx200_get_vlan_mode_enable(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
715 +{
716 + val->value.i = xrx200sw_read(attr->id);
717 + return 0;
718 +}
719 +
720 +static int xrx200_set_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
721 +{
722 + if ((attr->max > 0) && (val->value.i > attr->max))
723 + return -EINVAL;
724 +
725 + xrx200sw_write(val->value.i, attr->id);
726 + return 0;
727 +}
728 +
729 +static int xrx200_get_global_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
730 +{
731 + val->value.i = xrx200sw_read(attr->id);
732 + return 0;
733 +}
734 +
735 +// vlan
736 +static int xrx200sw_set_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr,
737 + struct switch_val *val)
738 +{
739 + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
740 + int i;
741 + struct xrx200_pce_table_entry tev;
742 + struct xrx200_pce_table_entry tem;
743 +
744 + tev.table = XRX200_PCE_ACTVLAN_IDX;
745 +
746 + for (i = 0; i < XRX200_MAX_VLAN; i++)
747 + {
748 + tev.index = i;
749 + xrx200_pce_table_entry_read(&tev);
750 + if (tev.key[0] == val->value.i && i != val->port_vlan)
751 + return -EINVAL;
752 + }
753 +
754 + hw->vlan_vid[val->port_vlan] = val->value.i;
755 +
756 + tev.index = val->port_vlan;
757 + xrx200_pce_table_entry_read(&tev);
758 + tev.key[0] = val->value.i;
759 + tev.valid = val->value.i > 0;
760 + xrx200_pce_table_entry_write(&tev);
761 +
762 + tem.table = XRX200_PCE_VLANMAP_IDX;
763 + tem.index = val->port_vlan;
764 + xrx200_pce_table_entry_read(&tem);
765 + tem.val[0] = val->value.i;
766 + xrx200_pce_table_entry_write(&tem);
767 +
768 + xrx200sw_fixup_pvids();
769 + return 0;
770 +}
771 +
772 +static int xrx200sw_get_vlan_vid(struct switch_dev *dev, const struct switch_attr *attr,
773 + struct switch_val *val)
774 +{
775 + struct xrx200_pce_table_entry te;
776 +
777 + te.table = XRX200_PCE_ACTVLAN_IDX;
778 + te.index = val->port_vlan;
779 + xrx200_pce_table_entry_read(&te);
780 + val->value.i = te.key[0];
781 +
782 + return 0;
783 +}
784 +
785 +static int xrx200sw_set_vlan_ports(struct switch_dev *dev, struct switch_val *val)
786 +{
787 + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
788 + int i, portmap, tagmap, untagged;
789 + struct xrx200_pce_table_entry tem;
790 +
791 + portmap = 0;
792 + tagmap = 0;
793 + for (i = 0; i < val->len; i++)
794 + {
795 + struct switch_port *p = &val->value.ports[i];
796 +
797 + portmap |= (1 << p->id);
798 + if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
799 + tagmap |= (1 << p->id);
800 + }
801 +
802 + tem.table = XRX200_PCE_VLANMAP_IDX;
803 +
804 + untagged = portmap ^ tagmap;
805 + for (i = 0; i < XRX200_MAX_VLAN; i++)
806 + {
807 + tem.index = i;
808 + xrx200_pce_table_entry_read(&tem);
809 +
810 + if (tem.val[0] == 0)
811 + continue;
812 +
813 + if ((untagged & (tem.val[1] ^ tem.val[2])) && (val->port_vlan != i))
814 + return -EINVAL;
815 + }
816 +
817 + tem.index = val->port_vlan;
818 + xrx200_pce_table_entry_read(&tem);
819 +
820 + // auto-enable this vlan if not enabled already
821 + if (tem.val[0] == 0)
822 + {
823 + struct switch_val v;
824 + v.port_vlan = val->port_vlan;
825 + v.value.i = val->port_vlan;
826 + if(xrx200sw_set_vlan_vid(dev, NULL, &v))
827 + return -EINVAL;
828 +
829 + //read updated tem
830 + tem.index = val->port_vlan;
831 + xrx200_pce_table_entry_read(&tem);
832 + }
833 +
834 + tem.val[1] = portmap;
835 + tem.val[2] = tagmap;
836 + xrx200_pce_table_entry_write(&tem);
837 +
838 + ltq_switch_w32_mask(0, portmap, PCE_PMAP2);
839 + ltq_switch_w32_mask(0, portmap, PCE_PMAP3);
840 + hw->vlan_port_map[val->port_vlan] = portmap;
841 +
842 + xrx200sw_fixup_pvids();
843 +
844 + return 0;
845 +}
846 +
847 +static int xrx200sw_get_vlan_ports(struct switch_dev *dev, struct switch_val *val)
848 +{
849 + int i;
850 + unsigned short ports, tags;
851 + struct xrx200_pce_table_entry tem;
852 +
853 + tem.table = XRX200_PCE_VLANMAP_IDX;
854 + tem.index = val->port_vlan;
855 + xrx200_pce_table_entry_read(&tem);
856 +
857 + ports = tem.val[1];
858 + tags = tem.val[2];
859 +
860 + for (i = 0; i < XRX200_MAX_PORT; i++) {
861 + struct switch_port *p;
862 +
863 + if (!(ports & (1 << i)))
864 + continue;
865 +
866 + p = &val->value.ports[val->len++];
867 + p->id = i;
868 + if (tags & (1 << i))
869 + p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
870 + else
871 + p->flags = 0;
872 + }
873 +
874 + return 0;
875 +}
876 +
877 +static int xrx200sw_set_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr,
878 + struct switch_val *val)
879 +{
880 + struct xrx200_pce_table_entry tev;
881 +
882 + tev.table = XRX200_PCE_ACTVLAN_IDX;
883 + tev.index = val->port_vlan;
884 + xrx200_pce_table_entry_read(&tev);
885 +
886 + if (tev.key[0] == 0)
887 + return -EINVAL;
888 +
889 + tev.valid = val->value.i;
890 + xrx200_pce_table_entry_write(&tev);
891 +
892 + xrx200sw_fixup_pvids();
893 + return 0;
894 +}
895 +
896 +static int xrx200sw_get_vlan_enable(struct switch_dev *dev, const struct switch_attr *attr,
897 + struct switch_val *val)
898 +{
899 + struct xrx200_pce_table_entry tev;
900 +
901 + tev.table = XRX200_PCE_ACTVLAN_IDX;
902 + tev.index = val->port_vlan;
903 + xrx200_pce_table_entry_read(&tev);
904 + val->value.i = tev.valid;
905 +
906 + return 0;
907 +}
908 +
909 +// port
910 +static int xrx200sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
911 +{
912 + struct xrx200_pce_table_entry tev;
913 +
914 + if (port >= XRX200_MAX_PORT)
915 + return -EINVAL;
916 +
917 + tev.table = XRX200_PCE_ACTVLAN_IDX;
918 + tev.index = xrx200sw_read_x(XRX200_PCE_DEFPVID_PVID, port);
919 + xrx200_pce_table_entry_read(&tev);
920 +
921 + *val = tev.key[0];
922 + return 0;
923 +}
924 +
925 +static int xrx200sw_get_port_link(struct switch_dev *dev,
926 + int port,
927 + struct switch_port_link *link)
928 +{
929 + if (port >= XRX200_MAX_PORT)
930 + return -EINVAL;
931 +
932 + link->link = xrx200sw_read_x(XRX200_MAC_PSTAT_LSTAT, port);
933 + if (!link->link)
934 + return 0;
935 +
936 + link->duplex = xrx200sw_read_x(XRX200_MAC_PSTAT_FDUP, port);
937 +
938 + link->rx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0010);
939 + link->tx_flow = !!(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port) && 0x0020);
940 + link->aneg = !(xrx200sw_read_x(XRX200_MAC_CTRL_0_FCON, port));
941 +
942 + link->speed = SWITCH_PORT_SPEED_10;
943 + if (xrx200sw_read_x(XRX200_MAC_PSTAT_MBIT, port))
944 + link->speed = SWITCH_PORT_SPEED_100;
945 + if (xrx200sw_read_x(XRX200_MAC_PSTAT_GBIT, port))
946 + link->speed = SWITCH_PORT_SPEED_1000;
947 +
948 + return 0;
949 +}
950 +
951 +static int xrx200sw_set_port_link(struct switch_dev *dev, int port,
952 + struct switch_port_link *link)
953 +{
954 + if (port >= XRX200_MAX_PORT)
955 + return -EINVAL;
956 +
957 + return switch_generic_set_link(dev, port, link);
958 +}
959 +
960 +static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val);
961 +static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg);
962 +
963 +static int xrx200sw_phy_read16(struct switch_dev *dev, int addr, u8 reg, u16 *value)
964 +{
965 + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
966 +
967 + *value = xrx200_mdio_rd(hw->mii_bus, hw->phy_addr[addr], reg);
968 +
969 + return 0;
970 +}
971 +
972 +static int xrx200sw_phy_write16(struct switch_dev *dev, int addr, u8 reg, u16 value)
973 +{
974 + struct xrx200_hw *hw = container_of(dev, struct xrx200_hw, swdev);
975 +
976 + return xrx200_mdio_wr(hw->mii_bus, hw->phy_addr[addr], reg, value);
977 +}
978 +
979 +static int xrx200_set_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
980 +{
981 + if (val->port_vlan >= XRX200_MAX_PORT)
982 + return -EINVAL;
983 +
984 + if ((attr->max > 0) && (val->value.i > attr->max))
985 + return -EINVAL;
986 +
987 + xrx200sw_write_x(val->value.i, attr->id, val->port_vlan);
988 + return 0;
989 +}
990 +
991 +static int xrx200_get_port_attr(struct switch_dev *dev, const struct switch_attr *attr, struct switch_val *val)
992 +{
993 + if (val->port_vlan >= XRX200_MAX_PORT)
994 + return -EINVAL;
995 +
996 + val->value.i = xrx200sw_read_x(attr->id, val->port_vlan);
997 + return 0;
998 +}
999 +
1000 +// attributes
1001 +static struct switch_attr xrx200sw_globals[] = {
1002 + {
1003 + .type = SWITCH_TYPE_INT,
1004 + .set = xrx200_set_vlan_mode_enable,
1005 + .get = xrx200_get_vlan_mode_enable,
1006 + .name = "enable_vlan",
1007 + .description = "Enable VLAN mode",
1008 + .max = 1},
1009 +};
1010 +
1011 +static struct switch_attr xrx200sw_port[] = {
1012 + {
1013 + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_UVR),
1014 + .name = "uvr",
1015 + .description = "Unknown VLAN Rule",
1016 + .max = 1,
1017 + },
1018 + {
1019 + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VSR),
1020 + .name = "vsr",
1021 + .description = "VLAN Security Rule",
1022 + .max = 1,
1023 + },
1024 + {
1025 + XRX200_PORT_REGATTR(XRX200_PCE_VCTRL_VINR),
1026 + .name = "vinr",
1027 + .description = "VLAN Ingress Tag Rule",
1028 + .max = 2,
1029 + },
1030 + {
1031 + XRX200_PORT_REGATTR(XRX200_PCE_PCTRL_0_TVM),
1032 + .name = "tvm",
1033 + .description = "Transparent VLAN Mode",
1034 + .max = 1,
1035 + },
1036 +};
1037 +
1038 +static struct switch_attr xrx200sw_vlan[] = {
1039 + {
1040 + .type = SWITCH_TYPE_INT,
1041 + .name = "vid",
1042 + .description = "VLAN ID (0-4094)",
1043 + .set = xrx200sw_set_vlan_vid,
1044 + .get = xrx200sw_get_vlan_vid,
1045 + .max = 4094,
1046 + },
1047 + {
1048 + .type = SWITCH_TYPE_INT,
1049 + .name = "enable",
1050 + .description = "Enable VLAN",
1051 + .set = xrx200sw_set_vlan_enable,
1052 + .get = xrx200sw_get_vlan_enable,
1053 + .max = 1,
1054 + },
1055 +};
1056 +
1057 +static const struct switch_dev_ops xrx200sw_ops = {
1058 + .attr_global = {
1059 + .attr = xrx200sw_globals,
1060 + .n_attr = ARRAY_SIZE(xrx200sw_globals),
1061 + },
1062 + .attr_port = {
1063 + .attr = xrx200sw_port,
1064 + .n_attr = ARRAY_SIZE(xrx200sw_port),
1065 + },
1066 + .attr_vlan = {
1067 + .attr = xrx200sw_vlan,
1068 + .n_attr = ARRAY_SIZE(xrx200sw_vlan),
1069 + },
1070 + .get_vlan_ports = xrx200sw_get_vlan_ports,
1071 + .set_vlan_ports = xrx200sw_set_vlan_ports,
1072 + .get_port_pvid = xrx200sw_get_port_pvid,
1073 + .reset_switch = xrx200sw_reset_switch,
1074 + .get_port_link = xrx200sw_get_port_link,
1075 + .set_port_link = xrx200sw_set_port_link,
1076 +// .get_port_stats = xrx200sw_get_port_stats, //TODO
1077 + .phy_read16 = xrx200sw_phy_read16,
1078 + .phy_write16 = xrx200sw_phy_write16,
1079 +};
1080 +
1081 +static int xrx200sw_init(struct xrx200_hw *hw)
1082 +{
1083 + int netdev_num;
1084 +
1085 + for (netdev_num = 0; netdev_num < hw->num_devs; netdev_num++)
1086 + {
1087 + struct switch_dev *swdev;
1088 + struct net_device *dev = hw->devs[netdev_num];
1089 + struct xrx200_priv *priv = netdev_priv(dev);
1090 + if (!priv->sw)
1091 + continue;
1092 +
1093 + swdev = &hw->swdev;
1094 +
1095 + swdev->name = "Lantiq XRX200 Switch";
1096 + swdev->vlans = XRX200_MAX_VLAN;
1097 + swdev->ports = XRX200_MAX_PORT;
1098 + swdev->cpu_port = 6;
1099 + swdev->ops = &xrx200sw_ops;
1100 +
1101 + register_switch(swdev, dev);
1102 + return 0; // enough switches
1103 + }
1104 + return 0;
1105 +}
1106 +
1107 +static int xrx200_open(struct net_device *dev)
1108 +{
1109 + struct xrx200_priv *priv = netdev_priv(dev);
1110 + int i;
1111 +
1112 + for (i = 0; i < XRX200_MAX_DMA; i++) {
1113 + if (!priv->hw->chan[i].dma.irq)
1114 + continue;
1115 + spin_lock_bh(&priv->hw->chan[i].lock);
1116 + if (!priv->hw->chan[i].refcount) {
1117 + if (XRX200_DMA_IS_RX(i))
1118 + napi_enable(&priv->hw->chan[i].napi);
1119 + ltq_dma_open(&priv->hw->chan[i].dma);
1120 + ltq_dma_enable_irq(&priv->hw->chan[i].dma);
1121 + }
1122 + priv->hw->chan[i].refcount++;
1123 + spin_unlock_bh(&priv->hw->chan[i].lock);
1124 + }
1125 + for (i = 0; i < priv->num_port; i++)
1126 + if (priv->port[i].phydev)
1127 + phy_start(priv->port[i].phydev);
1128 + netif_wake_queue(dev);
1129 +
1130 + return 0;
1131 +}
1132 +
1133 +static int xrx200_close(struct net_device *dev)
1134 +{
1135 + struct xrx200_priv *priv = netdev_priv(dev);
1136 + int i;
1137 +
1138 + netif_stop_queue(dev);
1139 +
1140 + for (i = 0; i < priv->num_port; i++)
1141 + if (priv->port[i].phydev)
1142 + phy_stop(priv->port[i].phydev);
1143 +
1144 + for (i = 0; i < XRX200_MAX_DMA; i++) {
1145 + if (!priv->hw->chan[i].dma.irq)
1146 + continue;
1147 +
1148 + priv->hw->chan[i].refcount--;
1149 + if (!priv->hw->chan[i].refcount) {
1150 + if (XRX200_DMA_IS_RX(i))
1151 + napi_disable(&priv->hw->chan[i].napi);
1152 + spin_lock_bh(&priv->hw->chan[i].lock);
1153 + ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma);
1154 + spin_unlock_bh(&priv->hw->chan[i].lock);
1155 + }
1156 + }
1157 +
1158 + return 0;
1159 +}
1160 +
1161 +static int xrx200_alloc_skb(struct xrx200_chan *ch)
1162 +{
1163 +#define DMA_PAD (NET_IP_ALIGN + NET_SKB_PAD)
1164 + ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD);
1165 + if (!ch->skb[ch->dma.desc])
1166 + goto skip;
1167 +
1168 + skb_reserve(ch->skb[ch->dma.desc], NET_SKB_PAD);
1169 + ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(ch->dma.dev,
1170 + ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
1171 + DMA_FROM_DEVICE);
1172 + ch->dma.desc_base[ch->dma.desc].addr =
1173 + CPHYSADDR(ch->skb[ch->dma.desc]->data);
1174 + skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
1175 +
1176 +skip:
1177 + ch->dma.desc_base[ch->dma.desc].ctl =
1178 + LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
1179 + XRX200_DMA_DATA_LEN;
1180 +
1181 + return 0;
1182 +}
1183 +
1184 +static void xrx200_hw_receive(struct xrx200_chan *ch, int id)
1185 +{
1186 + struct net_device *dev = ch->devs[id];
1187 + struct xrx200_priv *priv = netdev_priv(dev);
1188 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
1189 + struct sk_buff *skb = ch->skb[ch->dma.desc];
1190 + int len = (desc->ctl & LTQ_DMA_SIZE_MASK);
1191 + int ret;
1192 +
1193 + ret = xrx200_alloc_skb(ch);
1194 +
1195 + ch->dma.desc++;
1196 + ch->dma.desc %= LTQ_DESC_NUM;
1197 +
1198 + if (ret) {
1199 + netdev_err(dev,
1200 + "failed to allocate new rx buffer\n");
1201 + return;
1202 + }
1203 +
1204 + skb_put(skb, len);
1205 +#ifdef SW_ROUTING
1206 + skb_pull(skb, 8);
1207 +#endif
1208 + skb->dev = dev;
1209 + skb->protocol = eth_type_trans(skb, dev);
1210 + netif_receive_skb(skb);
1211 + priv->stats.rx_packets++;
1212 + priv->stats.rx_bytes+=len;
1213 +}
1214 +
1215 +static int xrx200_poll_rx(struct napi_struct *napi, int budget)
1216 +{
1217 + struct xrx200_chan *ch = container_of(napi,
1218 + struct xrx200_chan, napi);
1219 + struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
1220 + int rx = 0;
1221 + int complete = 0;
1222 +
1223 + while ((rx < budget) && !complete) {
1224 + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
1225 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
1226 +#ifdef SW_ROUTING
1227 + struct sk_buff *skb = ch->skb[ch->dma.desc];
1228 + u8 *special_tag = (u8*)skb->data;
1229 + int port = (special_tag[7] >> SPPID_SHIFT) & SPPID_MASK;
1230 + xrx200_hw_receive(ch, priv->hw->port_map[port]);
1231 +#else
1232 + xrx200_hw_receive(ch, 0);
1233 +#endif
1234 + rx++;
1235 + } else {
1236 + complete = 1;
1237 + }
1238 + }
1239 +
1240 + if (complete || !rx) {
1241 + napi_complete(&ch->napi);
1242 + ltq_dma_enable_irq(&ch->dma);
1243 + }
1244 +
1245 + return rx;
1246 +}
1247 +
1248 +static void xrx200_tx_housekeeping(unsigned long ptr)
1249 +{
1250 + struct xrx200_chan *ch = (struct xrx200_chan *) ptr;
1251 + int pkts = 0;
1252 + int i;
1253 +
1254 + spin_lock_bh(&ch->lock);
1255 + ltq_dma_ack_irq(&ch->dma);
1256 + while ((ch->dma.desc_base[ch->tx_free].ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
1257 + struct sk_buff *skb = ch->skb[ch->tx_free];
1258 +
1259 + pkts++;
1260 + ch->skb[ch->tx_free] = NULL;
1261 + dev_kfree_skb(skb);
1262 + memset(&ch->dma.desc_base[ch->tx_free], 0,
1263 + sizeof(struct ltq_dma_desc));
1264 + ch->tx_free++;
1265 + ch->tx_free %= LTQ_DESC_NUM;
1266 + }
1267 + ltq_dma_enable_irq(&ch->dma);
1268 + spin_unlock_bh(&ch->lock);
1269 +
1270 + if (!pkts)
1271 + return;
1272 +
1273 + for (i = 0; i < XRX200_MAX_DEV && ch->devs[i]; i++)
1274 + netif_wake_queue(ch->devs[i]);
1275 +}
1276 +
1277 +static struct net_device_stats *xrx200_get_stats (struct net_device *dev)
1278 +{
1279 + struct xrx200_priv *priv = netdev_priv(dev);
1280 +
1281 + return &priv->stats;
1282 +}
1283 +
1284 +static void xrx200_tx_timeout(struct net_device *dev)
1285 +{
1286 + struct xrx200_priv *priv = netdev_priv(dev);
1287 +
1288 + printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name);
1289 +
1290 + priv->stats.tx_errors++;
1291 + netif_wake_queue(dev);
1292 +}
1293 +
1294 +static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev)
1295 +{
1296 + struct xrx200_priv *priv = netdev_priv(dev);
1297 + struct xrx200_chan *ch;
1298 + struct ltq_dma_desc *desc;
1299 + u32 byte_offset;
1300 + int ret = NETDEV_TX_OK;
1301 + int len;
1302 +#ifdef SW_ROUTING
1303 + u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE;
1304 +#endif
1305 + if(priv->id)
1306 + ch = &priv->hw->chan[XRX200_DMA_TX_2];
1307 + else
1308 + ch = &priv->hw->chan[XRX200_DMA_TX];
1309 +
1310 + desc = &ch->dma.desc_base[ch->dma.desc];
1311 +
1312 + skb->dev = dev;
1313 + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
1314 +
1315 +#ifdef SW_ROUTING
1316 + if (is_multicast_ether_addr(eth_hdr(skb)->h_dest)) {
1317 + u16 port_map = priv->port_map;
1318 +
1319 + if (priv->sw && skb->protocol == htons(ETH_P_8021Q)) {
1320 + u16 vid;
1321 + int i;
1322 +
1323 + port_map = 0;
1324 + if (!__vlan_get_tag(skb, &vid)) {
1325 + for (i = 0; i < XRX200_MAX_VLAN; i++) {
1326 + if (priv->hw->vlan_vid[i] != vid)
1327 + continue;
1328 + port_map = priv->hw->vlan_port_map[i];
1329 + break;
1330 + }
1331 + }
1332 + }
1333 +
1334 + special_tag |= (port_map << PORT_MAP_SHIFT) |
1335 + PORT_MAP_SEL | PORT_MAP_EN;
1336 + }
1337 + if(priv->wan)
1338 + special_tag |= (1 << DPID_SHIFT);
1339 + if(skb_headroom(skb) < 4) {
1340 + struct sk_buff *tmp = skb_realloc_headroom(skb, 4);
1341 + dev_kfree_skb_any(skb);
1342 + skb = tmp;
1343 + }
1344 + skb_push(skb, 4);
1345 + memcpy(skb->data, &special_tag, sizeof(u32));
1346 + len += 4;
1347 +#endif
1348 +
1349 + /* dma needs to start on a 16 byte aligned address */
1350 + byte_offset = CPHYSADDR(skb->data) % 16;
1351 +
1352 + spin_lock_bh(&ch->lock);
1353 + if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
1354 + netdev_err(dev, "tx ring full\n");
1355 + netif_stop_queue(dev);
1356 + ret = NETDEV_TX_BUSY;
1357 + goto out;
1358 + }
1359 +
1360 + ch->skb[ch->dma.desc] = skb;
1361 +
1362 + netif_trans_update(dev);
1363 +
1364 + desc->addr = ((unsigned int) dma_map_single(ch->dma.dev, skb->data, len,
1365 + DMA_TO_DEVICE)) - byte_offset;
1366 + wmb();
1367 + desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
1368 + LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
1369 + ch->dma.desc++;
1370 + ch->dma.desc %= LTQ_DESC_NUM;
1371 + if (ch->dma.desc == ch->tx_free)
1372 + netif_stop_queue(dev);
1373 +
1374 +
1375 + priv->stats.tx_packets++;
1376 + priv->stats.tx_bytes+=len;
1377 +
1378 +out:
1379 + spin_unlock_bh(&ch->lock);
1380 +
1381 + return ret;
1382 +}
1383 +
1384 +static irqreturn_t xrx200_dma_irq(int irq, void *priv)
1385 +{
1386 + struct xrx200_hw *hw = priv;
1387 + int chnr = irq - XRX200_DMA_IRQ;
1388 + struct xrx200_chan *ch = &hw->chan[chnr];
1389 +
1390 + ltq_dma_disable_irq(&ch->dma);
1391 + ltq_dma_ack_irq(&ch->dma);
1392 +
1393 + if (chnr % 2)
1394 + tasklet_schedule(&ch->tasklet);
1395 + else
1396 + napi_schedule(&ch->napi);
1397 +
1398 + return IRQ_HANDLED;
1399 +}
1400 +
1401 +static int xrx200_dma_init(struct device *dev, struct xrx200_hw *hw)
1402 +{
1403 + int i, err = 0;
1404 +
1405 + ltq_dma_init_port(DMA_PORT_ETOP);
1406 +
1407 + for (i = 0; i < 8 && !err; i++) {
1408 + int irq = XRX200_DMA_IRQ + i;
1409 + struct xrx200_chan *ch = &hw->chan[i];
1410 +
1411 + spin_lock_init(&ch->lock);
1412 +
1413 + ch->idx = ch->dma.nr = i;
1414 + ch->dma.dev = dev;
1415 +
1416 + if (i == XRX200_DMA_TX) {
1417 + ltq_dma_alloc_tx(&ch->dma);
1418 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw);
1419 + } else if (i == XRX200_DMA_TX_2) {
1420 + ltq_dma_alloc_tx(&ch->dma);
1421 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx_2", hw);
1422 + } else if (i == XRX200_DMA_RX) {
1423 + ltq_dma_alloc_rx(&ch->dma);
1424 + for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
1425 + ch->dma.desc++)
1426 + if (xrx200_alloc_skb(ch))
1427 + err = -ENOMEM;
1428 + ch->dma.desc = 0;
1429 + err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw);
1430 + } else
1431 + continue;
1432 +
1433 + if (!err)
1434 + ch->dma.irq = irq;
1435 + else
1436 + pr_err("net-xrx200: failed to request irq %d\n", irq);
1437 + }
1438 +
1439 + return err;
1440 +}
1441 +
1442 +#ifdef SW_POLLING
1443 +static void xrx200_gmac_update(struct xrx200_port *port)
1444 +{
1445 + u16 phyaddr = port->phydev->mdio.addr & MDIO_PHY_ADDR_MASK;
1446 + u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK;
1447 + u16 miirate = 0;
1448 +
1449 + switch (port->phydev->speed) {
1450 + case SPEED_1000:
1451 + phyaddr |= MDIO_PHY_SPEED_G1;
1452 + miirate = MII_CFG_RATE_M125;
1453 + break;
1454 +
1455 + case SPEED_100:
1456 + phyaddr |= MDIO_PHY_SPEED_M100;
1457 + switch (miimode) {
1458 + case MII_CFG_MODE_RMIIM:
1459 + case MII_CFG_MODE_RMIIP:
1460 + miirate = MII_CFG_RATE_M50;
1461 + break;
1462 + default:
1463 + miirate = MII_CFG_RATE_M25;
1464 + break;
1465 + }
1466 + break;
1467 +
1468 + default:
1469 + phyaddr |= MDIO_PHY_SPEED_M10;
1470 + miirate = MII_CFG_RATE_M2P5;
1471 + break;
1472 + }
1473 +
1474 + if (port->phydev->link)
1475 + phyaddr |= MDIO_PHY_LINK_UP;
1476 + else
1477 + phyaddr |= MDIO_PHY_LINK_DOWN;
1478 +
1479 + if (port->phydev->duplex == DUPLEX_FULL)
1480 + phyaddr |= MDIO_PHY_FDUP_EN;
1481 + else
1482 + phyaddr |= MDIO_PHY_FDUP_DIS;
1483 +
1484 + ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num));
1485 + ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num));
1486 + udelay(1);
1487 +}
1488 +#else
1489 +static void xrx200_gmac_update(struct xrx200_port *port)
1490 +{
1491 +
1492 +}
1493 +#endif
1494 +
1495 +static void xrx200_mdio_link(struct net_device *dev)
1496 +{
1497 + struct xrx200_priv *priv = netdev_priv(dev);
1498 + int i;
1499 +
1500 + for (i = 0; i < priv->num_port; i++) {
1501 + if (!priv->port[i].phydev)
1502 + continue;
1503 +
1504 + if (priv->port[i].link != priv->port[i].phydev->link) {
1505 + xrx200_gmac_update(&priv->port[i]);
1506 + priv->port[i].link = priv->port[i].phydev->link;
1507 + netdev_info(dev, "port %d %s link\n",
1508 + priv->port[i].num,
1509 + (priv->port[i].link)?("got"):("lost"));
1510 + }
1511 + }
1512 +}
1513 +
1514 +static inline int xrx200_mdio_poll(struct mii_bus *bus)
1515 +{
1516 + unsigned cnt = 10000;
1517 +
1518 + while (likely(cnt--)) {
1519 + unsigned ctrl = ltq_mdio_r32(MDIO_CTRL);
1520 + if ((ctrl & MDIO_BUSY) == 0)
1521 + return 0;
1522 + }
1523 +
1524 + return 1;
1525 +}
1526 +
1527 +static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
1528 +{
1529 + if (xrx200_mdio_poll(bus))
1530 + return 1;
1531 +
1532 + ltq_mdio_w32(val, MDIO_WRITE);
1533 + ltq_mdio_w32(MDIO_BUSY | MDIO_WR |
1534 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
1535 + (reg & MDIO_MASK),
1536 + MDIO_CTRL);
1537 +
1538 + return 0;
1539 +}
1540 +
1541 +static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg)
1542 +{
1543 + if (xrx200_mdio_poll(bus))
1544 + return -1;
1545 +
1546 + ltq_mdio_w32(MDIO_BUSY | MDIO_RD |
1547 + ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
1548 + (reg & MDIO_MASK),
1549 + MDIO_CTRL);
1550 +
1551 + if (xrx200_mdio_poll(bus))
1552 + return -1;
1553 +
1554 + return ltq_mdio_r32(MDIO_READ);
1555 +}
1556 +
1557 +static int xrx200_phy_has_link(struct net_device *dev)
1558 +{
1559 + struct xrx200_priv *priv = netdev_priv(dev);
1560 + int i;
1561 +
1562 + for (i = 0; i < priv->num_port; i++) {
1563 + if (!priv->port[i].phydev)
1564 + continue;
1565 +
1566 + if (priv->port[i].phydev->link)
1567 + return 1;
1568 + }
1569 +
1570 + return 0;
1571 +}
1572 +
1573 +static void xrx200_phy_link_change(struct phy_device *phydev, bool up, bool do_carrier)
1574 +{
1575 + struct net_device *netdev = phydev->attached_dev;
1576 +
1577 + if (do_carrier) {
1578 + if (up)
1579 + netif_carrier_on(netdev);
1580 + else if (!xrx200_phy_has_link(netdev))
1581 + netif_carrier_off(netdev);
1582 + }
1583 +
1584 + phydev->adjust_link(netdev);
1585 +}
1586 +
1587 +static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port)
1588 +{
1589 + struct xrx200_priv *priv = netdev_priv(dev);
1590 + struct phy_device *phydev = NULL;
1591 + unsigned val;
1592 +
1593 + phydev = mdiobus_get_phy(priv->hw->mii_bus, port->phy_addr);
1594 +
1595 + if (!phydev) {
1596 + netdev_err(dev, "no PHY found\n");
1597 + return -ENODEV;
1598 + }
1599 +
1600 + phydev = phy_connect(dev, phydev_name(phydev), &xrx200_mdio_link,
1601 + port->phy_if);
1602 +
1603 + if (IS_ERR(phydev)) {
1604 + netdev_err(dev, "Could not attach to PHY\n");
1605 + return PTR_ERR(phydev);
1606 + }
1607 +
1608 + linkmode_zero(phydev->supported);
1609 + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
1610 + linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, phydev->supported);
1611 + linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, phydev->supported);
1612 + linkmode_set_bit_array(phy_10_100_features_array,
1613 + ARRAY_SIZE(phy_10_100_features_array),
1614 + phydev->supported);
1615 + linkmode_set_bit_array(phy_gbit_features_array,
1616 + ARRAY_SIZE(phy_gbit_features_array),
1617 + phydev->supported);
1618 + linkmode_copy(phydev->advertising, phydev->supported);
1619 +
1620 + port->phydev = phydev;
1621 + phydev->phy_link_change = xrx200_phy_link_change;
1622 +
1623 + phy_attached_info(phydev);
1624 +
1625 +#ifdef SW_POLLING
1626 + phy_read_status(phydev);
1627 +
1628 + val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
1629 + val |= ADVERTIZE_MPD;
1630 + xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
1631 + xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040);
1632 +
1633 + phy_start_aneg(phydev);
1634 +#endif
1635 + return 0;
1636 +}
1637 +
1638 +static void xrx200_port_config(struct xrx200_priv *priv,
1639 + const struct xrx200_port *port)
1640 +{
1641 + u16 miimode = 0;
1642 +
1643 + switch (port->num) {
1644 + case 0: /* xMII0 */
1645 + case 1: /* xMII1 */
1646 + switch (port->phy_if) {
1647 + case PHY_INTERFACE_MODE_MII:
1648 + if (port->flags & XRX200_PORT_TYPE_PHY)
1649 + /* MII MAC mode, connected to external PHY */
1650 + miimode = MII_CFG_MODE_MIIM;
1651 + else
1652 + /* MII PHY mode, connected to external MAC */
1653 + miimode = MII_CFG_MODE_MIIP;
1654 + break;
1655 + case PHY_INTERFACE_MODE_RMII:
1656 + if (port->flags & XRX200_PORT_TYPE_PHY)
1657 + /* RMII MAC mode, connected to external PHY */
1658 + miimode = MII_CFG_MODE_RMIIM;
1659 + else
1660 + /* RMII PHY mode, connected to external MAC */
1661 + miimode = MII_CFG_MODE_RMIIP;
1662 + break;
1663 + case PHY_INTERFACE_MODE_RGMII:
1664 + /* RGMII MAC mode, connected to external PHY */
1665 + miimode = MII_CFG_MODE_RGMII;
1666 + break;
1667 + default:
1668 + break;
1669 + }
1670 + break;
1671 + case 2: /* internal GPHY0 */
1672 + case 3: /* internal GPHY0 */
1673 + case 4: /* internal GPHY1 */
1674 + switch (port->phy_if) {
1675 + case PHY_INTERFACE_MODE_MII:
1676 + case PHY_INTERFACE_MODE_GMII:
1677 + /* MII MAC mode, connected to internal GPHY */
1678 + miimode = MII_CFG_MODE_MIIM;
1679 + break;
1680 + default:
1681 + break;
1682 + }
1683 + break;
1684 + case 5: /* internal GPHY1 or xMII2 */
1685 + switch (port->phy_if) {
1686 + case PHY_INTERFACE_MODE_MII:
1687 + /* MII MAC mode, connected to internal GPHY */
1688 + miimode = MII_CFG_MODE_MIIM;
1689 + break;
1690 + case PHY_INTERFACE_MODE_RGMII:
1691 + /* RGMII MAC mode, connected to external PHY */
1692 + miimode = MII_CFG_MODE_RGMII;
1693 + break;
1694 + default:
1695 + break;
1696 + }
1697 + break;
1698 + default:
1699 + break;
1700 + }
1701 +
1702 + ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN,
1703 + MII_CFG(port->num));
1704 +}
1705 +
1706 +static int xrx200_init(struct net_device *dev)
1707 +{
1708 + struct xrx200_priv *priv = netdev_priv(dev);
1709 + struct sockaddr mac;
1710 + int err, i;
1711 +
1712 +#ifndef SW_POLLING
1713 + unsigned int reg = 0;
1714 +
1715 + /* enable auto polling */
1716 + for (i = 0; i < priv->num_port; i++)
1717 + reg |= BIT(priv->port[i].num);
1718 + ltq_mdio_w32(reg, MDIO_CLK_CFG0);
1719 + ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1);
1720 +#endif
1721 +
1722 + /* setup each port */
1723 + for (i = 0; i < priv->num_port; i++)
1724 + xrx200_port_config(priv, &priv->port[i]);
1725 +
1726 + memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
1727 + if (!is_valid_ether_addr(mac.sa_data)) {
1728 + pr_warn("net-xrx200: invalid MAC, using random\n");
1729 + eth_random_addr(mac.sa_data);
1730 + dev->addr_assign_type |= NET_ADDR_RANDOM;
1731 + }
1732 +
1733 + err = eth_mac_addr(dev, &mac);
1734 + if (err)
1735 + goto err_netdev;
1736 +
1737 + for (i = 0; i < priv->num_port; i++)
1738 + if (xrx200_mdio_probe(dev, &priv->port[i]))
1739 + pr_warn("xrx200-mdio: probing phy of port %d failed\n",
1740 + priv->port[i].num);
1741 +
1742 + return 0;
1743 +
1744 +err_netdev:
1745 + unregister_netdev(dev);
1746 + free_netdev(dev);
1747 + return err;
1748 +}
1749 +
1750 +static void xrx200_pci_microcode(void)
1751 +{
1752 + int i;
1753 +
1754 + ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK,
1755 + PCE_TBL_CFG_ADWR, PCE_TBL_CTRL);
1756 + ltq_switch_w32(0, PCE_TBL_MASK);
1757 +
1758 + for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) {
1759 + ltq_switch_w32(i, PCE_TBL_ADDR);
1760 + ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0));
1761 + ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1));
1762 + ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2));
1763 + ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3));
1764 +
1765 + // start the table access:
1766 + ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL);
1767 + while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY);
1768 + }
1769 +
1770 + /* tell the switch that the microcode is loaded */
1771 + ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0));
1772 +}
1773 +
1774 +static void xrx200_hw_init(struct xrx200_hw *hw)
1775 +{
1776 + int i;
1777 +
1778 + /* enable clock gate */
1779 + clk_enable(hw->clk);
1780 +
1781 + ltq_switch_w32(1, 0);
1782 + mdelay(100);
1783 + ltq_switch_w32(0, 0);
1784 + /*
1785 + * TODO: we should really disbale all phys/miis here and explicitly
1786 + * enable them in the device secific init function
1787 + */
1788 +
1789 + /* disable port fetch/store dma */
1790 + for (i = 0; i < 7; i++ ) {
1791 + ltq_switch_w32(0, FDMA_PCTRLx(i));
1792 + ltq_switch_w32(0, SDMA_PCTRLx(i));
1793 + }
1794 +
1795 + /* enable Switch */
1796 + ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB);
1797 +
1798 + /* load the pce microcode */
1799 + xrx200_pci_microcode();
1800 +
1801 + /* Default unknown Broadcat/Multicast/Unicast port maps */
1802 + ltq_switch_w32(0x40, PCE_PMAP1);
1803 + ltq_switch_w32(0x40, PCE_PMAP2);
1804 + ltq_switch_w32(0x40, PCE_PMAP3);
1805 +
1806 + /* RMON Counter Enable for all physical ports */
1807 + for (i = 0; i < 7; i++)
1808 + ltq_switch_w32(0x1, BM_PCFG(i));
1809 +
1810 + /* disable auto polling */
1811 + ltq_mdio_w32(0x0, MDIO_CLK_CFG0);
1812 +
1813 + /* enable port statistic counters */
1814 + for (i = 0; i < 7; i++)
1815 + ltq_switch_w32(0x1, BM_PCFGx(i));
1816 +
1817 + /* set IPG to 12 */
1818 + ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG);
1819 +
1820 +#ifdef SW_ROUTING
1821 + /* enable status header, enable CRC */
1822 + ltq_pmac_w32_mask(0,
1823 + PMAC_HD_CTL_RST | PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC | PMAC_HD_CTL_RC,
1824 + PMAC_HD_CTL);
1825 +#else
1826 + /* disable status header, enable CRC */
1827 + ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS,
1828 + PMAC_HD_CTL_AC | PMAC_HD_CTL_RC,
1829 + PMAC_HD_CTL);
1830 +#endif
1831 +
1832 + /* enable port fetch/store dma & VLAN Modification */
1833 + for (i = 0; i < 7; i++ ) {
1834 + ltq_switch_w32_mask(0, 0x19, FDMA_PCTRLx(i));
1835 + ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i));
1836 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0));
1837 + }
1838 +
1839 + /* enable special tag insertion on cpu port */
1840 + ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6));
1841 + ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(6, 0));
1842 + ltq_switch_w32_mask(0, BIT(3), MAC_CTRL_REG(6, 2));
1843 + ltq_switch_w32(1518 + 8 + 4 * 2, MAC_FLEN_REG);
1844 + xrx200sw_write_x(1, XRX200_BM_QUEUE_GCTRL_GL_MOD, 0);
1845 +
1846 + for (i = 0; i < XRX200_MAX_VLAN; i++)
1847 + hw->vlan_vid[i] = i;
1848 +}
1849 +
1850 +static void xrx200_hw_cleanup(struct xrx200_hw *hw)
1851 +{
1852 + int i;
1853 +
1854 + /* disable the switch */
1855 + ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB);
1856 +
1857 + /* free the channels and IRQs */
1858 + for (i = 0; i < 2; i++) {
1859 + ltq_dma_free(&hw->chan[i].dma);
1860 + if (hw->chan[i].dma.irq)
1861 + free_irq(hw->chan[i].dma.irq, hw);
1862 + }
1863 +
1864 + /* free the allocated RX ring */
1865 + for (i = 0; i < LTQ_DESC_NUM; i++)
1866 + dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]);
1867 +
1868 + /* clear the mdio bus */
1869 + mdiobus_unregister(hw->mii_bus);
1870 + mdiobus_free(hw->mii_bus);
1871 +
1872 + /* release the clock */
1873 + clk_disable(hw->clk);
1874 + clk_put(hw->clk);
1875 +}
1876 +
1877 +static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np)
1878 +{
1879 + hw->mii_bus = mdiobus_alloc();
1880 + if (!hw->mii_bus)
1881 + return -ENOMEM;
1882 +
1883 + hw->mii_bus->read = xrx200_mdio_rd;
1884 + hw->mii_bus->write = xrx200_mdio_wr;
1885 + hw->mii_bus->name = "lantiq,xrx200-mdio";
1886 + snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
1887 +
1888 + if (of_mdiobus_register(hw->mii_bus, np)) {
1889 + mdiobus_free(hw->mii_bus);
1890 + return -ENXIO;
1891 + }
1892 +
1893 + return 0;
1894 +}
1895 +
1896 +static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port)
1897 +{
1898 + const __be32 *addr, *id = of_get_property(port, "reg", NULL);
1899 + struct xrx200_port *p = &priv->port[priv->num_port];
1900 +
1901 + if (!id)
1902 + return;
1903 +
1904 + memset(p, 0, sizeof(struct xrx200_port));
1905 + p->phy_node = of_parse_phandle(port, "phy-handle", 0);
1906 + addr = of_get_property(p->phy_node, "reg", NULL);
1907 + if (!addr)
1908 + return;
1909 +
1910 + p->num = *id;
1911 + p->phy_addr = *addr;
1912 + p->phy_if = of_get_phy_mode(port);
1913 + if (p->phy_addr > 0x10)
1914 + p->flags = XRX200_PORT_TYPE_MAC;
1915 + else
1916 + p->flags = XRX200_PORT_TYPE_PHY;
1917 + priv->num_port++;
1918 +
1919 + p->gpio = of_get_gpio_flags(port, 0, &p->gpio_flags);
1920 + if (gpio_is_valid(p->gpio))
1921 + if (!gpio_request(p->gpio, "phy-reset")) {
1922 + gpio_direction_output(p->gpio,
1923 + (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (1) : (0));
1924 + udelay(100);
1925 + gpio_set_value(p->gpio, (p->gpio_flags & OF_GPIO_ACTIVE_LOW) ? (0) : (1));
1926 + }
1927 + /* is this port a wan port ? */
1928 + if (priv->wan)
1929 + priv->hw->wan_map |= BIT(p->num);
1930 +
1931 + priv->port_map |= BIT(p->num);
1932 +
1933 + /* store the port id in the hw struct so we can map ports -> devices */
1934 + priv->hw->port_map[p->num] = priv->hw->num_devs;
1935 +
1936 + /* store the phy addr in the hw struct so we can map ports -> phys */
1937 + priv->hw->phy_addr[p->num] = p->phy_addr;
1938 +}
1939 +
1940 +static const struct net_device_ops xrx200_netdev_ops = {
1941 + .ndo_init = xrx200_init,
1942 + .ndo_open = xrx200_open,
1943 + .ndo_stop = xrx200_close,
1944 + .ndo_start_xmit = xrx200_start_xmit,
1945 + .ndo_set_mac_address = eth_mac_addr,
1946 + .ndo_validate_addr = eth_validate_addr,
1947 + .ndo_get_stats = xrx200_get_stats,
1948 + .ndo_tx_timeout = xrx200_tx_timeout,
1949 +};
1950 +
1951 +static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface, struct device *dev)
1952 +{
1953 + struct xrx200_priv *priv;
1954 + struct device_node *port;
1955 + const __be32 *wan;
1956 + const u8 *mac;
1957 +
1958 + /* alloc the network device */
1959 + hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv));
1960 + if (!hw->devs[hw->num_devs])
1961 + return;
1962 +
1963 + /* setup the network device */
1964 + strcpy(hw->devs[hw->num_devs]->name, "eth%d");
1965 + hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops;
1966 + hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT;
1967 + hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM;
1968 + SET_NETDEV_DEV(hw->devs[hw->num_devs], dev);
1969 +
1970 + /* setup our private data */
1971 + priv = netdev_priv(hw->devs[hw->num_devs]);
1972 + priv->hw = hw;
1973 + priv->id = hw->num_devs;
1974 +
1975 + mac = of_get_mac_address(iface);
1976 + if (!IS_ERR(mac))
1977 + memcpy(priv->mac, mac, ETH_ALEN);
1978 +
1979 + /* is this the wan interface ? */
1980 + wan = of_get_property(iface, "lantiq,wan", NULL);
1981 + if (wan && (*wan == 1))
1982 + priv->wan = 1;
1983 +
1984 + /* should the switch be enabled on this interface ? */
1985 + if (of_find_property(iface, "lantiq,switch", NULL))
1986 + priv->sw = 1;
1987 +
1988 + /* load the ports that are part of the interface */
1989 + for_each_child_of_node(iface, port)
1990 + if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port"))
1991 + xrx200_of_port(priv, port);
1992 +
1993 + /* register the actual device */
1994 + if (!register_netdev(hw->devs[hw->num_devs]))
1995 + hw->num_devs++;
1996 +}
1997 +
1998 +static struct xrx200_hw xrx200_hw;
1999 +
2000 +static int xrx200_probe(struct platform_device *pdev)
2001 +{
2002 + struct resource *res[4];
2003 + struct device_node *mdio_np, *iface_np, *phy_np;
2004 + struct of_phandle_iterator it;
2005 + int err;
2006 + int i;
2007 +
2008 + /* load the memory ranges */
2009 + for (i = 0; i < 4; i++) {
2010 + res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
2011 + if (!res[i]) {
2012 + dev_err(&pdev->dev, "failed to get resources\n");
2013 + return -ENOENT;
2014 + }
2015 + }
2016 + xrx200_switch_membase = devm_ioremap_resource(&pdev->dev, res[0]);
2017 + xrx200_mdio_membase = devm_ioremap_resource(&pdev->dev, res[1]);
2018 + xrx200_mii_membase = devm_ioremap_resource(&pdev->dev, res[2]);
2019 + xrx200_pmac_membase = devm_ioremap_resource(&pdev->dev, res[3]);
2020 + if (!xrx200_switch_membase || !xrx200_mdio_membase ||
2021 + !xrx200_mii_membase || !xrx200_pmac_membase) {
2022 + dev_err(&pdev->dev, "failed to request and remap io ranges \n");
2023 + return -ENOMEM;
2024 + }
2025 +
2026 + of_for_each_phandle(&it, err, pdev->dev.of_node, "lantiq,phys", NULL, 0) {
2027 + phy_np = it.node;
2028 + if (phy_np) {
2029 + struct platform_device *phy = of_find_device_by_node(phy_np);
2030 +
2031 + of_node_put(phy_np);
2032 + if (!platform_get_drvdata(phy))
2033 + return -EPROBE_DEFER;
2034 + }
2035 + }
2036 +
2037 + /* get the clock */
2038 + xrx200_hw.clk = clk_get(&pdev->dev, NULL);
2039 + if (IS_ERR(xrx200_hw.clk)) {
2040 + dev_err(&pdev->dev, "failed to get clock\n");
2041 + return PTR_ERR(xrx200_hw.clk);
2042 + }
2043 +
2044 + /* bring up the dma engine and IP core */
2045 + xrx200_dma_init(&pdev->dev, &xrx200_hw);
2046 + xrx200_hw_init(&xrx200_hw);
2047 + tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX]);
2048 + tasklet_init(&xrx200_hw.chan[XRX200_DMA_TX_2].tasklet, xrx200_tx_housekeeping, (u32) &xrx200_hw.chan[XRX200_DMA_TX_2]);
2049 +
2050 + /* bring up the mdio bus */
2051 + mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL,
2052 + "lantiq,xrx200-mdio");
2053 + if (mdio_np)
2054 + if (xrx200_of_mdio(&xrx200_hw, mdio_np))
2055 + dev_err(&pdev->dev, "mdio probe failed\n");
2056 +
2057 + /* load the interfaces */
2058 + for_each_child_of_node(pdev->dev.of_node, iface_np)
2059 + if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) {
2060 + if (xrx200_hw.num_devs < XRX200_MAX_DEV)
2061 + xrx200_of_iface(&xrx200_hw, iface_np, &pdev->dev);
2062 + else
2063 + dev_err(&pdev->dev,
2064 + "only %d interfaces allowed\n",
2065 + XRX200_MAX_DEV);
2066 + }
2067 +
2068 + if (!xrx200_hw.num_devs) {
2069 + xrx200_hw_cleanup(&xrx200_hw);
2070 + dev_err(&pdev->dev, "failed to load interfaces\n");
2071 + return -ENOENT;
2072 + }
2073 +
2074 + xrx200sw_init(&xrx200_hw);
2075 +
2076 + /* set wan port mask */
2077 + ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN);
2078 +
2079 + for (i = 0; i < xrx200_hw.num_devs; i++) {
2080 + xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i];
2081 + xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i];
2082 + xrx200_hw.chan[XRX200_DMA_TX_2].devs[i] = xrx200_hw.devs[i];
2083 + }
2084 +
2085 + /* setup NAPI */
2086 + init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev);
2087 + netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev,
2088 + &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32);
2089 +
2090 + platform_set_drvdata(pdev, &xrx200_hw);
2091 +
2092 + return 0;
2093 +}
2094 +
2095 +static int xrx200_remove(struct platform_device *pdev)
2096 +{
2097 + struct net_device *dev = platform_get_drvdata(pdev);
2098 + struct xrx200_priv *priv;
2099 +
2100 + if (!dev)
2101 + return 0;
2102 +
2103 + priv = netdev_priv(dev);
2104 +
2105 + /* free stack related instances */
2106 + netif_stop_queue(dev);
2107 + netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi);
2108 +
2109 + /* shut down hardware */
2110 + xrx200_hw_cleanup(&xrx200_hw);
2111 +
2112 + /* remove the actual device */
2113 + unregister_netdev(dev);
2114 + free_netdev(dev);
2115 +
2116 + return 0;
2117 +}
2118 +
2119 +static const struct of_device_id xrx200_match[] = {
2120 + { .compatible = "lantiq,xrx200-net" },
2121 + {},
2122 +};
2123 +MODULE_DEVICE_TABLE(of, xrx200_match);
2124 +
2125 +static struct platform_driver xrx200_driver = {
2126 + .probe = xrx200_probe,
2127 + .remove = xrx200_remove,
2128 + .driver = {
2129 + .name = "lantiq,xrx200-net",
2130 + .of_match_table = xrx200_match,
2131 + .owner = THIS_MODULE,
2132 + },
2133 +};
2134 +
2135 +module_platform_driver(xrx200_driver);
2136 +
2137 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2138 +MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
2139 +MODULE_LICENSE("GPL");
2140 --- /dev/null
2141 +++ b/drivers/net/ethernet/lantiq_xrx200_legacy.h
2142 @@ -0,0 +1,1328 @@
2143 +/*
2144 + * This program is free software; you can redistribute it and/or modify it
2145 + * under the terms of the GNU General Public License version 2 as published
2146 + * by the Free Software Foundation.
2147 + *
2148 + * This program is distributed in the hope that it will be useful,
2149 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2150 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2151 + * GNU General Public License for more details.
2152 + *
2153 + * You should have received a copy of the GNU General Public License
2154 + * along with this program; if not, write to the Free Software
2155 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
2156 + *
2157 + * Copyright (C) 2010 Lantiq Deutschland GmbH
2158 + * Copyright (C) 2013 Antonios Vamporakis <vamporakis@yahoo.com>
2159 + *
2160 + * VR9 switch registers extracted from 310TUJ0 switch api
2161 + * WARNING mult values of 0x00 may not be correct
2162 + *
2163 + */
2164 +
2165 +enum {
2166 +// XRX200_ETHSW_SWRES, /* Ethernet Switch ResetControl Register */
2167 +// XRX200_ETHSW_SWRES_R1, /* Hardware Reset */
2168 +// XRX200_ETHSW_SWRES_R0, /* Register Configuration */
2169 +// XRX200_ETHSW_CLK_MAC_GAT, /* Ethernet Switch Clock ControlRegister */
2170 +// XRX200_ETHSW_CLK_EXP_SLEEP, /* Exponent to put system into sleep */
2171 +// XRX200_ETHSW_CLK_EXP_WAKE, /* Exponent to wake up system */
2172 +// XRX200_ETHSW_CLK_CLK2_EN, /* CLK2 Input for MAC */
2173 +// XRX200_ETHSW_CLK_EXT_DIV_EN, /* External Clock Divider Enable */
2174 +// XRX200_ETHSW_CLK_RAM_DBG_EN, /* Clock Gating Enable */
2175 +// XRX200_ETHSW_CLK_REG_GAT_EN, /* Clock Gating Enable */
2176 +// XRX200_ETHSW_CLK_GAT_EN, /* Clock Gating Enable */
2177 +// XRX200_ETHSW_CLK_MAC_GAT_EN, /* Clock Gating Enable */
2178 +// XRX200_ETHSW_DBG_STEP, /* Ethernet Switch Debug ControlRegister */
2179 +// XRX200_ETHSW_DBG_CLK_SEL, /* Trigger Enable */
2180 +// XRX200_ETHSW_DBG_MON_EN, /* Monitoring Enable */
2181 +// XRX200_ETHSW_DBG_TRIG_EN, /* Trigger Enable */
2182 +// XRX200_ETHSW_DBG_MODE, /* Debug Mode */
2183 +// XRX200_ETHSW_DBG_STEP_TIME, /* Clock Step Size */
2184 +// XRX200_ETHSW_SSB_MODE, /* Ethernet Switch SharedSegment Buffer Mode Register */
2185 +// XRX200_ETHSW_SSB_MODE_ADDE, /* Memory Address */
2186 +// XRX200_ETHSW_SSB_MODE_MODE, /* Memory Access Mode */
2187 +// XRX200_ETHSW_SSB_ADDR, /* Ethernet Switch SharedSegment Buffer Address Register */
2188 +// XRX200_ETHSW_SSB_ADDR_ADDE, /* Memory Address */
2189 +// XRX200_ETHSW_SSB_DATA, /* Ethernet Switch SharedSegment Buffer Data Register */
2190 +// XRX200_ETHSW_SSB_DATA_DATA, /* Data Value */
2191 +// XRX200_ETHSW_CAP_0, /* Ethernet Switch CapabilityRegister 0 */
2192 +// XRX200_ETHSW_CAP_0_SPEED, /* Clock frequency */
2193 +// XRX200_ETHSW_CAP_1, /* Ethernet Switch CapabilityRegister 1 */
2194 +// XRX200_ETHSW_CAP_1_GMAC, /* MAC operation mode */
2195 +// XRX200_ETHSW_CAP_1_QUEUE, /* Number of queues */
2196 +// XRX200_ETHSW_CAP_1_VPORTS, /* Number of virtual ports */
2197 +// XRX200_ETHSW_CAP_1_PPORTS, /* Number of physical ports */
2198 +// XRX200_ETHSW_CAP_2, /* Ethernet Switch CapabilityRegister 2 */
2199 +// XRX200_ETHSW_CAP_2_PACKETS, /* Number of packets */
2200 +// XRX200_ETHSW_CAP_3, /* Ethernet Switch CapabilityRegister 3 */
2201 +// XRX200_ETHSW_CAP_3_METERS, /* Number of traffic meters */
2202 +// XRX200_ETHSW_CAP_3_SHAPERS, /* Number of traffic shapers */
2203 +// XRX200_ETHSW_CAP_4, /* Ethernet Switch CapabilityRegister 4 */
2204 +// XRX200_ETHSW_CAP_4_PPPOE, /* PPPoE table size */
2205 +// XRX200_ETHSW_CAP_4_VLAN, /* Active VLAN table size */
2206 +// XRX200_ETHSW_CAP_5, /* Ethernet Switch CapabilityRegister 5 */
2207 +// XRX200_ETHSW_CAP_5_IPPLEN, /* IP packet length table size */
2208 +// XRX200_ETHSW_CAP_5_PROT, /* Protocol table size */
2209 +// XRX200_ETHSW_CAP_6, /* Ethernet Switch CapabilityRegister 6 */
2210 +// XRX200_ETHSW_CAP_6_MACDASA, /* MAC DA/SA table size */
2211 +// XRX200_ETHSW_CAP_6_APPL, /* Application table size */
2212 +// XRX200_ETHSW_CAP_7, /* Ethernet Switch CapabilityRegister 7 */
2213 +// XRX200_ETHSW_CAP_7_IPDASAM, /* IP DA/SA MSB table size */
2214 +// XRX200_ETHSW_CAP_7_IPDASAL, /* IP DA/SA LSB table size */
2215 +// XRX200_ETHSW_CAP_8, /* Ethernet Switch CapabilityRegister 8 */
2216 +// XRX200_ETHSW_CAP_8_MCAST, /* Multicast table size */
2217 +// XRX200_ETHSW_CAP_9, /* Ethernet Switch CapabilityRegister 9 */
2218 +// XRX200_ETHSW_CAP_9_FLAGG, /* Flow Aggregation table size */
2219 +// XRX200_ETHSW_CAP_10, /* Ethernet Switch CapabilityRegister 10 */
2220 +// XRX200_ETHSW_CAP_10_MACBT, /* MAC bridging table size */
2221 +// XRX200_ETHSW_CAP_11, /* Ethernet Switch CapabilityRegister 11 */
2222 +// XRX200_ETHSW_CAP_11_BSIZEL, /* Packet buffer size (lower part, in byte) */
2223 +// XRX200_ETHSW_CAP_12, /* Ethernet Switch CapabilityRegister 12 */
2224 +// XRX200_ETHSW_CAP_12_BSIZEH, /* Packet buffer size (higher part, in byte) */
2225 +// XRX200_ETHSW_VERSION_REV, /* Ethernet Switch VersionRegister */
2226 +// XRX200_ETHSW_VERSION_MOD_ID, /* Module Identification */
2227 +// XRX200_ETHSW_VERSION_REV_ID, /* Hardware Revision Identification */
2228 +// XRX200_ETHSW_IER, /* Interrupt Enable Register */
2229 +// XRX200_ETHSW_IER_FDMAIE, /* Fetch DMA Interrupt Enable */
2230 +// XRX200_ETHSW_IER_SDMAIE, /* Store DMA Interrupt Enable */
2231 +// XRX200_ETHSW_IER_MACIE, /* Ethernet MAC Interrupt Enable */
2232 +// XRX200_ETHSW_IER_PCEIE, /* Parser and Classification Engine Interrupt Enable */
2233 +// XRX200_ETHSW_IER_BMIE, /* Buffer Manager Interrupt Enable */
2234 +// XRX200_ETHSW_ISR, /* Interrupt Status Register */
2235 +// XRX200_ETHSW_ISR_FDMAINT, /* Fetch DMA Interrupt */
2236 +// XRX200_ETHSW_ISR_SDMAINT, /* Store DMA Interrupt */
2237 +// XRX200_ETHSW_ISR_MACINT, /* Ethernet MAC Interrupt */
2238 +// XRX200_ETHSW_ISR_PCEINT, /* Parser and Classification Engine Interrupt */
2239 +// XRX200_ETHSW_ISR_BMINT, /* Buffer Manager Interrupt */
2240 +// XRX200_ETHSW_SPARE_0, /* Ethernet Switch SpareCells 0 */
2241 +// XRX200_ETHSW_SPARE_0_SPARE, /* SPARE0 */
2242 +// XRX200_ETHSW_SPARE_1, /* Ethernet Switch SpareCells 1 */
2243 +// XRX200_ETHSW_SPARE_1_SPARE, /* SPARE1 */
2244 +// XRX200_ETHSW_SPARE_2, /* Ethernet Switch SpareCells 2 */
2245 +// XRX200_ETHSW_SPARE_2_SPARE, /* SPARE2 */
2246 +// XRX200_ETHSW_SPARE_3, /* Ethernet Switch SpareCells 3 */
2247 +// XRX200_ETHSW_SPARE_3_SPARE, /* SPARE3 */
2248 +// XRX200_ETHSW_SPARE_4, /* Ethernet Switch SpareCells 4 */
2249 +// XRX200_ETHSW_SPARE_4_SPARE, /* SPARE4 */
2250 +// XRX200_ETHSW_SPARE_5, /* Ethernet Switch SpareCells 5 */
2251 +// XRX200_ETHSW_SPARE_5_SPARE, /* SPARE5 */
2252 +// XRX200_ETHSW_SPARE_6, /* Ethernet Switch SpareCells 6 */
2253 +// XRX200_ETHSW_SPARE_6_SPARE, /* SPARE6 */
2254 +// XRX200_ETHSW_SPARE_7, /* Ethernet Switch SpareCells 7 */
2255 +// XRX200_ETHSW_SPARE_7_SPARE, /* SPARE7 */
2256 +// XRX200_ETHSW_SPARE_8, /* Ethernet Switch SpareCells 8 */
2257 +// XRX200_ETHSW_SPARE_8_SPARE, /* SPARE8 */
2258 +// XRX200_ETHSW_SPARE_9, /* Ethernet Switch SpareCells 9 */
2259 +// XRX200_ETHSW_SPARE_9_SPARE, /* SPARE9 */
2260 +// XRX200_ETHSW_SPARE_10, /* Ethernet Switch SpareCells 10 */
2261 +// XRX200_ETHSW_SPARE_10_SPARE, /* SPARE10 */
2262 +// XRX200_ETHSW_SPARE_11, /* Ethernet Switch SpareCells 11 */
2263 +// XRX200_ETHSW_SPARE_11_SPARE, /* SPARE11 */
2264 +// XRX200_ETHSW_SPARE_12, /* Ethernet Switch SpareCells 12 */
2265 +// XRX200_ETHSW_SPARE_12_SPARE, /* SPARE12 */
2266 +// XRX200_ETHSW_SPARE_13, /* Ethernet Switch SpareCells 13 */
2267 +// XRX200_ETHSW_SPARE_13_SPARE, /* SPARE13 */
2268 +// XRX200_ETHSW_SPARE_14, /* Ethernet Switch SpareCells 14 */
2269 +// XRX200_ETHSW_SPARE_14_SPARE, /* SPARE14 */
2270 +// XRX200_ETHSW_SPARE_15, /* Ethernet Switch SpareCells 15 */
2271 +// XRX200_ETHSW_SPARE_15_SPARE, /* SPARE15 */
2272 +// XRX200_BM_RAM_VAL_3, /* RAM Value Register 3 */
2273 +// XRX200_BM_RAM_VAL_3_VAL3, /* Data value [15:0] */
2274 +// XRX200_BM_RAM_VAL_2, /* RAM Value Register 2 */
2275 +// XRX200_BM_RAM_VAL_2_VAL2, /* Data value [15:0] */
2276 +// XRX200_BM_RAM_VAL_1, /* RAM Value Register 1 */
2277 +// XRX200_BM_RAM_VAL_1_VAL1, /* Data value [15:0] */
2278 +// XRX200_BM_RAM_VAL_0, /* RAM Value Register 0 */
2279 +// XRX200_BM_RAM_VAL_0_VAL0, /* Data value [15:0] */
2280 +// XRX200_BM_RAM_ADDR, /* RAM Address Register */
2281 +// XRX200_BM_RAM_ADDR_ADDR, /* RAM Address */
2282 +// XRX200_BM_RAM_CTRL, /* RAM Access Control Register */
2283 +// XRX200_BM_RAM_CTRL_BAS, /* Access Busy/Access Start */
2284 +// XRX200_BM_RAM_CTRL_OPMOD, /* Lookup Table Access Operation Mode */
2285 +// XRX200_BM_RAM_CTRL_ADDR, /* Address for RAM selection */
2286 +// XRX200_BM_FSQM_GCTRL, /* Free Segment Queue ManagerGlobal Control Register */
2287 +// XRX200_BM_FSQM_GCTRL_SEGNUM, /* Maximum Segment Number */
2288 +// XRX200_BM_CONS_SEG, /* Number of Consumed SegmentsRegister */
2289 +// XRX200_BM_CONS_SEG_FSEG, /* Number of Consumed Segments */
2290 +// XRX200_BM_CONS_PKT, /* Number of Consumed PacketPointers Register */
2291 +// XRX200_BM_CONS_PKT_FQP, /* Number of Consumed Packet Pointers */
2292 +// XRX200_BM_GCTRL_F, /* Buffer Manager Global ControlRegister 0 */
2293 +// XRX200_BM_GCTRL_BM_STA, /* Buffer Manager Initialization Status Bit */
2294 +// XRX200_BM_GCTRL_SAT, /* RMON Counter Update Mode */
2295 +// XRX200_BM_GCTRL_FR_RBC, /* Freeze RMON RX Bad Byte 64 Bit Counter */
2296 +// XRX200_BM_GCTRL_FR_RGC, /* Freeze RMON RX Good Byte 64 Bit Counter */
2297 +// XRX200_BM_GCTRL_FR_TGC, /* Freeze RMON TX Good Byte 64 Bit Counter */
2298 +// XRX200_BM_GCTRL_I_FIN, /* RAM initialization finished */
2299 +// XRX200_BM_GCTRL_CX_INI, /* PQM Context RAM initialization */
2300 +// XRX200_BM_GCTRL_FP_INI, /* FPQM RAM initialization */
2301 +// XRX200_BM_GCTRL_FS_INI, /* FSQM RAM initialization */
2302 +// XRX200_BM_GCTRL_R_SRES, /* Software Reset for RMON */
2303 +// XRX200_BM_GCTRL_S_SRES, /* Software Reset for Scheduler */
2304 +// XRX200_BM_GCTRL_A_SRES, /* Software Reset for AVG */
2305 +// XRX200_BM_GCTRL_P_SRES, /* Software Reset for PQM */
2306 +// XRX200_BM_GCTRL_F_SRES, /* Software Reset for FSQM */
2307 +// XRX200_BM_QUEUE_GCTRL, /* Queue Manager GlobalControl Register 0 */
2308 + XRX200_BM_QUEUE_GCTRL_GL_MOD, /* WRED Mode Signal */
2309 +// XRX200_BM_QUEUE_GCTRL_AQUI, /* Average Queue Update Interval */
2310 +// XRX200_BM_QUEUE_GCTRL_AQWF, /* Average Queue Weight Factor */
2311 +// XRX200_BM_QUEUE_GCTRL_QAVGEN, /* Queue Average Calculation Enable */
2312 +// XRX200_BM_QUEUE_GCTRL_DPROB, /* Drop Probability Profile */
2313 +// XRX200_BM_WRED_RTH_0, /* WRED Red Threshold Register0 */
2314 +// XRX200_BM_WRED_RTH_0_MINTH, /* Minimum Threshold */
2315 +// XRX200_BM_WRED_RTH_1, /* WRED Red Threshold Register1 */
2316 +// XRX200_BM_WRED_RTH_1_MAXTH, /* Maximum Threshold */
2317 +// XRX200_BM_WRED_YTH_0, /* WRED Yellow ThresholdRegister 0 */
2318 +// XRX200_BM_WRED_YTH_0_MINTH, /* Minimum Threshold */
2319 +// XRX200_BM_WRED_YTH_1, /* WRED Yellow ThresholdRegister 1 */
2320 +// XRX200_BM_WRED_YTH_1_MAXTH, /* Maximum Threshold */
2321 +// XRX200_BM_WRED_GTH_0, /* WRED Green ThresholdRegister 0 */
2322 +// XRX200_BM_WRED_GTH_0_MINTH, /* Minimum Threshold */
2323 +// XRX200_BM_WRED_GTH_1, /* WRED Green ThresholdRegister 1 */
2324 +// XRX200_BM_WRED_GTH_1_MAXTH, /* Maximum Threshold */
2325 +// XRX200_BM_DROP_GTH_0_THR, /* Drop Threshold ConfigurationRegister 0 */
2326 +// XRX200_BM_DROP_GTH_0_THR_FQ, /* Threshold for frames marked red */
2327 +// XRX200_BM_DROP_GTH_1_THY, /* Drop Threshold ConfigurationRegister 1 */
2328 +// XRX200_BM_DROP_GTH_1_THY_FQ, /* Threshold for frames marked yellow */
2329 +// XRX200_BM_DROP_GTH_2_THG, /* Drop Threshold ConfigurationRegister 2 */
2330 +// XRX200_BM_DROP_GTH_2_THG_FQ, /* Threshold for frames marked green */
2331 +// XRX200_BM_IER, /* Buffer Manager Global InterruptEnable Register */
2332 +// XRX200_BM_IER_CNT4, /* Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */
2333 +// XRX200_BM_IER_CNT3, /* Counter Group 3 (RMON-PQM) Interrupt Enable */
2334 +// XRX200_BM_IER_CNT2, /* Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */
2335 +// XRX200_BM_IER_CNT1, /* Counter Group 1 (RMON-QFETCH) Interrupt Enable */
2336 +// XRX200_BM_IER_CNT0, /* Counter Group 0 (RMON-QSTOR) Interrupt Enable */
2337 +// XRX200_BM_IER_DEQ, /* PQM dequeue Interrupt Enable */
2338 +// XRX200_BM_IER_ENQ, /* PQM Enqueue Interrupt Enable */
2339 +// XRX200_BM_IER_FSQM, /* Buffer Empty Interrupt Enable */
2340 +// XRX200_BM_ISR, /* Buffer Manager Global InterruptStatus Register */
2341 +// XRX200_BM_ISR_CNT4, /* Counter Group 4 Interrupt */
2342 +// XRX200_BM_ISR_CNT3, /* Counter Group 3 Interrupt */
2343 +// XRX200_BM_ISR_CNT2, /* Counter Group 2 Interrupt */
2344 +// XRX200_BM_ISR_CNT1, /* Counter Group 1 Interrupt */
2345 +// XRX200_BM_ISR_CNT0, /* Counter Group 0 Interrupt */
2346 +// XRX200_BM_ISR_DEQ, /* PQM dequeue Interrupt Enable */
2347 +// XRX200_BM_ISR_ENQ, /* PQM Enqueue Interrupt */
2348 +// XRX200_BM_ISR_FSQM, /* Buffer Empty Interrupt */
2349 +// XRX200_BM_CISEL, /* Buffer Manager RMON CounterInterrupt Select Register */
2350 +// XRX200_BM_CISEL_PORT, /* Port Number */
2351 +// XRX200_BM_DEBUG_CTRL_DBG, /* Debug Control Register */
2352 +// XRX200_BM_DEBUG_CTRL_DBG_SEL, /* Select Signal for Debug Multiplexer */
2353 +// XRX200_BM_DEBUG_VAL_DBG, /* Debug Value Register */
2354 +// XRX200_BM_DEBUG_VAL_DBG_DAT, /* Debug Data Value */
2355 +// XRX200_BM_PCFG, /* Buffer Manager PortConfiguration Register */
2356 +// XRX200_BM_PCFG_CNTEN, /* RMON Counter Enable */
2357 +// XRX200_BM_RMON_CTRL_RAM1, /* Buffer ManagerRMON Control Register */
2358 +// XRX200_BM_RMON_CTRL_RAM2_RES, /* Software Reset for RMON RAM2 */
2359 +// XRX200_BM_RMON_CTRL_RAM1_RES, /* Software Reset for RMON RAM1 */
2360 +// XRX200_PQM_DP, /* Packet Queue ManagerDrop Probability Register */
2361 +// XRX200_PQM_DP_DPROB, /* Drop Probability Profile */
2362 +// XRX200_PQM_RS, /* Packet Queue ManagerRate Shaper Assignment Register */
2363 +// XRX200_PQM_RS_EN2, /* Rate Shaper 2 Enable */
2364 +// XRX200_PQM_RS_RS2, /* Rate Shaper 2 */
2365 +// XRX200_PQM_RS_EN1, /* Rate Shaper 1 Enable */
2366 +// XRX200_PQM_RS_RS1, /* Rate Shaper 1 */
2367 +// XRX200_RS_CTRL, /* Rate Shaper ControlRegister */
2368 +// XRX200_RS_CTRL_RSEN, /* Rate Shaper Enable */
2369 +// XRX200_RS_CBS, /* Rate Shaper CommittedBurst Size Register */
2370 +// XRX200_RS_CBS_CBS, /* Committed Burst Size */
2371 +// XRX200_RS_IBS, /* Rate Shaper InstantaneousBurst Size Register */
2372 +// XRX200_RS_IBS_IBS, /* Instantaneous Burst Size */
2373 +// XRX200_RS_CIR_EXP, /* Rate Shaper RateExponent Register */
2374 +// XRX200_RS_CIR_EXP_EXP, /* Exponent */
2375 +// XRX200_RS_CIR_MANT, /* Rate Shaper RateMantissa Register */
2376 +// XRX200_RS_CIR_MANT_MANT, /* Mantissa */
2377 + XRX200_PCE_TBL_KEY_7, /* Table Key Data 7 */
2378 +// XRX200_PCE_TBL_KEY_7_KEY7, /* Key Value[15:0] */
2379 + XRX200_PCE_TBL_KEY_6, /* Table Key Data 6 */
2380 +// XRX200_PCE_TBL_KEY_6_KEY6, /* Key Value[15:0] */
2381 + XRX200_PCE_TBL_KEY_5, /* Table Key Data 5 */
2382 +// XRX200_PCE_TBL_KEY_5_KEY5, /* Key Value[15:0] */
2383 + XRX200_PCE_TBL_KEY_4, /* Table Key Data 4 */
2384 +// XRX200_PCE_TBL_KEY_4_KEY4, /* Key Value[15:0] */
2385 + XRX200_PCE_TBL_KEY_3, /* Table Key Data 3 */
2386 +// XRX200_PCE_TBL_KEY_3_KEY3, /* Key Value[15:0] */
2387 + XRX200_PCE_TBL_KEY_2, /* Table Key Data 2 */
2388 +// XRX200_PCE_TBL_KEY_2_KEY2, /* Key Value[15:0] */
2389 + XRX200_PCE_TBL_KEY_1, /* Table Key Data 1 */
2390 +// XRX200_PCE_TBL_KEY_1_KEY1, /* Key Value[31:16] */
2391 + XRX200_PCE_TBL_KEY_0, /* Table Key Data 0 */
2392 +// XRX200_PCE_TBL_KEY_0_KEY0, /* Key Value[15:0] */
2393 + XRX200_PCE_TBL_MASK_0, /* Table Mask Write Register0 */
2394 +// XRX200_PCE_TBL_MASK_0_MASK0, /* Mask Pattern [15:0] */
2395 + XRX200_PCE_TBL_VAL_4, /* Table Value Register4 */
2396 +// XRX200_PCE_TBL_VAL_4_VAL4, /* Data value [15:0] */
2397 + XRX200_PCE_TBL_VAL_3, /* Table Value Register3 */
2398 +// XRX200_PCE_TBL_VAL_3_VAL3, /* Data value [15:0] */
2399 + XRX200_PCE_TBL_VAL_2, /* Table Value Register2 */
2400 +// XRX200_PCE_TBL_VAL_2_VAL2, /* Data value [15:0] */
2401 + XRX200_PCE_TBL_VAL_1, /* Table Value Register1 */
2402 +// XRX200_PCE_TBL_VAL_1_VAL1, /* Data value [15:0] */
2403 + XRX200_PCE_TBL_VAL_0, /* Table Value Register0 */
2404 +// XRX200_PCE_TBL_VAL_0_VAL0, /* Data value [15:0] */
2405 +// XRX200_PCE_TBL_ADDR, /* Table Entry AddressRegister */
2406 + XRX200_PCE_TBL_ADDR_ADDR, /* Table Address */
2407 +// XRX200_PCE_TBL_CTRL, /* Table Access ControlRegister */
2408 + XRX200_PCE_TBL_CTRL_BAS, /* Access Busy/Access Start */
2409 + XRX200_PCE_TBL_CTRL_TYPE, /* Lookup Entry Type */
2410 + XRX200_PCE_TBL_CTRL_VLD, /* Lookup Entry Valid */
2411 + XRX200_PCE_TBL_CTRL_GMAP, /* Group Map */
2412 + XRX200_PCE_TBL_CTRL_OPMOD, /* Lookup Table Access Operation Mode */
2413 + XRX200_PCE_TBL_CTRL_ADDR, /* Lookup Table Address */
2414 +// XRX200_PCE_TBL_STAT, /* Table General StatusRegister */
2415 +// XRX200_PCE_TBL_STAT_TBUSY, /* Table Access Busy */
2416 +// XRX200_PCE_TBL_STAT_TEMPT, /* Table Empty */
2417 +// XRX200_PCE_TBL_STAT_TFUL, /* Table Full */
2418 +// XRX200_PCE_AGE_0, /* Aging Counter ConfigurationRegister 0 */
2419 +// XRX200_PCE_AGE_0_EXP, /* Aging Counter Exponent Value */
2420 +// XRX200_PCE_AGE_1, /* Aging Counter ConfigurationRegister 1 */
2421 +// XRX200_PCE_AGE_1_MANT, /* Aging Counter Mantissa Value */
2422 +// XRX200_PCE_PMAP_1, /* Port Map Register 1 */
2423 +// XRX200_PCE_PMAP_1_MPMAP, /* Monitoring Port Map */
2424 +// XRX200_PCE_PMAP_2, /* Port Map Register 2 */
2425 +// XRX200_PCE_PMAP_2_DMCPMAP, /* Default Multicast Port Map */
2426 +// XRX200_PCE_PMAP_3, /* Port Map Register 3 */
2427 +// XRX200_PCE_PMAP_3_UUCMAP, /* Default Unknown Unicast Port Map */
2428 +// XRX200_PCE_GCTRL_0, /* PCE Global Control Register0 */
2429 +// XRX200_PCE_GCTRL_0_IGMP, /* IGMP Mode Selection */
2430 + XRX200_PCE_GCTRL_0_VLAN, /* VLAN-aware Switching */
2431 +// XRX200_PCE_GCTRL_0_NOPM, /* No Port Map Forwarding */
2432 +// XRX200_PCE_GCTRL_0_SCONUC, /* Unknown Unicast Storm Control */
2433 +// XRX200_PCE_GCTRL_0_SCONMC, /* Multicast Storm Control */
2434 +// XRX200_PCE_GCTRL_0_SCONBC, /* Broadcast Storm Control */
2435 +// XRX200_PCE_GCTRL_0_SCONMOD, /* Storm Control Mode */
2436 +// XRX200_PCE_GCTRL_0_SCONMET, /* Storm Control Metering Instance */
2437 +// XRX200_PCE_GCTRL_0_MC_VALID, /* Access Request */
2438 +// XRX200_PCE_GCTRL_0_PLCKMOD, /* Port Lock Mode */
2439 +// XRX200_PCE_GCTRL_0_PLIMMOD, /* MAC Address Learning Limitation Mode */
2440 +// XRX200_PCE_GCTRL_0_MTFL, /* MAC Table Flushing */
2441 +// XRX200_PCE_GCTRL_1, /* PCE Global Control Register1 */
2442 +// XRX200_PCE_GCTRL_1_PCE_DIS, /* PCE Disable after currently processed packet */
2443 +// XRX200_PCE_GCTRL_1_LRNMOD, /* MAC Address Learning Mode */
2444 +// XRX200_PCE_TCM_GLOB_CTRL, /* Three-color MarkerGlobal Control Register */
2445 +// XRX200_PCE_TCM_GLOB_CTRL_DPRED, /* Re-marking Drop Precedence Red Encoding */
2446 +// XRX200_PCE_TCM_GLOB_CTRL_DPYEL, /* Re-marking Drop Precedence Yellow Encoding */
2447 +// XRX200_PCE_TCM_GLOB_CTRL_DPGRN, /* Re-marking Drop Precedence Green Encoding */
2448 +// XRX200_PCE_IGMP_CTRL, /* IGMP Control Register */
2449 +// XRX200_PCE_IGMP_CTRL_FAGEEN, /* Force Aging of Table Entries Enable */
2450 +// XRX200_PCE_IGMP_CTRL_FLEAVE, /* Fast Leave Enable */
2451 +// XRX200_PCE_IGMP_CTRL_DMRTEN, /* Default Maximum Response Time Enable */
2452 +// XRX200_PCE_IGMP_CTRL_JASUP, /* Join Aggregation Suppression Enable */
2453 +// XRX200_PCE_IGMP_CTRL_REPSUP, /* Report Suppression Enable */
2454 +// XRX200_PCE_IGMP_CTRL_SRPEN, /* Snooping of Router Port Enable */
2455 +// XRX200_PCE_IGMP_CTRL_ROB, /* Robustness Variable */
2456 +// XRX200_PCE_IGMP_CTRL_DMRT, /* IGMP Default Maximum Response Time */
2457 +// XRX200_PCE_IGMP_DRPM, /* IGMP Default RouterPort Map Register */
2458 +// XRX200_PCE_IGMP_DRPM_DRPM, /* IGMP Default Router Port Map */
2459 +// XRX200_PCE_IGMP_AGE_0, /* IGMP Aging Register0 */
2460 +// XRX200_PCE_IGMP_AGE_0_MANT, /* IGMP Group Aging Time Mantissa */
2461 +// XRX200_PCE_IGMP_AGE_0_EXP, /* IGMP Group Aging Time Exponent */
2462 +// XRX200_PCE_IGMP_AGE_1, /* IGMP Aging Register1 */
2463 +// XRX200_PCE_IGMP_AGE_1_MANT, /* IGMP Router Port Aging Time Mantissa */
2464 +// XRX200_PCE_IGMP_STAT, /* IGMP Status Register */
2465 +// XRX200_PCE_IGMP_STAT_IGPM, /* IGMP Port Map */
2466 +// XRX200_WOL_GLB_CTRL, /* Wake-on-LAN ControlRegister */
2467 +// XRX200_WOL_GLB_CTRL_PASSEN, /* WoL Password Enable */
2468 +// XRX200_WOL_DA_0, /* Wake-on-LAN DestinationAddress Register 0 */
2469 +// XRX200_WOL_DA_0_DA0, /* WoL Destination Address [15:0] */
2470 +// XRX200_WOL_DA_1, /* Wake-on-LAN DestinationAddress Register 1 */
2471 +// XRX200_WOL_DA_1_DA1, /* WoL Destination Address [31:16] */
2472 +// XRX200_WOL_DA_2, /* Wake-on-LAN DestinationAddress Register 2 */
2473 +// XRX200_WOL_DA_2_DA2, /* WoL Destination Address [47:32] */
2474 +// XRX200_WOL_PW_0, /* Wake-on-LAN Password Register0 */
2475 +// XRX200_WOL_PW_0_PW0, /* WoL Password [15:0] */
2476 +// XRX200_WOL_PW_1, /* Wake-on-LAN Password Register1 */
2477 +// XRX200_WOL_PW_1_PW1, /* WoL Password [31:16] */
2478 +// XRX200_WOL_PW_2, /* Wake-on-LAN Password Register2 */
2479 +// XRX200_WOL_PW_2_PW2, /* WoL Password [47:32] */
2480 +// XRX200_PCE_IER_0_PINT, /* Parser and ClassificationEngine Global Interrupt Enable Register 0 */
2481 +// XRX200_PCE_IER_0_PINT_15, /* Port Interrupt Enable */
2482 +// XRX200_PCE_IER_0_PINT_14, /* Port Interrupt Enable */
2483 +// XRX200_PCE_IER_0_PINT_13, /* Port Interrupt Enable */
2484 +// XRX200_PCE_IER_0_PINT_12, /* Port Interrupt Enable */
2485 +// XRX200_PCE_IER_0_PINT_11, /* Port Interrupt Enable */
2486 +// XRX200_PCE_IER_0_PINT_10, /* Port Interrupt Enable */
2487 +// XRX200_PCE_IER_0_PINT_9, /* Port Interrupt Enable */
2488 +// XRX200_PCE_IER_0_PINT_8, /* Port Interrupt Enable */
2489 +// XRX200_PCE_IER_0_PINT_7, /* Port Interrupt Enable */
2490 +// XRX200_PCE_IER_0_PINT_6, /* Port Interrupt Enable */
2491 +// XRX200_PCE_IER_0_PINT_5, /* Port Interrupt Enable */
2492 +// XRX200_PCE_IER_0_PINT_4, /* Port Interrupt Enable */
2493 +// XRX200_PCE_IER_0_PINT_3, /* Port Interrupt Enable */
2494 +// XRX200_PCE_IER_0_PINT_2, /* Port Interrupt Enable */
2495 +// XRX200_PCE_IER_0_PINT_1, /* Port Interrupt Enable */
2496 +// XRX200_PCE_IER_0_PINT_0, /* Port Interrupt Enable */
2497 +// XRX200_PCE_IER_1, /* Parser and ClassificationEngine Global Interrupt Enable Register 1 */
2498 +// XRX200_PCE_IER_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched Interrupt Enable */
2499 +// XRX200_PCE_IER_1_CPH2, /* Classification Phase 2 Ready Interrupt Enable */
2500 +// XRX200_PCE_IER_1_CPH1, /* Classification Phase 1 Ready Interrupt Enable */
2501 +// XRX200_PCE_IER_1_CPH0, /* Classification Phase 0 Ready Interrupt Enable */
2502 +// XRX200_PCE_IER_1_PRDY, /* Parser Ready Interrupt Enable */
2503 +// XRX200_PCE_IER_1_IGTF, /* IGMP Table Full Interrupt Enable */
2504 +// XRX200_PCE_IER_1_MTF, /* MAC Table Full Interrupt Enable */
2505 +// XRX200_PCE_ISR_0_PINT, /* Parser and ClassificationEngine Global Interrupt Status Register 0 */
2506 +// XRX200_PCE_ISR_0_PINT_15, /* Port Interrupt */
2507 +// XRX200_PCE_ISR_0_PINT_14, /* Port Interrupt */
2508 +// XRX200_PCE_ISR_0_PINT_13, /* Port Interrupt */
2509 +// XRX200_PCE_ISR_0_PINT_12, /* Port Interrupt */
2510 +// XRX200_PCE_ISR_0_PINT_11, /* Port Interrupt */
2511 +// XRX200_PCE_ISR_0_PINT_10, /* Port Interrupt */
2512 +// XRX200_PCE_ISR_0_PINT_9, /* Port Interrupt */
2513 +// XRX200_PCE_ISR_0_PINT_8, /* Port Interrupt */
2514 +// XRX200_PCE_ISR_0_PINT_7, /* Port Interrupt */
2515 +// XRX200_PCE_ISR_0_PINT_6, /* Port Interrupt */
2516 +// XRX200_PCE_ISR_0_PINT_5, /* Port Interrupt */
2517 +// XRX200_PCE_ISR_0_PINT_4, /* Port Interrupt */
2518 +// XRX200_PCE_ISR_0_PINT_3, /* Port Interrupt */
2519 +// XRX200_PCE_ISR_0_PINT_2, /* Port Interrupt */
2520 +// XRX200_PCE_ISR_0_PINT_1, /* Port Interrupt */
2521 +// XRX200_PCE_ISR_0_PINT_0, /* Port Interrupt */
2522 +// XRX200_PCE_ISR_1, /* Parser and ClassificationEngine Global Interrupt Status Register 1 */
2523 +// XRX200_PCE_ISR_1_FLOWINT, /* Traffic Flow Table Interrupt Rule matched */
2524 +// XRX200_PCE_ISR_1_CPH2, /* Classification Phase 2 Ready Interrupt */
2525 +// XRX200_PCE_ISR_1_CPH1, /* Classification Phase 1 Ready Interrupt */
2526 +// XRX200_PCE_ISR_1_CPH0, /* Classification Phase 0 Ready Interrupt */
2527 +// XRX200_PCE_ISR_1_PRDY, /* Parser Ready Interrupt */
2528 +// XRX200_PCE_ISR_1_IGTF, /* IGMP Table Full Interrupt */
2529 +// XRX200_PCE_ISR_1_MTF, /* MAC Table Full Interrupt */
2530 +// XRX200_PARSER_STAT_FIFO, /* Parser Status Register */
2531 +// XRX200_PARSER_STAT_FSM_DAT_CNT, /* Parser FSM Data Counter */
2532 +// XRX200_PARSER_STAT_FSM_STATE, /* Parser FSM State */
2533 +// XRX200_PARSER_STAT_PKT_ERR, /* Packet error detected */
2534 +// XRX200_PARSER_STAT_FSM_FIN, /* Parser FSM finished */
2535 +// XRX200_PARSER_STAT_FSM_START, /* Parser FSM start */
2536 +// XRX200_PARSER_STAT_FIFO_RDY, /* Parser FIFO ready for read. */
2537 +// XRX200_PARSER_STAT_FIFO_FULL, /* Parser */
2538 +// XRX200_PCE_PCTRL_0, /* PCE Port ControlRegister 0 */
2539 +// XRX200_PCE_PCTRL_0_MCST, /* Multicast Forwarding Mode Selection */
2540 +// XRX200_PCE_PCTRL_0_EGSTEN, /* Table-based Egress Special Tag Enable */
2541 +// XRX200_PCE_PCTRL_0_IGSTEN, /* Ingress Special Tag Enable */
2542 +// XRX200_PCE_PCTRL_0_PCPEN, /* PCP Remarking Mode */
2543 +// XRX200_PCE_PCTRL_0_CLPEN, /* Class Remarking Mode */
2544 +// XRX200_PCE_PCTRL_0_DPEN, /* Drop Precedence Remarking Mode */
2545 +// XRX200_PCE_PCTRL_0_CMOD, /* Three-color Marker Color Mode */
2546 +// XRX200_PCE_PCTRL_0_VREP, /* VLAN Replacement Mode */
2547 + XRX200_PCE_PCTRL_0_TVM, /* Transparent VLAN Mode */
2548 +// XRX200_PCE_PCTRL_0_PLOCK, /* Port Locking Enable */
2549 +// XRX200_PCE_PCTRL_0_AGEDIS, /* Aging Disable */
2550 +// XRX200_PCE_PCTRL_0_PSTATE, /* Port State */
2551 +// XRX200_PCE_PCTRL_1, /* PCE Port ControlRegister 1 */
2552 +// XRX200_PCE_PCTRL_1_LRNLIM, /* MAC Address Learning Limit */
2553 +// XRX200_PCE_PCTRL_2, /* PCE Port ControlRegister 2 */
2554 +// XRX200_PCE_PCTRL_2_DSCPMOD, /* DSCP Mode Selection */
2555 +// XRX200_PCE_PCTRL_2_DSCP, /* Enable DSCP to select the Class of Service */
2556 +// XRX200_PCE_PCTRL_2_PCP, /* Enable VLAN PCP to select the Class of Service */
2557 +// XRX200_PCE_PCTRL_2_PCLASS, /* Port-based Traffic Class */
2558 +// XRX200_PCE_PCTRL_3_VIO, /* PCE Port ControlRegister 3 */
2559 +// XRX200_PCE_PCTRL_3_EDIR, /* Egress Redirection Mode */
2560 +// XRX200_PCE_PCTRL_3_RXDMIR, /* Receive Mirroring Enable for dropped frames */
2561 +// XRX200_PCE_PCTRL_3_RXVMIR, /* Receive Mirroring Enable for valid frames */
2562 +// XRX200_PCE_PCTRL_3_TXMIR, /* Transmit Mirroring Enable */
2563 +// XRX200_PCE_PCTRL_3_VIO_7, /* Violation Type 7 Mirroring Enable */
2564 +// XRX200_PCE_PCTRL_3_VIO_6, /* Violation Type 6 Mirroring Enable */
2565 +// XRX200_PCE_PCTRL_3_VIO_5, /* Violation Type 5 Mirroring Enable */
2566 +// XRX200_PCE_PCTRL_3_VIO_4, /* Violation Type 4 Mirroring Enable */
2567 +// XRX200_PCE_PCTRL_3_VIO_3, /* Violation Type 3 Mirroring Enable */
2568 +// XRX200_PCE_PCTRL_3_VIO_2, /* Violation Type 2 Mirroring Enable */
2569 +// XRX200_PCE_PCTRL_3_VIO_1, /* Violation Type 1 Mirroring Enable */
2570 +// XRX200_PCE_PCTRL_3_VIO_0, /* Violation Type 0 Mirroring Enable */
2571 +// XRX200_WOL_CTRL, /* Wake-on-LAN ControlRegister */
2572 +// XRX200_WOL_CTRL_PORT, /* WoL Enable */
2573 +// XRX200_PCE_VCTRL, /* PCE VLAN ControlRegister */
2574 + XRX200_PCE_VCTRL_VSR, /* VLAN Security Rule */
2575 + XRX200_PCE_VCTRL_VEMR, /* VLAN Egress Member Violation Rule */
2576 + XRX200_PCE_VCTRL_VIMR, /* VLAN Ingress Member Violation Rule */
2577 + XRX200_PCE_VCTRL_VINR, /* VLAN Ingress Tag Rule */
2578 + XRX200_PCE_VCTRL_UVR, /* Unknown VLAN Rule */
2579 +// XRX200_PCE_DEFPVID, /* PCE Default PortVID Register */
2580 + XRX200_PCE_DEFPVID_PVID, /* Default Port VID Index */
2581 +// XRX200_PCE_PSTAT, /* PCE Port StatusRegister */
2582 +// XRX200_PCE_PSTAT_LRNCNT, /* Learning Count */
2583 +// XRX200_PCE_PIER, /* Parser and ClassificationEngine Port Interrupt Enable Register */
2584 +// XRX200_PCE_PIER_CLDRP, /* Classification Drop Interrupt Enable */
2585 +// XRX200_PCE_PIER_PTDRP, /* Port Drop Interrupt Enable */
2586 +// XRX200_PCE_PIER_VLAN, /* VLAN Violation Interrupt Enable */
2587 +// XRX200_PCE_PIER_WOL, /* Wake-on-LAN Interrupt Enable */
2588 +// XRX200_PCE_PIER_LOCK, /* Port Limit Alert Interrupt Enable */
2589 +// XRX200_PCE_PIER_LIM, /* Port Lock Alert Interrupt Enable */
2590 +// XRX200_PCE_PISR, /* Parser and ClassificationEngine Port Interrupt Status Register */
2591 +// XRX200_PCE_PISR_CLDRP, /* Classification Drop Interrupt */
2592 +// XRX200_PCE_PISR_PTDRP, /* Port Drop Interrupt */
2593 +// XRX200_PCE_PISR_VLAN, /* VLAN Violation Interrupt */
2594 +// XRX200_PCE_PISR_WOL, /* Wake-on-LAN Interrupt */
2595 +// XRX200_PCE_PISR_LOCK, /* Port Lock Alert Interrupt */
2596 +// XRX200_PCE_PISR_LIMIT, /* Port Limitation Alert Interrupt */
2597 +// XRX200_PCE_TCM_CTRL, /* Three-colorMarker Control Register */
2598 +// XRX200_PCE_TCM_CTRL_TCMEN, /* Three-color Marker metering instance enable */
2599 +// XRX200_PCE_TCM_STAT, /* Three-colorMarker Status Register */
2600 +// XRX200_PCE_TCM_STAT_AL1, /* Three-color Marker Alert 1 Status */
2601 +// XRX200_PCE_TCM_STAT_AL0, /* Three-color Marker Alert 0 Status */
2602 +// XRX200_PCE_TCM_CBS, /* Three-color MarkerCommitted Burst Size Register */
2603 +// XRX200_PCE_TCM_CBS_CBS, /* Committed Burst Size */
2604 +// XRX200_PCE_TCM_EBS, /* Three-color MarkerExcess Burst Size Register */
2605 +// XRX200_PCE_TCM_EBS_EBS, /* Excess Burst Size */
2606 +// XRX200_PCE_TCM_IBS, /* Three-color MarkerInstantaneous Burst Size Register */
2607 +// XRX200_PCE_TCM_IBS_IBS, /* Instantaneous Burst Size */
2608 +// XRX200_PCE_TCM_CIR_MANT, /* Three-colorMarker Constant Information Rate Mantissa Register */
2609 +// XRX200_PCE_TCM_CIR_MANT_MANT, /* Rate Counter Mantissa */
2610 +// XRX200_PCE_TCM_CIR_EXP, /* Three-colorMarker Constant Information Rate Exponent Register */
2611 +// XRX200_PCE_TCM_CIR_EXP_EXP, /* Rate Counter Exponent */
2612 +// XRX200_MAC_TEST, /* MAC Test Register */
2613 +// XRX200_MAC_TEST_JTP, /* Jitter Test Pattern */
2614 +// XRX200_MAC_PFAD_CFG, /* MAC Pause FrameSource Address Configuration Register */
2615 +// XRX200_MAC_PFAD_CFG_SAMOD, /* Source Address Mode */
2616 +// XRX200_MAC_PFSA_0, /* Pause Frame SourceAddress Part 0 */
2617 +// XRX200_MAC_PFSA_0_PFAD, /* Pause Frame Source Address Part 0 */
2618 +// XRX200_MAC_PFSA_1, /* Pause Frame SourceAddress Part 1 */
2619 +// XRX200_MAC_PFSA_1_PFAD, /* Pause Frame Source Address Part 1 */
2620 +// XRX200_MAC_PFSA_2, /* Pause Frame SourceAddress Part 2 */
2621 +// XRX200_MAC_PFSA_2_PFAD, /* Pause Frame Source Address Part 2 */
2622 +// XRX200_MAC_FLEN, /* MAC Frame Length Register */
2623 +// XRX200_MAC_FLEN_LEN, /* Maximum Frame Length */
2624 +// XRX200_MAC_VLAN_ETYPE_0, /* MAC VLAN EthertypeRegister 0 */
2625 +// XRX200_MAC_VLAN_ETYPE_0_OUTER, /* Ethertype */
2626 +// XRX200_MAC_VLAN_ETYPE_1, /* MAC VLAN EthertypeRegister 1 */
2627 +// XRX200_MAC_VLAN_ETYPE_1_INNER, /* Ethertype */
2628 +// XRX200_MAC_IER, /* MAC Interrupt EnableRegister */
2629 +// XRX200_MAC_IER_MACIEN, /* MAC Interrupt Enable */
2630 +// XRX200_MAC_ISR, /* MAC Interrupt StatusRegister */
2631 +// XRX200_MAC_ISR_MACINT, /* MAC Interrupt */
2632 +// XRX200_MAC_PSTAT, /* MAC Port Status Register */
2633 +// XRX200_MAC_PSTAT_PACT, /* PHY Active Status */
2634 + XRX200_MAC_PSTAT_GBIT, /* Gigabit Speed Status */
2635 + XRX200_MAC_PSTAT_MBIT, /* Megabit Speed Status */
2636 + XRX200_MAC_PSTAT_FDUP, /* Full Duplex Status */
2637 +// XRX200_MAC_PSTAT_RXPAU, /* Receive Pause Status */
2638 +// XRX200_MAC_PSTAT_TXPAU, /* Transmit Pause Status */
2639 +// XRX200_MAC_PSTAT_RXPAUEN, /* Receive Pause Enable Status */
2640 +// XRX200_MAC_PSTAT_TXPAUEN, /* Transmit Pause Enable Status */
2641 + XRX200_MAC_PSTAT_LSTAT, /* Link Status */
2642 +// XRX200_MAC_PSTAT_CRS, /* Carrier Sense Status */
2643 +// XRX200_MAC_PSTAT_TXLPI, /* Transmit Low-power Idle Status */
2644 +// XRX200_MAC_PSTAT_RXLPI, /* Receive Low-power Idle Status */
2645 +// XRX200_MAC_PISR, /* MAC Interrupt Status Register */
2646 +// XRX200_MAC_PISR_PACT, /* PHY Active Status */
2647 +// XRX200_MAC_PISR_SPEED, /* Megabit Speed Status */
2648 +// XRX200_MAC_PISR_FDUP, /* Full Duplex Status */
2649 +// XRX200_MAC_PISR_RXPAUEN, /* Receive Pause Enable Status */
2650 +// XRX200_MAC_PISR_TXPAUEN, /* Transmit Pause Enable Status */
2651 +// XRX200_MAC_PISR_LPIOFF, /* Receive Low-power Idle Mode is left */
2652 +// XRX200_MAC_PISR_LPION, /* Receive Low-power Idle Mode is entered */
2653 +// XRX200_MAC_PISR_JAM, /* Jam Status Detected */
2654 +// XRX200_MAC_PISR_TOOSHORT, /* Too Short Frame Error Detected */
2655 +// XRX200_MAC_PISR_TOOLONG, /* Too Long Frame Error Detected */
2656 +// XRX200_MAC_PISR_LENERR, /* Length Mismatch Error Detected */
2657 +// XRX200_MAC_PISR_FCSERR, /* Frame Checksum Error Detected */
2658 +// XRX200_MAC_PISR_TXPAUSE, /* Pause Frame Transmitted */
2659 +// XRX200_MAC_PISR_RXPAUSE, /* Pause Frame Received */
2660 +// XRX200_MAC_PIER, /* MAC Interrupt Enable Register */
2661 +// XRX200_MAC_PIER_PACT, /* PHY Active Status */
2662 +// XRX200_MAC_PIER_SPEED, /* Megabit Speed Status */
2663 +// XRX200_MAC_PIER_FDUP, /* Full Duplex Status */
2664 +// XRX200_MAC_PIER_RXPAUEN, /* Receive Pause Enable Status */
2665 +// XRX200_MAC_PIER_TXPAUEN, /* Transmit Pause Enable Status */
2666 +// XRX200_MAC_PIER_LPIOFF, /* Low-power Idle Off Interrupt Mask */
2667 +// XRX200_MAC_PIER_LPION, /* Low-power Idle On Interrupt Mask */
2668 +// XRX200_MAC_PIER_JAM, /* Jam Status Interrupt Mask */
2669 +// XRX200_MAC_PIER_TOOSHORT, /* Too Short Frame Error Interrupt Mask */
2670 +// XRX200_MAC_PIER_TOOLONG, /* Too Long Frame Error Interrupt Mask */
2671 +// XRX200_MAC_PIER_LENERR, /* Length Mismatch Error Interrupt Mask */
2672 +// XRX200_MAC_PIER_FCSERR, /* Frame Checksum Error Interrupt Mask */
2673 +// XRX200_MAC_PIER_TXPAUSE, /* Transmit Pause Frame Interrupt Mask */
2674 +// XRX200_MAC_PIER_RXPAUSE, /* Receive Pause Frame Interrupt Mask */
2675 +// XRX200_MAC_CTRL_0, /* MAC Control Register0 */
2676 +// XRX200_MAC_CTRL_0_LCOL, /* Late Collision Control */
2677 +// XRX200_MAC_CTRL_0_BM, /* Burst Mode Control */
2678 +// XRX200_MAC_CTRL_0_APADEN, /* Automatic VLAN Padding Enable */
2679 +// XRX200_MAC_CTRL_0_VPAD2EN, /* Stacked VLAN Padding Enable */
2680 +// XRX200_MAC_CTRL_0_VPADEN, /* VLAN Padding Enable */
2681 +// XRX200_MAC_CTRL_0_PADEN, /* Padding Enable */
2682 +// XRX200_MAC_CTRL_0_FCS, /* Transmit FCS Control */
2683 + XRX200_MAC_CTRL_0_FCON, /* Flow Control Mode */
2684 +// XRX200_MAC_CTRL_0_FDUP, /* Full Duplex Control */
2685 +// XRX200_MAC_CTRL_0_GMII, /* GMII/MII interface mode selection */
2686 +// XRX200_MAC_CTRL_1, /* MAC Control Register1 */
2687 +// XRX200_MAC_CTRL_1_SHORTPRE, /* Short Preamble Control */
2688 +// XRX200_MAC_CTRL_1_IPG, /* Minimum Inter Packet Gap Size */
2689 +// XRX200_MAC_CTRL_2, /* MAC Control Register2 */
2690 +// XRX200_MAC_CTRL_2_MLEN, /* Maximum Untagged Frame Length */
2691 +// XRX200_MAC_CTRL_2_LCHKL, /* Frame Length Check Long Enable */
2692 +// XRX200_MAC_CTRL_2_LCHKS, /* Frame Length Check Short Enable */
2693 +// XRX200_MAC_CTRL_3, /* MAC Control Register3 */
2694 +// XRX200_MAC_CTRL_3_RCNT, /* Retry Count */
2695 +// XRX200_MAC_CTRL_4, /* MAC Control Register4 */
2696 +// XRX200_MAC_CTRL_4_LPIEN, /* LPI Mode Enable */
2697 +// XRX200_MAC_CTRL_4_WAIT, /* LPI Wait Time */
2698 +// XRX200_MAC_CTRL_5_PJPS, /* MAC Control Register5 */
2699 +// XRX200_MAC_CTRL_5_PJPS_NOBP, /* Prolonged Jam pattern size during no-backpressure state */
2700 +// XRX200_MAC_CTRL_5_PJPS_BP, /* Prolonged Jam pattern size during backpressure state */
2701 +// XRX200_MAC_CTRL_6_XBUF, /* Transmit and ReceiveBuffer Control Register */
2702 +// XRX200_MAC_CTRL_6_RBUF_DLY_WP, /* Delay */
2703 +// XRX200_MAC_CTRL_6_RBUF_INIT, /* Receive Buffer Initialization */
2704 +// XRX200_MAC_CTRL_6_RBUF_BYPASS, /* Bypass the Receive Buffer */
2705 +// XRX200_MAC_CTRL_6_XBUF_DLY_WP, /* Delay */
2706 +// XRX200_MAC_CTRL_6_XBUF_INIT, /* Initialize the Transmit Buffer */
2707 +// XRX200_MAC_CTRL_6_XBUF_BYPASS, /* Bypass the Transmit Buffer */
2708 +// XRX200_MAC_BUFST_XBUF, /* MAC Receive and TransmitBuffer Status Register */
2709 +// XRX200_MAC_BUFST_RBUF_UFL, /* Receive Buffer Underflow Indicator */
2710 +// XRX200_MAC_BUFST_RBUF_OFL, /* Receive Buffer Overflow Indicator */
2711 +// XRX200_MAC_BUFST_XBUF_UFL, /* Transmit Buffer Underflow Indicator */
2712 +// XRX200_MAC_BUFST_XBUF_OFL, /* Transmit Buffer Overflow Indicator */
2713 +// XRX200_MAC_TESTEN, /* MAC Test Enable Register */
2714 +// XRX200_MAC_TESTEN_JTEN, /* Jitter Test Enable */
2715 +// XRX200_MAC_TESTEN_TXER, /* Transmit Error Insertion */
2716 +// XRX200_MAC_TESTEN_LOOP, /* MAC Loopback Enable */
2717 +// XRX200_FDMA_CTRL, /* Ethernet Switch FetchDMA Control Register */
2718 +// XRX200_FDMA_CTRL_LPI_THRESHOLD, /* Low Power Idle Threshold */
2719 +// XRX200_FDMA_CTRL_LPI_MODE, /* Low Power Idle Mode */
2720 +// XRX200_FDMA_CTRL_EGSTAG, /* Egress Special Tag Size */
2721 +// XRX200_FDMA_CTRL_IGSTAG, /* Ingress Special Tag Size */
2722 +// XRX200_FDMA_CTRL_EXCOL, /* Excessive Collision Handling */
2723 +// XRX200_FDMA_STETYPE, /* Special Tag EthertypeControl Register */
2724 +// XRX200_FDMA_STETYPE_ETYPE, /* Special Tag Ethertype */
2725 +// XRX200_FDMA_VTETYPE, /* VLAN Tag EthertypeControl Register */
2726 +// XRX200_FDMA_VTETYPE_ETYPE, /* VLAN Tag Ethertype */
2727 +// XRX200_FDMA_STAT_0, /* FDMA Status Register0 */
2728 +// XRX200_FDMA_STAT_0_FSMS, /* FSM states status */
2729 +// XRX200_FDMA_IER, /* Fetch DMA Global InterruptEnable Register */
2730 +// XRX200_FDMA_IER_PCKD, /* Packet Drop Interrupt Enable */
2731 +// XRX200_FDMA_IER_PCKR, /* Packet Ready Interrupt Enable */
2732 +// XRX200_FDMA_IER_PCKT, /* Packet Sent Interrupt Enable */
2733 +// XRX200_FDMA_ISR, /* Fetch DMA Global InterruptStatus Register */
2734 +// XRX200_FDMA_ISR_PCKTD, /* Packet Drop */
2735 +// XRX200_FDMA_ISR_PCKR, /* Packet is Ready for Transmission */
2736 +// XRX200_FDMA_ISR_PCKT, /* Packet Sent Event */
2737 +// XRX200_FDMA_PCTRL, /* Ethernet SwitchFetch DMA Port Control Register */
2738 +// XRX200_FDMA_PCTRL_VLANMOD, /* VLAN Modification Enable */
2739 +// XRX200_FDMA_PCTRL_DSCPRM, /* DSCP Re-marking Enable */
2740 +// XRX200_FDMA_PCTRL_STEN, /* Special Tag Insertion Enable */
2741 +// XRX200_FDMA_PCTRL_EN, /* FDMA Port Enable */
2742 +// XRX200_FDMA_PRIO, /* Ethernet SwitchFetch DMA Port Priority Register */
2743 +// XRX200_FDMA_PRIO_PRIO, /* FDMA PRIO */
2744 +// XRX200_FDMA_PSTAT0, /* Ethernet SwitchFetch DMA Port Status Register 0 */
2745 +// XRX200_FDMA_PSTAT0_PKT_AVAIL, /* Port Egress Packet Available */
2746 +// XRX200_FDMA_PSTAT0_POK, /* Port Status OK */
2747 +// XRX200_FDMA_PSTAT0_PSEG, /* Port Egress Segment Count */
2748 +// XRX200_FDMA_PSTAT1_HDR, /* Ethernet SwitchFetch DMA Port Status Register 1 */
2749 +// XRX200_FDMA_PSTAT1_HDR_PTR, /* Header Pointer */
2750 +// XRX200_FDMA_TSTAMP0, /* Egress TimeStamp Register 0 */
2751 +// XRX200_FDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */
2752 +// XRX200_FDMA_TSTAMP1, /* Egress TimeStamp Register 1 */
2753 +// XRX200_FDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */
2754 +// XRX200_SDMA_CTRL, /* Ethernet Switch StoreDMA Control Register */
2755 +// XRX200_SDMA_CTRL_TSTEN, /* Time Stamp Enable */
2756 +// XRX200_SDMA_FCTHR1, /* SDMA Flow Control Threshold1 Register */
2757 +// XRX200_SDMA_FCTHR1_THR1, /* Threshold 1 */
2758 +// XRX200_SDMA_FCTHR2, /* SDMA Flow Control Threshold2 Register */
2759 +// XRX200_SDMA_FCTHR2_THR2, /* Threshold 2 */
2760 +// XRX200_SDMA_FCTHR3, /* SDMA Flow Control Threshold3 Register */
2761 +// XRX200_SDMA_FCTHR3_THR3, /* Threshold 3 */
2762 +// XRX200_SDMA_FCTHR4, /* SDMA Flow Control Threshold4 Register */
2763 +// XRX200_SDMA_FCTHR4_THR4, /* Threshold 4 */
2764 +// XRX200_SDMA_FCTHR5, /* SDMA Flow Control Threshold5 Register */
2765 +// XRX200_SDMA_FCTHR5_THR5, /* Threshold 5 */
2766 +// XRX200_SDMA_FCTHR6, /* SDMA Flow Control Threshold6 Register */
2767 +// XRX200_SDMA_FCTHR6_THR6, /* Threshold 6 */
2768 +// XRX200_SDMA_FCTHR7, /* SDMA Flow Control Threshold7 Register */
2769 +// XRX200_SDMA_FCTHR7_THR7, /* Threshold 7 */
2770 +// XRX200_SDMA_STAT_0, /* SDMA Status Register0 */
2771 +// XRX200_SDMA_STAT_0_BPS_FILL, /* Back Pressure Status */
2772 +// XRX200_SDMA_STAT_0_BPS_PNT, /* Back Pressure Status */
2773 +// XRX200_SDMA_STAT_0_DROP, /* Back Pressure Status */
2774 +// XRX200_SDMA_STAT_1, /* SDMA Status Register1 */
2775 +// XRX200_SDMA_STAT_1_FILL, /* Buffer Filling Level */
2776 +// XRX200_SDMA_STAT_2, /* SDMA Status Register2 */
2777 +// XRX200_SDMA_STAT_2_FSMS, /* FSM states status */
2778 +// XRX200_SDMA_IER, /* SDMA Interrupt Enable Register */
2779 +// XRX200_SDMA_IER_BPEX, /* Buffer Pointers Exceeded */
2780 +// XRX200_SDMA_IER_BFULL, /* Buffer Full */
2781 +// XRX200_SDMA_IER_FERR, /* Frame Error */
2782 +// XRX200_SDMA_IER_FRX, /* Frame Received Successfully */
2783 +// XRX200_SDMA_ISR, /* SDMA Interrupt Status Register */
2784 +// XRX200_SDMA_ISR_BPEX, /* Packet Descriptors Exceeded */
2785 +// XRX200_SDMA_ISR_BFULL, /* Buffer Full */
2786 +// XRX200_SDMA_ISR_FERR, /* Frame Error */
2787 +// XRX200_SDMA_ISR_FRX, /* Frame Received Successfully */
2788 +// XRX200_SDMA_PCTRL, /* Ethernet SwitchStore DMA Port Control Register */
2789 +// XRX200_SDMA_PCTRL_DTHR, /* Drop Threshold Selection */
2790 +// XRX200_SDMA_PCTRL_PTHR, /* Pause Threshold Selection */
2791 +// XRX200_SDMA_PCTRL_PHYEFWD, /* Forward PHY Error Frames */
2792 +// XRX200_SDMA_PCTRL_ALGFWD, /* Forward Alignment Error Frames */
2793 +// XRX200_SDMA_PCTRL_LENFWD, /* Forward Length Errored Frames */
2794 +// XRX200_SDMA_PCTRL_OSFWD, /* Forward Oversized Frames */
2795 +// XRX200_SDMA_PCTRL_USFWD, /* Forward Undersized Frames */
2796 +// XRX200_SDMA_PCTRL_FCSIGN, /* Ignore FCS Errors */
2797 +// XRX200_SDMA_PCTRL_FCSFWD, /* Forward FCS Errored Frames */
2798 +// XRX200_SDMA_PCTRL_PAUFWD, /* Pause Frame Forwarding */
2799 +// XRX200_SDMA_PCTRL_MFCEN, /* Metering Flow Control Enable */
2800 +// XRX200_SDMA_PCTRL_FCEN, /* Flow Control Enable */
2801 +// XRX200_SDMA_PCTRL_PEN, /* Port Enable */
2802 +// XRX200_SDMA_PRIO, /* Ethernet SwitchStore DMA Port Priority Register */
2803 +// XRX200_SDMA_PRIO_PRIO, /* SDMA PRIO */
2804 +// XRX200_SDMA_PSTAT0_HDR, /* Ethernet SwitchStore DMA Port Status Register 0 */
2805 +// XRX200_SDMA_PSTAT0_HDR_PTR, /* Port Ingress Queue Header Pointer */
2806 +// XRX200_SDMA_PSTAT1, /* Ethernet SwitchStore DMA Port Status Register 1 */
2807 +// XRX200_SDMA_PSTAT1_PPKT, /* Port Ingress Packet Count */
2808 +// XRX200_SDMA_TSTAMP0, /* Ingress TimeStamp Register 0 */
2809 +// XRX200_SDMA_TSTAMP0_TSTL, /* Time Stamp [15:0] */
2810 +// XRX200_SDMA_TSTAMP1, /* Ingress TimeStamp Register 1 */
2811 +// XRX200_SDMA_TSTAMP1_TSTH, /* Time Stamp [31:16] */
2812 +};
2813 +
2814 +
2815 +struct xrx200sw_reg {
2816 + int offset;
2817 + int shift;
2818 + int size;
2819 + int mult;
2820 +} xrx200sw_reg[] = {
2821 +// offeset shift size mult
2822 +// {0x0000, 0, 16, 0x00}, /* XRX200_ETHSW_SWRES Ethernet Switch ResetControl Register */
2823 +// {0x0000, 1, 1, 0x00}, /* XRX200_ETHSW_SWRES_R1 Hardware Reset */
2824 +// {0x0000, 0, 1, 0x00}, /* XRX200_ETHSW_SWRES_R0 Register Configuration */
2825 +// {0x0004, 0, 16, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT Ethernet Switch Clock ControlRegister */
2826 +// {0x0004, 12, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_SLEEP Exponent to put system into sleep */
2827 +// {0x0004, 8, 4, 0x00}, /* XRX200_ETHSW_CLK_EXP_WAKE Exponent to wake up system */
2828 +// {0x0004, 7, 1, 0x00}, /* XRX200_ETHSW_CLK_CLK2_EN CLK2 Input for MAC */
2829 +// {0x0004, 6, 1, 0x00}, /* XRX200_ETHSW_CLK_EXT_DIV_EN External Clock Divider Enable */
2830 +// {0x0004, 5, 1, 0x00}, /* XRX200_ETHSW_CLK_RAM_DBG_EN Clock Gating Enable */
2831 +// {0x0004, 4, 1, 0x00}, /* XRX200_ETHSW_CLK_REG_GAT_EN Clock Gating Enable */
2832 +// {0x0004, 3, 1, 0x00}, /* XRX200_ETHSW_CLK_GAT_EN Clock Gating Enable */
2833 +// {0x0004, 2, 1, 0x00}, /* XRX200_ETHSW_CLK_MAC_GAT_EN Clock Gating Enable */
2834 +// {0x0008, 0, 16, 0x00}, /* XRX200_ETHSW_DBG_STEP Ethernet Switch Debug ControlRegister */
2835 +// {0x0008, 12, 4, 0x00}, /* XRX200_ETHSW_DBG_CLK_SEL Trigger Enable */
2836 +// {0x0008, 11, 1, 0x00}, /* XRX200_ETHSW_DBG_MON_EN Monitoring Enable */
2837 +// {0x0008, 9, 2, 0x00}, /* XRX200_ETHSW_DBG_TRIG_EN Trigger Enable */
2838 +// {0x0008, 8, 1, 0x00}, /* XRX200_ETHSW_DBG_MODE Debug Mode */
2839 +// {0x0008, 0, 8, 0x00}, /* XRX200_ETHSW_DBG_STEP_TIME Clock Step Size */
2840 +// {0x000C, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_MODE Ethernet Switch SharedSegment Buffer Mode Register */
2841 +// {0x000C, 2, 4, 0x00}, /* XRX200_ETHSW_SSB_MODE_ADDE Memory Address */
2842 +// {0x000C, 0, 2, 0x00}, /* XRX200_ETHSW_SSB_MODE_MODE Memory Access Mode */
2843 +// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR Ethernet Switch SharedSegment Buffer Address Register */
2844 +// {0x0010, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_ADDR_ADDE Memory Address */
2845 +// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA Ethernet Switch SharedSegment Buffer Data Register */
2846 +// {0x0014, 0, 16, 0x00}, /* XRX200_ETHSW_SSB_DATA_DATA Data Value */
2847 +// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0 Ethernet Switch CapabilityRegister 0 */
2848 +// {0x0018, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_0_SPEED Clock frequency */
2849 +// {0x001C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_1 Ethernet Switch CapabilityRegister 1 */
2850 +// {0x001C, 15, 1, 0x00}, /* XRX200_ETHSW_CAP_1_GMAC MAC operation mode */
2851 +// {0x001C, 8, 7, 0x00}, /* XRX200_ETHSW_CAP_1_QUEUE Number of queues */
2852 +// {0x001C, 4, 4, 0x00}, /* XRX200_ETHSW_CAP_1_VPORTS Number of virtual ports */
2853 +// {0x001C, 0, 4, 0x00}, /* XRX200_ETHSW_CAP_1_PPORTS Number of physical ports */
2854 +// {0x0020, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_2 Ethernet Switch CapabilityRegister 2 */
2855 +// {0x0020, 0, 11, 0x00}, /* XRX200_ETHSW_CAP_2_PACKETS Number of packets */
2856 +// {0x0024, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_3 Ethernet Switch CapabilityRegister 3 */
2857 +// {0x0024, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_3_METERS Number of traffic meters */
2858 +// {0x0024, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_3_SHAPERS Number of traffic shapers */
2859 +// {0x0028, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_4 Ethernet Switch CapabilityRegister 4 */
2860 +// {0x0028, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_4_PPPOE PPPoE table size */
2861 +// {0x0028, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_4_VLAN Active VLAN table size */
2862 +// {0x002C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_5 Ethernet Switch CapabilityRegister 5 */
2863 +// {0x002C, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_5_IPPLEN IP packet length table size */
2864 +// {0x002C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_5_PROT Protocol table size */
2865 +// {0x0030, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_6 Ethernet Switch CapabilityRegister 6 */
2866 +// {0x0030, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_6_MACDASA MAC DA/SA table size */
2867 +// {0x0030, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_6_APPL Application table size */
2868 +// {0x0034, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_7 Ethernet Switch CapabilityRegister 7 */
2869 +// {0x0034, 8, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAM IP DA/SA MSB table size */
2870 +// {0x0034, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_7_IPDASAL IP DA/SA LSB table size */
2871 +// {0x0038, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_8 Ethernet Switch CapabilityRegister 8 */
2872 +// {0x0038, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_8_MCAST Multicast table size */
2873 +// {0x003C, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_9 Ethernet Switch CapabilityRegister 9 */
2874 +// {0x003C, 0, 8, 0x00}, /* XRX200_ETHSW_CAP_9_FLAGG Flow Aggregation table size */
2875 +// {0x0040, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_10 Ethernet Switch CapabilityRegister 10 */
2876 +// {0x0040, 0, 13, 0x00}, /* XRX200_ETHSW_CAP_10_MACBT MAC bridging table size */
2877 +// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11 Ethernet Switch CapabilityRegister 11 */
2878 +// {0x0044, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_11_BSIZEL Packet buffer size (lower part, in byte) */
2879 +// {0x0048, 0, 16, 0x00}, /* XRX200_ETHSW_CAP_12 Ethernet Switch CapabilityRegister 12 */
2880 +// {0x0048, 0, 3, 0x00}, /* XRX200_ETHSW_CAP_12_BSIZEH Packet buffer size (higher part, in byte) */
2881 +// {0x004C, 0, 16, 0x00}, /* XRX200_ETHSW_VERSION_REV Ethernet Switch VersionRegister */
2882 +// {0x004C, 8, 8, 0x00}, /* XRX200_ETHSW_VERSION_MOD_ID Module Identification */
2883 +// {0x004C, 0, 8, 0x00}, /* XRX200_ETHSW_VERSION_REV_ID Hardware Revision Identification */
2884 +// {0x0050, 0, 16, 0x00}, /* XRX200_ETHSW_IER Interrupt Enable Register */
2885 +// {0x0050, 4, 1, 0x00}, /* XRX200_ETHSW_IER_FDMAIE Fetch DMA Interrupt Enable */
2886 +// {0x0050, 3, 1, 0x00}, /* XRX200_ETHSW_IER_SDMAIE Store DMA Interrupt Enable */
2887 +// {0x0050, 2, 1, 0x00}, /* XRX200_ETHSW_IER_MACIE Ethernet MAC Interrupt Enable */
2888 +// {0x0050, 1, 1, 0x00}, /* XRX200_ETHSW_IER_PCEIE Parser and Classification Engine Interrupt Enable */
2889 +// {0x0050, 0, 1, 0x00}, /* XRX200_ETHSW_IER_BMIE Buffer Manager Interrupt Enable */
2890 +// {0x0054, 0, 16, 0x00}, /* XRX200_ETHSW_ISR Interrupt Status Register */
2891 +// {0x0054, 4, 1, 0x00}, /* XRX200_ETHSW_ISR_FDMAINT Fetch DMA Interrupt */
2892 +// {0x0054, 3, 1, 0x00}, /* XRX200_ETHSW_ISR_SDMAINT Store DMA Interrupt */
2893 +// {0x0054, 2, 1, 0x00}, /* XRX200_ETHSW_ISR_MACINT Ethernet MAC Interrupt */
2894 +// {0x0054, 1, 1, 0x00}, /* XRX200_ETHSW_ISR_PCEINT Parser and Classification Engine Interrupt */
2895 +// {0x0054, 0, 1, 0x00}, /* XRX200_ETHSW_ISR_BMINT Buffer Manager Interrupt */
2896 +// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0 Ethernet Switch SpareCells 0 */
2897 +// {0x0058, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_0_SPARE SPARE0 */
2898 +// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1 Ethernet Switch SpareCells 1 */
2899 +// {0x005C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_1_SPARE SPARE1 */
2900 +// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2 Ethernet Switch SpareCells 2 */
2901 +// {0x0060, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_2_SPARE SPARE2 */
2902 +// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3 Ethernet Switch SpareCells 3 */
2903 +// {0x0064, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_3_SPARE SPARE3 */
2904 +// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4 Ethernet Switch SpareCells 4 */
2905 +// {0x0068, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_4_SPARE SPARE4 */
2906 +// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5 Ethernet Switch SpareCells 5 */
2907 +// {0x006C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_5_SPARE SPARE5 */
2908 +// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6 Ethernet Switch SpareCells 6 */
2909 +// {0x0070, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_6_SPARE SPARE6 */
2910 +// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7 Ethernet Switch SpareCells 7 */
2911 +// {0x0074, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_7_SPARE SPARE7 */
2912 +// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8 Ethernet Switch SpareCells 8 */
2913 +// {0x0078, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_8_SPARE SPARE8 */
2914 +// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9 Ethernet Switch SpareCells 9 */
2915 +// {0x007C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_9_SPARE SPARE9 */
2916 +// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10 Ethernet Switch SpareCells 10 */
2917 +// {0x0080, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_10_SPARE SPARE10 */
2918 +// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11 Ethernet Switch SpareCells 11 */
2919 +// {0x0084, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_11_SPARE SPARE11 */
2920 +// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12 Ethernet Switch SpareCells 12 */
2921 +// {0x0088, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_12_SPARE SPARE12 */
2922 +// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13 Ethernet Switch SpareCells 13 */
2923 +// {0x008C, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_13_SPARE SPARE13 */
2924 +// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14 Ethernet Switch SpareCells 14 */
2925 +// {0x0090, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_14_SPARE SPARE14 */
2926 +// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15 Ethernet Switch SpareCells 15 */
2927 +// {0x0094, 0, 16, 0x00}, /* XRX200_ETHSW_SPARE_15_SPARE SPARE15 */
2928 +// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3 RAM Value Register 3 */
2929 +// {0x0100, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_3_VAL3 Data value [15:0] */
2930 +// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2 RAM Value Register 2 */
2931 +// {0x0104, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_2_VAL2 Data value [15:0] */
2932 +// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1 RAM Value Register 1 */
2933 +// {0x0108, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_1_VAL1 Data value [15:0] */
2934 +// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0 RAM Value Register 0 */
2935 +// {0x010C, 0, 16, 0x00}, /* XRX200_BM_RAM_VAL_0_VAL0 Data value [15:0] */
2936 +// {0x0110, 0, 16, 0x00}, /* XRX200_BM_RAM_ADDR RAM Address Register */
2937 +// {0x0110, 0, 11, 0x00}, /* XRX200_BM_RAM_ADDR_ADDR RAM Address */
2938 +// {0x0114, 0, 16, 0x00}, /* XRX200_BM_RAM_CTRL RAM Access Control Register */
2939 +// {0x0114, 15, 1, 0x00}, /* XRX200_BM_RAM_CTRL_BAS Access Busy/Access Start */
2940 +// {0x0114, 5, 1, 0x00}, /* XRX200_BM_RAM_CTRL_OPMOD Lookup Table Access Operation Mode */
2941 +// {0x0114, 0, 5, 0x00}, /* XRX200_BM_RAM_CTRL_ADDR Address for RAM selection */
2942 +// {0x0118, 0, 16, 0x00}, /* XRX200_BM_FSQM_GCTRL Free Segment Queue ManagerGlobal Control Register */
2943 +// {0x0118, 0, 10, 0x00}, /* XRX200_BM_FSQM_GCTRL_SEGNUM Maximum Segment Number */
2944 +// {0x011C, 0, 16, 0x00}, /* XRX200_BM_CONS_SEG Number of Consumed SegmentsRegister */
2945 +// {0x011C, 0, 10, 0x00}, /* XRX200_BM_CONS_SEG_FSEG Number of Consumed Segments */
2946 +// {0x0120, 0, 16, 0x00}, /* XRX200_BM_CONS_PKT Number of Consumed PacketPointers Register */
2947 +// {0x0120, 0, 11, 0x00}, /* XRX200_BM_CONS_PKT_FQP Number of Consumed Packet Pointers */
2948 +// {0x0124, 0, 16, 0x00}, /* XRX200_BM_GCTRL_F Buffer Manager Global ControlRegister 0 */
2949 +// {0x0124, 13, 1, 0x00}, /* XRX200_BM_GCTRL_BM_STA Buffer Manager Initialization Status Bit */
2950 +// {0x0124, 12, 1, 0x00}, /* XRX200_BM_GCTRL_SAT RMON Counter Update Mode */
2951 +// {0x0124, 11, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RBC Freeze RMON RX Bad Byte 64 Bit Counter */
2952 +// {0x0124, 10, 1, 0x00}, /* XRX200_BM_GCTRL_FR_RGC Freeze RMON RX Good Byte 64 Bit Counter */
2953 +// {0x0124, 9, 1, 0x00}, /* XRX200_BM_GCTRL_FR_TGC Freeze RMON TX Good Byte 64 Bit Counter */
2954 +// {0x0124, 8, 1, 0x00}, /* XRX200_BM_GCTRL_I_FIN RAM initialization finished */
2955 +// {0x0124, 7, 1, 0x00}, /* XRX200_BM_GCTRL_CX_INI PQM Context RAM initialization */
2956 +// {0x0124, 6, 1, 0x00}, /* XRX200_BM_GCTRL_FP_INI FPQM RAM initialization */
2957 +// {0x0124, 5, 1, 0x00}, /* XRX200_BM_GCTRL_FS_INI FSQM RAM initialization */
2958 +// {0x0124, 4, 1, 0x00}, /* XRX200_BM_GCTRL_R_SRES Software Reset for RMON */
2959 +// {0x0124, 3, 1, 0x00}, /* XRX200_BM_GCTRL_S_SRES Software Reset for Scheduler */
2960 +// {0x0124, 2, 1, 0x00}, /* XRX200_BM_GCTRL_A_SRES Software Reset for AVG */
2961 +// {0x0124, 1, 1, 0x00}, /* XRX200_BM_GCTRL_P_SRES Software Reset for PQM */
2962 +// {0x0124, 0, 1, 0x00}, /* XRX200_BM_GCTRL_F_SRES Software Reset for FSQM */
2963 +// {0x0128, 0, 16, 0x00}, /* XRX200_BM_QUEUE_GCTRL Queue Manager GlobalControl Register 0 */
2964 + {0x0128, 10, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_GL_MOD WRED Mode Signal */
2965 +// {0x0128, 7, 3, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQUI Average Queue Update Interval */
2966 +// {0x0128, 3, 4, 0x00}, /* XRX200_BM_QUEUE_GCTRL_AQWF Average Queue Weight Factor */
2967 +// {0x0128, 2, 1, 0x00}, /* XRX200_BM_QUEUE_GCTRL_QAVGEN Queue Average Calculation Enable */
2968 +// {0x0128, 0, 2, 0x00}, /* XRX200_BM_QUEUE_GCTRL_DPROB Drop Probability Profile */
2969 +// {0x012C, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_0 WRED Red Threshold Register0 */
2970 +// {0x012C, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_0_MINTH Minimum Threshold */
2971 +// {0x0130, 0, 16, 0x00}, /* XRX200_BM_WRED_RTH_1 WRED Red Threshold Register1 */
2972 +// {0x0130, 0, 10, 0x00}, /* XRX200_BM_WRED_RTH_1_MAXTH Maximum Threshold */
2973 +// {0x0134, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_0 WRED Yellow ThresholdRegister 0 */
2974 +// {0x0134, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_0_MINTH Minimum Threshold */
2975 +// {0x0138, 0, 16, 0x00}, /* XRX200_BM_WRED_YTH_1 WRED Yellow ThresholdRegister 1 */
2976 +// {0x0138, 0, 10, 0x00}, /* XRX200_BM_WRED_YTH_1_MAXTH Maximum Threshold */
2977 +// {0x013C, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_0 WRED Green ThresholdRegister 0 */
2978 +// {0x013C, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_0_MINTH Minimum Threshold */
2979 +// {0x0140, 0, 16, 0x00}, /* XRX200_BM_WRED_GTH_1 WRED Green ThresholdRegister 1 */
2980 +// {0x0140, 0, 10, 0x00}, /* XRX200_BM_WRED_GTH_1_MAXTH Maximum Threshold */
2981 +// {0x0144, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_0_THR Drop Threshold ConfigurationRegister 0 */
2982 +// {0x0144, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_0_THR_FQ Threshold for frames marked red */
2983 +// {0x0148, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_1_THY Drop Threshold ConfigurationRegister 1 */
2984 +// {0x0148, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_1_THY_FQ Threshold for frames marked yellow */
2985 +// {0x014C, 0, 16, 0x00}, /* XRX200_BM_DROP_GTH_2_THG Drop Threshold ConfigurationRegister 2 */
2986 +// {0x014C, 0, 11, 0x00}, /* XRX200_BM_DROP_GTH_2_THG_FQ Threshold for frames marked green */
2987 +// {0x0150, 0, 16, 0x00}, /* XRX200_BM_IER Buffer Manager Global InterruptEnable Register */
2988 +// {0x0150, 7, 1, 0x00}, /* XRX200_BM_IER_CNT4 Counter Group 4 (RMON-CLASSIFICATION) Interrupt Enable */
2989 +// {0x0150, 6, 1, 0x00}, /* XRX200_BM_IER_CNT3 Counter Group 3 (RMON-PQM) Interrupt Enable */
2990 +// {0x0150, 5, 1, 0x00}, /* XRX200_BM_IER_CNT2 Counter Group 2 (RMON-SCHEDULER) Interrupt Enable */
2991 +// {0x0150, 4, 1, 0x00}, /* XRX200_BM_IER_CNT1 Counter Group 1 (RMON-QFETCH) Interrupt Enable */
2992 +// {0x0150, 3, 1, 0x00}, /* XRX200_BM_IER_CNT0 Counter Group 0 (RMON-QSTOR) Interrupt Enable */
2993 +// {0x0150, 2, 1, 0x00}, /* XRX200_BM_IER_DEQ PQM dequeue Interrupt Enable */
2994 +// {0x0150, 1, 1, 0x00}, /* XRX200_BM_IER_ENQ PQM Enqueue Interrupt Enable */
2995 +// {0x0150, 0, 1, 0x00}, /* XRX200_BM_IER_FSQM Buffer Empty Interrupt Enable */
2996 +// {0x0154, 0, 16, 0x00}, /* XRX200_BM_ISR Buffer Manager Global InterruptStatus Register */
2997 +// {0x0154, 7, 1, 0x00}, /* XRX200_BM_ISR_CNT4 Counter Group 4 Interrupt */
2998 +// {0x0154, 6, 1, 0x00}, /* XRX200_BM_ISR_CNT3 Counter Group 3 Interrupt */
2999 +// {0x0154, 5, 1, 0x00}, /* XRX200_BM_ISR_CNT2 Counter Group 2 Interrupt */
3000 +// {0x0154, 4, 1, 0x00}, /* XRX200_BM_ISR_CNT1 Counter Group 1 Interrupt */
3001 +// {0x0154, 3, 1, 0x00}, /* XRX200_BM_ISR_CNT0 Counter Group 0 Interrupt */
3002 +// {0x0154, 2, 1, 0x00}, /* XRX200_BM_ISR_DEQ PQM dequeue Interrupt Enable */
3003 +// {0x0154, 1, 1, 0x00}, /* XRX200_BM_ISR_ENQ PQM Enqueue Interrupt */
3004 +// {0x0154, 0, 1, 0x00}, /* XRX200_BM_ISR_FSQM Buffer Empty Interrupt */
3005 +// {0x0158, 0, 16, 0x00}, /* XRX200_BM_CISEL Buffer Manager RMON CounterInterrupt Select Register */
3006 +// {0x0158, 0, 3, 0x00}, /* XRX200_BM_CISEL_PORT Port Number */
3007 +// {0x015C, 0, 16, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG Debug Control Register */
3008 +// {0x015C, 0, 8, 0x00}, /* XRX200_BM_DEBUG_CTRL_DBG_SEL Select Signal for Debug Multiplexer */
3009 +// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG Debug Value Register */
3010 +// {0x0160, 0, 16, 0x00}, /* XRX200_BM_DEBUG_VAL_DBG_DAT Debug Data Value */
3011 +// {0x0200, 0, 16, 0x08}, /* XRX200_BM_PCFG Buffer Manager PortConfiguration Register */
3012 +// {0x0200, 0, 1, 0x08}, /* XRX200_BM_PCFG_CNTEN RMON Counter Enable */
3013 +// {0x0204, 0, 16, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1 Buffer ManagerRMON Control Register */
3014 +// {0x0204, 1, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM2_RES Software Reset for RMON RAM2 */
3015 +// {0x0204, 0, 1, 0x08}, /* XRX200_BM_RMON_CTRL_RAM1_RES Software Reset for RMON RAM1 */
3016 +// {0x0400, 0, 16, 0x08}, /* XRX200_PQM_DP Packet Queue ManagerDrop Probability Register */
3017 +// {0x0400, 0, 2, 0x08}, /* XRX200_PQM_DP_DPROB Drop Probability Profile */
3018 +// {0x0404, 0, 16, 0x08}, /* XRX200_PQM_RS Packet Queue ManagerRate Shaper Assignment Register */
3019 +// {0x0404, 15, 1, 0x08}, /* XRX200_PQM_RS_EN2 Rate Shaper 2 Enable */
3020 +// {0x0404, 8, 6, 0x08}, /* XRX200_PQM_RS_RS2 Rate Shaper 2 */
3021 +// {0x0404, 7, 1, 0x08}, /* XRX200_PQM_RS_EN1 Rate Shaper 1 Enable */
3022 +// {0x0404, 0, 6, 0x08}, /* XRX200_PQM_RS_RS1 Rate Shaper 1 */
3023 +// {0x0500, 0, 16, 0x14}, /* XRX200_RS_CTRL Rate Shaper ControlRegister */
3024 +// {0x0500, 0, 1, 0x14}, /* XRX200_RS_CTRL_RSEN Rate Shaper Enable */
3025 +// {0x0504, 0, 16, 0x14}, /* XRX200_RS_CBS Rate Shaper CommittedBurst Size Register */
3026 +// {0x0504, 0, 10, 0x14}, /* XRX200_RS_CBS_CBS Committed Burst Size */
3027 +// {0x0508, 0, 16, 0x14}, /* XRX200_RS_IBS Rate Shaper InstantaneousBurst Size Register */
3028 +// {0x0508, 0, 2, 0x14}, /* XRX200_RS_IBS_IBS Instantaneous Burst Size */
3029 +// {0x050C, 0, 16, 0x14}, /* XRX200_RS_CIR_EXP Rate Shaper RateExponent Register */
3030 +// {0x050C, 0, 4, 0x14}, /* XRX200_RS_CIR_EXP_EXP Exponent */
3031 +// {0x0510, 0, 16, 0x14}, /* XRX200_RS_CIR_MANT Rate Shaper RateMantissa Register */
3032 +// {0x0510, 0, 10, 0x14}, /* XRX200_RS_CIR_MANT_MANT Mantissa */
3033 + {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7 Table Key Data 7 */
3034 +// {0x1100, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_7_KEY7 Key Value[15:0] */
3035 + {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6 Table Key Data 6 */
3036 +// {0x1104, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_6_KEY6 Key Value[15:0] */
3037 + {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5 Table Key Data 5 */
3038 +// {0x1108, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_5_KEY5 Key Value[15:0] */
3039 + {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4 Table Key Data 4 */
3040 +// {0x110C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_4_KEY4 Key Value[15:0] */
3041 + {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3 Table Key Data 3 */
3042 +// {0x1110, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_3_KEY3 Key Value[15:0] */
3043 + {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2 Table Key Data 2 */
3044 +// {0x1114, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_2_KEY2 Key Value[15:0] */
3045 + {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1 Table Key Data 1 */
3046 +// {0x1118, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_1_KEY1 Key Value[31:16] */
3047 + {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0 Table Key Data 0 */
3048 +// {0x111C, 0, 16, 0x00}, /* XRX200_PCE_TBL_KEY_0_KEY0 Key Value[15:0] */
3049 + {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0 Table Mask Write Register0 */
3050 +// {0x1120, 0, 16, 0x00}, /* XRX200_PCE_TBL_MASK_0_MASK0 Mask Pattern [15:0] */
3051 + {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4 Table Value Register4 */
3052 +// {0x1124, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_4_VAL4 Data value [15:0] */
3053 + {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3 Table Value Register3 */
3054 +// {0x1128, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_3_VAL3 Data value [15:0] */
3055 + {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2 Table Value Register2 */
3056 +// {0x112C, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_2_VAL2 Data value [15:0] */
3057 + {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1 Table Value Register1 */
3058 +// {0x1130, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_1_VAL1 Data value [15:0] */
3059 + {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0 Table Value Register0 */
3060 +// {0x1134, 0, 16, 0x00}, /* XRX200_PCE_TBL_VAL_0_VAL0 Data value [15:0] */
3061 +// {0x1138, 0, 16, 0x00}, /* XRX200_PCE_TBL_ADDR Table Entry AddressRegister */
3062 + {0x1138, 0, 11, 0x00}, /* XRX200_PCE_TBL_ADDR_ADDR Table Address */
3063 +// {0x113C, 0, 16, 0x00}, /* XRX200_PCE_TBL_CTRL Table Access ControlRegister */
3064 + {0x113C, 15, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_BAS Access Busy/Access Start */
3065 + {0x113C, 13, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_TYPE Lookup Entry Type */
3066 + {0x113C, 12, 1, 0x00}, /* XRX200_PCE_TBL_CTRL_VLD Lookup Entry Valid */
3067 + {0x113C, 7, 4, 0x00}, /* XRX200_PCE_TBL_CTRL_GMAP Group Map */
3068 + {0x113C, 5, 2, 0x00}, /* XRX200_PCE_TBL_CTRL_OPMOD Lookup Table Access Operation Mode */
3069 + {0x113C, 0, 5, 0x00}, /* XRX200_PCE_TBL_CTRL_ADDR Lookup Table Address */
3070 +// {0x1140, 0, 16, 0x00}, /* XRX200_PCE_TBL_STAT Table General StatusRegister */
3071 +// {0x1140, 2, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TBUSY Table Access Busy */
3072 +// {0x1140, 1, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TEMPT Table Empty */
3073 +// {0x1140, 0, 1, 0x00}, /* XRX200_PCE_TBL_STAT_TFUL Table Full */
3074 +// {0x1144, 0, 16, 0x00}, /* XRX200_PCE_AGE_0 Aging Counter ConfigurationRegister 0 */
3075 +// {0x1144, 0, 4, 0x00}, /* XRX200_PCE_AGE_0_EXP Aging Counter Exponent Value */
3076 +// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1 Aging Counter ConfigurationRegister 1 */
3077 +// {0x1148, 0, 16, 0x00}, /* XRX200_PCE_AGE_1_MANT Aging Counter Mantissa Value */
3078 +// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1 Port Map Register 1 */
3079 +// {0x114C, 0, 16, 0x00}, /* XRX200_PCE_PMAP_1_MPMAP Monitoring Port Map */
3080 +// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2 Port Map Register 2 */
3081 +// {0x1150, 0, 16, 0x00}, /* XRX200_PCE_PMAP_2_DMCPMAP Default Multicast Port Map */
3082 +// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3 Port Map Register 3 */
3083 +// {0x1154, 0, 16, 0x00}, /* XRX200_PCE_PMAP_3_UUCMAP Default Unknown Unicast Port Map */
3084 +// {0x1158, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_0 PCE Global Control Register0 */
3085 +// {0x1158, 15, 1, 0x00}, /* XRX200_PCE_GCTRL_0_IGMP IGMP Mode Selection */
3086 + {0x1158, 14, 1, 0x00}, /* XRX200_PCE_GCTRL_0_VLAN VLAN-aware Switching */
3087 +// {0x1158, 13, 1, 0x00}, /* XRX200_PCE_GCTRL_0_NOPM No Port Map Forwarding */
3088 +// {0x1158, 12, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONUC Unknown Unicast Storm Control */
3089 +// {0x1158, 11, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMC Multicast Storm Control */
3090 +// {0x1158, 10, 1, 0x00}, /* XRX200_PCE_GCTRL_0_SCONBC Broadcast Storm Control */
3091 +// {0x1158, 8, 2, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMOD Storm Control Mode */
3092 +// {0x1158, 4, 4, 0x00}, /* XRX200_PCE_GCTRL_0_SCONMET Storm Control Metering Instance */
3093 +// {0x1158, 3, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MC_VALID Access Request */
3094 +// {0x1158, 2, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLCKMOD Port Lock Mode */
3095 +// {0x1158, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_0_PLIMMOD MAC Address Learning Limitation Mode */
3096 +// {0x1158, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_0_MTFL MAC Table Flushing */
3097 +// {0x115C, 0, 16, 0x00}, /* XRX200_PCE_GCTRL_1 PCE Global Control Register1 */
3098 +// {0x115C, 1, 1, 0x00}, /* XRX200_PCE_GCTRL_1_PCE_DIS PCE Disable after currently processed packet */
3099 +// {0x115C, 0, 1, 0x00}, /* XRX200_PCE_GCTRL_1_LRNMOD MAC Address Learning Mode */
3100 +// {0x1160, 0, 16, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL Three-color MarkerGlobal Control Register */
3101 +// {0x1160, 6, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPRED Re-marking Drop Precedence Red Encoding */
3102 +// {0x1160, 3, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPYEL Re-marking Drop Precedence Yellow Encoding */
3103 +// {0x1160, 0, 3, 0x00}, /* XRX200_PCE_TCM_GLOB_CTRL_DPGRN Re-marking Drop Precedence Green Encoding */
3104 +// {0x1164, 0, 16, 0x00}, /* XRX200_PCE_IGMP_CTRL IGMP Control Register */
3105 +// {0x1164, 15, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FAGEEN Force Aging of Table Entries Enable */
3106 +// {0x1164, 14, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_FLEAVE Fast Leave Enable */
3107 +// {0x1164, 13, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRTEN Default Maximum Response Time Enable */
3108 +// {0x1164, 12, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_JASUP Join Aggregation Suppression Enable */
3109 +// {0x1164, 11, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_REPSUP Report Suppression Enable */
3110 +// {0x1164, 10, 1, 0x00}, /* XRX200_PCE_IGMP_CTRL_SRPEN Snooping of Router Port Enable */
3111 +// {0x1164, 8, 2, 0x00}, /* XRX200_PCE_IGMP_CTRL_ROB Robustness Variable */
3112 +// {0x1164, 0, 8, 0x00}, /* XRX200_PCE_IGMP_CTRL_DMRT IGMP Default Maximum Response Time */
3113 +// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM IGMP Default RouterPort Map Register */
3114 +// {0x1168, 0, 16, 0x00}, /* XRX200_PCE_IGMP_DRPM_DRPM IGMP Default Router Port Map */
3115 +// {0x116C, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_0 IGMP Aging Register0 */
3116 +// {0x116C, 3, 8, 0x00}, /* XRX200_PCE_IGMP_AGE_0_MANT IGMP Group Aging Time Mantissa */
3117 +// {0x116C, 0, 3, 0x00}, /* XRX200_PCE_IGMP_AGE_0_EXP IGMP Group Aging Time Exponent */
3118 +// {0x1170, 0, 16, 0x00}, /* XRX200_PCE_IGMP_AGE_1 IGMP Aging Register1 */
3119 +// {0x1170, 0, 12, 0x00}, /* XRX200_PCE_IGMP_AGE_1_MANT IGMP Router Port Aging Time Mantissa */
3120 +// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT IGMP Status Register */
3121 +// {0x1174, 0, 16, 0x00}, /* XRX200_PCE_IGMP_STAT_IGPM IGMP Port Map */
3122 +// {0x1178, 0, 16, 0x00}, /* XRX200_WOL_GLB_CTRL Wake-on-LAN ControlRegister */
3123 +// {0x1178, 0, 1, 0x00}, /* XRX200_WOL_GLB_CTRL_PASSEN WoL Password Enable */
3124 +// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0 Wake-on-LAN DestinationAddress Register 0 */
3125 +// {0x117C, 0, 16, 0x00}, /* XRX200_WOL_DA_0_DA0 WoL Destination Address [15:0] */
3126 +// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1 Wake-on-LAN DestinationAddress Register 1 */
3127 +// {0x1180, 0, 16, 0x00}, /* XRX200_WOL_DA_1_DA1 WoL Destination Address [31:16] */
3128 +// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2 Wake-on-LAN DestinationAddress Register 2 */
3129 +// {0x1184, 0, 16, 0x00}, /* XRX200_WOL_DA_2_DA2 WoL Destination Address [47:32] */
3130 +// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0 Wake-on-LAN Password Register0 */
3131 +// {0x1188, 0, 16, 0x00}, /* XRX200_WOL_PW_0_PW0 WoL Password [15:0] */
3132 +// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1 Wake-on-LAN Password Register1 */
3133 +// {0x118C, 0, 16, 0x00}, /* XRX200_WOL_PW_1_PW1 WoL Password [31:16] */
3134 +// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2 Wake-on-LAN Password Register2 */
3135 +// {0x1190, 0, 16, 0x00}, /* XRX200_WOL_PW_2_PW2 WoL Password [47:32] */
3136 +// {0x1194, 0, 16, 0x00}, /* XRX200_PCE_IER_0_PINT Parser and ClassificationEngine Global Interrupt Enable Register 0 */
3137 +// {0x1194, 15, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_15 Port Interrupt Enable */
3138 +// {0x1194, 14, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_14 Port Interrupt Enable */
3139 +// {0x1194, 13, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_13 Port Interrupt Enable */
3140 +// {0x1194, 12, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_12 Port Interrupt Enable */
3141 +// {0x1194, 11, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_11 Port Interrupt Enable */
3142 +// {0x1194, 10, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_10 Port Interrupt Enable */
3143 +// {0x1194, 9, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_9 Port Interrupt Enable */
3144 +// {0x1194, 8, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_8 Port Interrupt Enable */
3145 +// {0x1194, 7, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_7 Port Interrupt Enable */
3146 +// {0x1194, 6, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_6 Port Interrupt Enable */
3147 +// {0x1194, 5, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_5 Port Interrupt Enable */
3148 +// {0x1194, 4, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_4 Port Interrupt Enable */
3149 +// {0x1194, 3, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_3 Port Interrupt Enable */
3150 +// {0x1194, 2, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_2 Port Interrupt Enable */
3151 +// {0x1194, 1, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_1 Port Interrupt Enable */
3152 +// {0x1194, 0, 1, 0x00}, /* XRX200_PCE_IER_0_PINT_0 Port Interrupt Enable */
3153 +// {0x1198, 0, 16, 0x00}, /* XRX200_PCE_IER_1 Parser and ClassificationEngine Global Interrupt Enable Register 1 */
3154 +// {0x1198, 6, 1, 0x00}, /* XRX200_PCE_IER_1_FLOWINT Traffic Flow Table Interrupt Rule matched Interrupt Enable */
3155 +// {0x1198, 5, 1, 0x00}, /* XRX200_PCE_IER_1_CPH2 Classification Phase 2 Ready Interrupt Enable */
3156 +// {0x1198, 4, 1, 0x00}, /* XRX200_PCE_IER_1_CPH1 Classification Phase 1 Ready Interrupt Enable */
3157 +// {0x1198, 3, 1, 0x00}, /* XRX200_PCE_IER_1_CPH0 Classification Phase 0 Ready Interrupt Enable */
3158 +// {0x1198, 2, 1, 0x00}, /* XRX200_PCE_IER_1_PRDY Parser Ready Interrupt Enable */
3159 +// {0x1198, 1, 1, 0x00}, /* XRX200_PCE_IER_1_IGTF IGMP Table Full Interrupt Enable */
3160 +// {0x1198, 0, 1, 0x00}, /* XRX200_PCE_IER_1_MTF MAC Table Full Interrupt Enable */
3161 +// {0x119C, 0, 16, 0x00}, /* XRX200_PCE_ISR_0_PINT Parser and ClassificationEngine Global Interrupt Status Register 0 */
3162 +// {0x119C, 15, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_15 Port Interrupt */
3163 +// {0x119C, 14, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_14 Port Interrupt */
3164 +// {0x119C, 13, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_13 Port Interrupt */
3165 +// {0x119C, 12, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_12 Port Interrupt */
3166 +// {0x119C, 11, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_11 Port Interrupt */
3167 +// {0x119C, 10, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_10 Port Interrupt */
3168 +// {0x119C, 9, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_9 Port Interrupt */
3169 +// {0x119C, 8, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_8 Port Interrupt */
3170 +// {0x119C, 7, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_7 Port Interrupt */
3171 +// {0x119C, 6, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_6 Port Interrupt */
3172 +// {0x119C, 5, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_5 Port Interrupt */
3173 +// {0x119C, 4, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_4 Port Interrupt */
3174 +// {0x119C, 3, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_3 Port Interrupt */
3175 +// {0x119C, 2, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_2 Port Interrupt */
3176 +// {0x119C, 1, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_1 Port Interrupt */
3177 +// {0x119C, 0, 1, 0x00}, /* XRX200_PCE_ISR_0_PINT_0 Port Interrupt */
3178 +// {0x11A0, 0, 16, 0x00}, /* XRX200_PCE_ISR_1 Parser and ClassificationEngine Global Interrupt Status Register 1 */
3179 +// {0x11A0, 6, 1, 0x00}, /* XRX200_PCE_ISR_1_FLOWINT Traffic Flow Table Interrupt Rule matched */
3180 +// {0x11A0, 5, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH2 Classification Phase 2 Ready Interrupt */
3181 +// {0x11A0, 4, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH1 Classification Phase 1 Ready Interrupt */
3182 +// {0x11A0, 3, 1, 0x00}, /* XRX200_PCE_ISR_1_CPH0 Classification Phase 0 Ready Interrupt */
3183 +// {0x11A0, 2, 1, 0x00}, /* XRX200_PCE_ISR_1_PRDY Parser Ready Interrupt */
3184 +// {0x11A0, 1, 1, 0x00}, /* XRX200_PCE_ISR_1_IGTF IGMP Table Full Interrupt */
3185 +// {0x11A0, 0, 1, 0x00}, /* XRX200_PCE_ISR_1_MTF MAC Table Full Interrupt */
3186 +// {0x11A4, 0, 16, 0x00}, /* XRX200_PARSER_STAT_FIFO Parser Status Register */
3187 +// {0x11A4, 8, 8, 0x00}, /* XRX200_PARSER_STAT_FSM_DAT_CNT Parser FSM Data Counter */
3188 +// {0x11A4, 5, 3, 0x00}, /* XRX200_PARSER_STAT_FSM_STATE Parser FSM State */
3189 +// {0x11A4, 4, 1, 0x00}, /* XRX200_PARSER_STAT_PKT_ERR Packet error detected */
3190 +// {0x11A4, 3, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_FIN Parser FSM finished */
3191 +// {0x11A4, 2, 1, 0x00}, /* XRX200_PARSER_STAT_FSM_START Parser FSM start */
3192 +// {0x11A4, 1, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_RDY Parser FIFO ready for read. */
3193 +// {0x11A4, 0, 1, 0x00}, /* XRX200_PARSER_STAT_FIFO_FULL Parser */
3194 +// {0x1200, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_0 PCE Port ControlRegister 0 */
3195 +// {0x1200, 13, 1, 0x28}, /* XRX200_PCE_PCTRL_0_MCST Multicast Forwarding Mode Selection */
3196 +// {0x1200, 12, 1, 0x28}, /* XRX200_PCE_PCTRL_0_EGSTEN Table-based Egress Special Tag Enable */
3197 +// {0x1200, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_0_IGSTEN Ingress Special Tag Enable */
3198 +// {0x1200, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PCPEN PCP Remarking Mode */
3199 +// {0x1200, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CLPEN Class Remarking Mode */
3200 +// {0x1200, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_0_DPEN Drop Precedence Remarking Mode */
3201 +// {0x1200, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_0_CMOD Three-color Marker Color Mode */
3202 +// {0x1200, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_0_VREP VLAN Replacement Mode */
3203 + {0x1200, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_0_TVM Transparent VLAN Mode */
3204 +// {0x1200, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_0_PLOCK Port Locking Enable */
3205 +// {0x1200, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_0_AGEDIS Aging Disable */
3206 +// {0x1200, 0, 3, 0x28}, /* XRX200_PCE_PCTRL_0_PSTATE Port State */
3207 +// {0x1204, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_1 PCE Port ControlRegister 1 */
3208 +// {0x1204, 0, 8, 0x28}, /* XRX200_PCE_PCTRL_1_LRNLIM MAC Address Learning Limit */
3209 +// {0x1208, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_2 PCE Port ControlRegister 2 */
3210 +// {0x1208, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_2_DSCPMOD DSCP Mode Selection */
3211 +// {0x1208, 5, 2, 0x28}, /* XRX200_PCE_PCTRL_2_DSCP Enable DSCP to select the Class of Service */
3212 +// {0x1208, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_2_PCP Enable VLAN PCP to select the Class of Service */
3213 +// {0x1208, 0, 4, 0x28}, /* XRX200_PCE_PCTRL_2_PCLASS Port-based Traffic Class */
3214 +// {0x120C, 0, 16, 0x28}, /* XRX200_PCE_PCTRL_3_VIO PCE Port ControlRegister 3 */
3215 +// {0x120C, 11, 1, 0x28}, /* XRX200_PCE_PCTRL_3_EDIR Egress Redirection Mode */
3216 +// {0x120C, 10, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXDMIR Receive Mirroring Enable for dropped frames */
3217 +// {0x120C, 9, 1, 0x28}, /* XRX200_PCE_PCTRL_3_RXVMIR Receive Mirroring Enable for valid frames */
3218 +// {0x120C, 8, 1, 0x28}, /* XRX200_PCE_PCTRL_3_TXMIR Transmit Mirroring Enable */
3219 +// {0x120C, 7, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_7 Violation Type 7 Mirroring Enable */
3220 +// {0x120C, 6, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_6 Violation Type 6 Mirroring Enable */
3221 +// {0x120C, 5, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_5 Violation Type 5 Mirroring Enable */
3222 +// {0x120C, 4, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_4 Violation Type 4 Mirroring Enable */
3223 +// {0x120C, 3, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_3 Violation Type 3 Mirroring Enable */
3224 +// {0x120C, 2, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_2 Violation Type 2 Mirroring Enable */
3225 +// {0x120C, 1, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_1 Violation Type 1 Mirroring Enable */
3226 +// {0x120C, 0, 1, 0x28}, /* XRX200_PCE_PCTRL_3_VIO_0 Violation Type 0 Mirroring Enable */
3227 +// {0x1210, 0, 16, 0x28}, /* XRX200_WOL_CTRL Wake-on-LAN ControlRegister */
3228 +// {0x1210, 0, 1, 0x28}, /* XRX200_WOL_CTRL_PORT WoL Enable */
3229 +// {0x1214, 0, 16, 0x28}, /* XRX200_PCE_VCTRL PCE VLAN ControlRegister */
3230 + {0x1214, 5, 1, 0x28}, /* XRX200_PCE_VCTRL_VSR VLAN Security Rule */
3231 + {0x1214, 4, 1, 0x28}, /* XRX200_PCE_VCTRL_VEMR VLAN Egress Member Violation Rule */
3232 + {0x1214, 3, 1, 0x28}, /* XRX200_PCE_VCTRL_VIMR VLAN Ingress Member Violation Rule */
3233 + {0x1214, 1, 2, 0x28}, /* XRX200_PCE_VCTRL_VINR VLAN Ingress Tag Rule */
3234 + {0x1214, 0, 1, 0x28}, /* XRX200_PCE_VCTRL_UVR Unknown VLAN Rule */
3235 +// {0x1218, 0, 16, 0x28}, /* XRX200_PCE_DEFPVID PCE Default PortVID Register */
3236 + {0x1218, 0, 6, 0x28}, /* XRX200_PCE_DEFPVID_PVID Default Port VID Index */
3237 +// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT PCE Port StatusRegister */
3238 +// {0x121C, 0, 16, 0x28}, /* XRX200_PCE_PSTAT_LRNCNT Learning Count */
3239 +// {0x1220, 0, 16, 0x28}, /* XRX200_PCE_PIER Parser and ClassificationEngine Port Interrupt Enable Register */
3240 +// {0x1220, 5, 1, 0x28}, /* XRX200_PCE_PIER_CLDRP Classification Drop Interrupt Enable */
3241 +// {0x1220, 4, 1, 0x28}, /* XRX200_PCE_PIER_PTDRP Port Drop Interrupt Enable */
3242 +// {0x1220, 3, 1, 0x28}, /* XRX200_PCE_PIER_VLAN VLAN Violation Interrupt Enable */
3243 +// {0x1220, 2, 1, 0x28}, /* XRX200_PCE_PIER_WOL Wake-on-LAN Interrupt Enable */
3244 +// {0x1220, 1, 1, 0x28}, /* XRX200_PCE_PIER_LOCK Port Limit Alert Interrupt Enable */
3245 +// {0x1220, 0, 1, 0x28}, /* XRX200_PCE_PIER_LIM Port Lock Alert Interrupt Enable */
3246 +// {0x1224, 0, 16, 0x28}, /* XRX200_PCE_PISR Parser and ClassificationEngine Port Interrupt Status Register */
3247 +// {0x1224, 5, 1, 0x28}, /* XRX200_PCE_PISR_CLDRP Classification Drop Interrupt */
3248 +// {0x1224, 4, 1, 0x28}, /* XRX200_PCE_PISR_PTDRP Port Drop Interrupt */
3249 +// {0x1224, 3, 1, 0x28}, /* XRX200_PCE_PISR_VLAN VLAN Violation Interrupt */
3250 +// {0x1224, 2, 1, 0x28}, /* XRX200_PCE_PISR_WOL Wake-on-LAN Interrupt */
3251 +// {0x1224, 1, 1, 0x28}, /* XRX200_PCE_PISR_LOCK Port Lock Alert Interrupt */
3252 +// {0x1224, 0, 1, 0x28}, /* XRX200_PCE_PISR_LIMIT Port Limitation Alert Interrupt */
3253 +// {0x1600, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CTRL Three-colorMarker Control Register */
3254 +// {0x1600, 0, 1, 0x1c}, /* XRX200_PCE_TCM_CTRL_TCMEN Three-color Marker metering instance enable */
3255 +// {0x1604, 0, 16, 0x1c}, /* XRX200_PCE_TCM_STAT Three-colorMarker Status Register */
3256 +// {0x1604, 1, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL1 Three-color Marker Alert 1 Status */
3257 +// {0x1604, 0, 1, 0x1c}, /* XRX200_PCE_TCM_STAT_AL0 Three-color Marker Alert 0 Status */
3258 +// {0x1608, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CBS Three-color MarkerCommitted Burst Size Register */
3259 +// {0x1608, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CBS_CBS Committed Burst Size */
3260 +// {0x160C, 0, 16, 0x1c}, /* XRX200_PCE_TCM_EBS Three-color MarkerExcess Burst Size Register */
3261 +// {0x160C, 0, 10, 0x1c}, /* XRX200_PCE_TCM_EBS_EBS Excess Burst Size */
3262 +// {0x1610, 0, 16, 0x1c}, /* XRX200_PCE_TCM_IBS Three-color MarkerInstantaneous Burst Size Register */
3263 +// {0x1610, 0, 2, 0x1c}, /* XRX200_PCE_TCM_IBS_IBS Instantaneous Burst Size */
3264 +// {0x1614, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT Three-colorMarker Constant Information Rate Mantissa Register */
3265 +// {0x1614, 0, 10, 0x1c}, /* XRX200_PCE_TCM_CIR_MANT_MANT Rate Counter Mantissa */
3266 +// {0x1618, 0, 16, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP Three-colorMarker Constant Information Rate Exponent Register */
3267 +// {0x1618, 0, 4, 0x1c}, /* XRX200_PCE_TCM_CIR_EXP_EXP Rate Counter Exponent */
3268 +// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST MAC Test Register */
3269 +// {0x2300, 0, 16, 0x00}, /* XRX200_MAC_TEST_JTP Jitter Test Pattern */
3270 +// {0x2304, 0, 16, 0x00}, /* XRX200_MAC_PFAD_CFG MAC Pause FrameSource Address Configuration Register */
3271 +// {0x2304, 0, 1, 0x00}, /* XRX200_MAC_PFAD_CFG_SAMOD Source Address Mode */
3272 +// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0 Pause Frame SourceAddress Part 0 */
3273 +// {0x2308, 0, 16, 0x00}, /* XRX200_MAC_PFSA_0_PFAD Pause Frame Source Address Part 0 */
3274 +// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1 Pause Frame SourceAddress Part 1 */
3275 +// {0x230C, 0, 16, 0x00}, /* XRX200_MAC_PFSA_1_PFAD Pause Frame Source Address Part 1 */
3276 +// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2 Pause Frame SourceAddress Part 2 */
3277 +// {0x2310, 0, 16, 0x00}, /* XRX200_MAC_PFSA_2_PFAD Pause Frame Source Address Part 2 */
3278 +// {0x2314, 0, 16, 0x00}, /* XRX200_MAC_FLEN MAC Frame Length Register */
3279 +// {0x2314, 0, 14, 0x00}, /* XRX200_MAC_FLEN_LEN Maximum Frame Length */
3280 +// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0 MAC VLAN EthertypeRegister 0 */
3281 +// {0x2318, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_0_OUTER Ethertype */
3282 +// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1 MAC VLAN EthertypeRegister 1 */
3283 +// {0x231C, 0, 16, 0x00}, /* XRX200_MAC_VLAN_ETYPE_1_INNER Ethertype */
3284 +// {0x2320, 0, 16, 0x00}, /* XRX200_MAC_IER MAC Interrupt EnableRegister */
3285 +// {0x2320, 0, 8, 0x00}, /* XRX200_MAC_IER_MACIEN MAC Interrupt Enable */
3286 +// {0x2324, 0, 16, 0x00}, /* XRX200_MAC_ISR MAC Interrupt StatusRegister */
3287 +// {0x2324, 0, 8, 0x00}, /* XRX200_MAC_ISR_MACINT MAC Interrupt */
3288 +// {0x2400, 0, 16, 0x30}, /* XRX200_MAC_PSTAT MAC Port Status Register */
3289 +// {0x2400, 11, 1, 0x30}, /* XRX200_MAC_PSTAT_PACT PHY Active Status */
3290 + {0x2400, 10, 1, 0x30}, /* XRX200_MAC_PSTAT_GBIT Gigabit Speed Status */
3291 + {0x2400, 9, 1, 0x30}, /* XRX200_MAC_PSTAT_MBIT Megabit Speed Status */
3292 + {0x2400, 8, 1, 0x30}, /* XRX200_MAC_PSTAT_FDUP Full Duplex Status */
3293 +// {0x2400, 7, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAU Receive Pause Status */
3294 +// {0x2400, 6, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAU Transmit Pause Status */
3295 +// {0x2400, 5, 1, 0x30}, /* XRX200_MAC_PSTAT_RXPAUEN Receive Pause Enable Status */
3296 +// {0x2400, 4, 1, 0x30}, /* XRX200_MAC_PSTAT_TXPAUEN Transmit Pause Enable Status */
3297 + {0x2400, 3, 1, 0x30}, /* XRX200_MAC_PSTAT_LSTAT Link Status */
3298 +// {0x2400, 2, 1, 0x30}, /* XRX200_MAC_PSTAT_CRS Carrier Sense Status */
3299 +// {0x2400, 1, 1, 0x30}, /* XRX200_MAC_PSTAT_TXLPI Transmit Low-power Idle Status */
3300 +// {0x2400, 0, 1, 0x30}, /* XRX200_MAC_PSTAT_RXLPI Receive Low-power Idle Status */
3301 +// {0x2404, 0, 16, 0x30}, /* XRX200_MAC_PISR MAC Interrupt Status Register */
3302 +// {0x2404, 13, 1, 0x30}, /* XRX200_MAC_PISR_PACT PHY Active Status */
3303 +// {0x2404, 12, 1, 0x30}, /* XRX200_MAC_PISR_SPEED Megabit Speed Status */
3304 +// {0x2404, 11, 1, 0x30}, /* XRX200_MAC_PISR_FDUP Full Duplex Status */
3305 +// {0x2404, 10, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUEN Receive Pause Enable Status */
3306 +// {0x2404, 9, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUEN Transmit Pause Enable Status */
3307 +// {0x2404, 8, 1, 0x30}, /* XRX200_MAC_PISR_LPIOFF Receive Low-power Idle Mode is left */
3308 +// {0x2404, 7, 1, 0x30}, /* XRX200_MAC_PISR_LPION Receive Low-power Idle Mode is entered */
3309 +// {0x2404, 6, 1, 0x30}, /* XRX200_MAC_PISR_JAM Jam Status Detected */
3310 +// {0x2404, 5, 1, 0x30}, /* XRX200_MAC_PISR_TOOSHORT Too Short Frame Error Detected */
3311 +// {0x2404, 4, 1, 0x30}, /* XRX200_MAC_PISR_TOOLONG Too Long Frame Error Detected */
3312 +// {0x2404, 3, 1, 0x30}, /* XRX200_MAC_PISR_LENERR Length Mismatch Error Detected */
3313 +// {0x2404, 2, 1, 0x30}, /* XRX200_MAC_PISR_FCSERR Frame Checksum Error Detected */
3314 +// {0x2404, 1, 1, 0x30}, /* XRX200_MAC_PISR_TXPAUSE Pause Frame Transmitted */
3315 +// {0x2404, 0, 1, 0x30}, /* XRX200_MAC_PISR_RXPAUSE Pause Frame Received */
3316 +// {0x2408, 0, 16, 0x30}, /* XRX200_MAC_PIER MAC Interrupt Enable Register */
3317 +// {0x2408, 13, 1, 0x30}, /* XRX200_MAC_PIER_PACT PHY Active Status */
3318 +// {0x2408, 12, 1, 0x30}, /* XRX200_MAC_PIER_SPEED Megabit Speed Status */
3319 +// {0x2408, 11, 1, 0x30}, /* XRX200_MAC_PIER_FDUP Full Duplex Status */
3320 +// {0x2408, 10, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUEN Receive Pause Enable Status */
3321 +// {0x2408, 9, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUEN Transmit Pause Enable Status */
3322 +// {0x2408, 8, 1, 0x30}, /* XRX200_MAC_PIER_LPIOFF Low-power Idle Off Interrupt Mask */
3323 +// {0x2408, 7, 1, 0x30}, /* XRX200_MAC_PIER_LPION Low-power Idle On Interrupt Mask */
3324 +// {0x2408, 6, 1, 0x30}, /* XRX200_MAC_PIER_JAM Jam Status Interrupt Mask */
3325 +// {0x2408, 5, 1, 0x30}, /* XRX200_MAC_PIER_TOOSHORT Too Short Frame Error Interrupt Mask */
3326 +// {0x2408, 4, 1, 0x30}, /* XRX200_MAC_PIER_TOOLONG Too Long Frame Error Interrupt Mask */
3327 +// {0x2408, 3, 1, 0x30}, /* XRX200_MAC_PIER_LENERR Length Mismatch Error Interrupt Mask */
3328 +// {0x2408, 2, 1, 0x30}, /* XRX200_MAC_PIER_FCSERR Frame Checksum Error Interrupt Mask */
3329 +// {0x2408, 1, 1, 0x30}, /* XRX200_MAC_PIER_TXPAUSE Transmit Pause Frame Interrupt Mask */
3330 +// {0x2408, 0, 1, 0x30}, /* XRX200_MAC_PIER_RXPAUSE Receive Pause Frame Interrupt Mask */
3331 +// {0x240C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_0 MAC Control Register0 */
3332 +// {0x240C, 13, 2, 0x30}, /* XRX200_MAC_CTRL_0_LCOL Late Collision Control */
3333 +// {0x240C, 12, 1, 0x30}, /* XRX200_MAC_CTRL_0_BM Burst Mode Control */
3334 +// {0x240C, 11, 1, 0x30}, /* XRX200_MAC_CTRL_0_APADEN Automatic VLAN Padding Enable */
3335 +// {0x240C, 10, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPAD2EN Stacked VLAN Padding Enable */
3336 +// {0x240C, 9, 1, 0x30}, /* XRX200_MAC_CTRL_0_VPADEN VLAN Padding Enable */
3337 +// {0x240C, 8, 1, 0x30}, /* XRX200_MAC_CTRL_0_PADEN Padding Enable */
3338 +// {0x240C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_0_FCS Transmit FCS Control */
3339 + {0x240C, 4, 3, 0x30}, /* XRX200_MAC_CTRL_0_FCON Flow Control Mode */
3340 +// {0x240C, 2, 2, 0x30}, /* XRX200_MAC_CTRL_0_FDUP Full Duplex Control */
3341 +// {0x240C, 0, 2, 0x30}, /* XRX200_MAC_CTRL_0_GMII GMII/MII interface mode selection */
3342 +// {0x2410, 0, 16, 0x30}, /* XRX200_MAC_CTRL_1 MAC Control Register1 */
3343 +// {0x2410, 8, 1, 0x30}, /* XRX200_MAC_CTRL_1_SHORTPRE Short Preamble Control */
3344 +// {0x2410, 0, 4, 0x30}, /* XRX200_MAC_CTRL_1_IPG Minimum Inter Packet Gap Size */
3345 +// {0x2414, 0, 16, 0x30}, /* XRX200_MAC_CTRL_2 MAC Control Register2 */
3346 +// {0x2414, 3, 1, 0x30}, /* XRX200_MAC_CTRL_2_MLEN Maximum Untagged Frame Length */
3347 +// {0x2414, 2, 1, 0x30}, /* XRX200_MAC_CTRL_2_LCHKL Frame Length Check Long Enable */
3348 +// {0x2414, 0, 2, 0x30}, /* XRX200_MAC_CTRL_2_LCHKS Frame Length Check Short Enable */
3349 +// {0x2418, 0, 16, 0x30}, /* XRX200_MAC_CTRL_3 MAC Control Register3 */
3350 +// {0x2418, 0, 4, 0x30}, /* XRX200_MAC_CTRL_3_RCNT Retry Count */
3351 +// {0x241C, 0, 16, 0x30}, /* XRX200_MAC_CTRL_4 MAC Control Register4 */
3352 +// {0x241C, 7, 1, 0x30}, /* XRX200_MAC_CTRL_4_LPIEN LPI Mode Enable */
3353 +// {0x241C, 0, 7, 0x30}, /* XRX200_MAC_CTRL_4_WAIT LPI Wait Time */
3354 +// {0x2420, 0, 16, 0x30}, /* XRX200_MAC_CTRL_5_PJPS MAC Control Register5 */
3355 +// {0x2420, 1, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_NOBP Prolonged Jam pattern size during no-backpressure state */
3356 +// {0x2420, 0, 1, 0x30}, /* XRX200_MAC_CTRL_5_PJPS_BP Prolonged Jam pattern size during backpressure state */
3357 +// {0x2424, 0, 16, 0x30}, /* XRX200_MAC_CTRL_6_XBUF Transmit and ReceiveBuffer Control Register */
3358 +// {0x2424, 9, 3, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_DLY_WP Delay */
3359 +// {0x2424, 8, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_INIT Receive Buffer Initialization */
3360 +// {0x2424, 6, 1, 0x30}, /* XRX200_MAC_CTRL_6_RBUF_BYPASS Bypass the Receive Buffer */
3361 +// {0x2424, 3, 3, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_DLY_WP Delay */
3362 +// {0x2424, 2, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_INIT Initialize the Transmit Buffer */
3363 +// {0x2424, 0, 1, 0x30}, /* XRX200_MAC_CTRL_6_XBUF_BYPASS Bypass the Transmit Buffer */
3364 +// {0x2428, 0, 16, 0x30}, /* XRX200_MAC_BUFST_XBUF MAC Receive and TransmitBuffer Status Register */
3365 +// {0x2428, 3, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_UFL Receive Buffer Underflow Indicator */
3366 +// {0x2428, 2, 1, 0x30}, /* XRX200_MAC_BUFST_RBUF_OFL Receive Buffer Overflow Indicator */
3367 +// {0x2428, 1, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_UFL Transmit Buffer Underflow Indicator */
3368 +// {0x2428, 0, 1, 0x30}, /* XRX200_MAC_BUFST_XBUF_OFL Transmit Buffer Overflow Indicator */
3369 +// {0x242C, 0, 16, 0x30}, /* XRX200_MAC_TESTEN MAC Test Enable Register */
3370 +// {0x242C, 2, 1, 0x30}, /* XRX200_MAC_TESTEN_JTEN Jitter Test Enable */
3371 +// {0x242C, 1, 1, 0x30}, /* XRX200_MAC_TESTEN_TXER Transmit Error Insertion */
3372 +// {0x242C, 0, 1, 0x30}, /* XRX200_MAC_TESTEN_LOOP MAC Loopback Enable */
3373 +// {0x2900, 0, 16, 0x00}, /* XRX200_FDMA_CTRL Ethernet Switch FetchDMA Control Register */
3374 +// {0x2900, 7, 5, 0x00}, /* XRX200_FDMA_CTRL_LPI_THRESHOLD Low Power Idle Threshold */
3375 +// {0x2900, 4, 3, 0x00}, /* XRX200_FDMA_CTRL_LPI_MODE Low Power Idle Mode */
3376 +// {0x2900, 2, 2, 0x00}, /* XRX200_FDMA_CTRL_EGSTAG Egress Special Tag Size */
3377 +// {0x2900, 1, 1, 0x00}, /* XRX200_FDMA_CTRL_IGSTAG Ingress Special Tag Size */
3378 +// {0x2900, 0, 1, 0x00}, /* XRX200_FDMA_CTRL_EXCOL Excessive Collision Handling */
3379 +// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE Special Tag EthertypeControl Register */
3380 +// {0x2904, 0, 16, 0x00}, /* XRX200_FDMA_STETYPE_ETYPE Special Tag Ethertype */
3381 +// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE VLAN Tag EthertypeControl Register */
3382 +// {0x2908, 0, 16, 0x00}, /* XRX200_FDMA_VTETYPE_ETYPE VLAN Tag Ethertype */
3383 +// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0 FDMA Status Register0 */
3384 +// {0x290C, 0, 16, 0x00}, /* XRX200_FDMA_STAT_0_FSMS FSM states status */
3385 +// {0x2910, 0, 16, 0x00}, /* XRX200_FDMA_IER Fetch DMA Global InterruptEnable Register */
3386 +// {0x2910, 14, 1, 0x00}, /* XRX200_FDMA_IER_PCKD Packet Drop Interrupt Enable */
3387 +// {0x2910, 13, 1, 0x00}, /* XRX200_FDMA_IER_PCKR Packet Ready Interrupt Enable */
3388 +// {0x2910, 0, 8, 0x00}, /* XRX200_FDMA_IER_PCKT Packet Sent Interrupt Enable */
3389 +// {0x2914, 0, 16, 0x00}, /* XRX200_FDMA_ISR Fetch DMA Global InterruptStatus Register */
3390 +// {0x2914, 14, 1, 0x00}, /* XRX200_FDMA_ISR_PCKTD Packet Drop */
3391 +// {0x2914, 13, 1, 0x00}, /* XRX200_FDMA_ISR_PCKR Packet is Ready for Transmission */
3392 +// {0x2914, 0, 8, 0x00}, /* XRX200_FDMA_ISR_PCKT Packet Sent Event */
3393 +// {0x2A00, 0, 16, 0x18}, /* XRX200_FDMA_PCTRL Ethernet SwitchFetch DMA Port Control Register */
3394 +// {0x2A00, 3, 2, 0x18}, /* XRX200_FDMA_PCTRL_VLANMOD VLAN Modification Enable */
3395 +// {0x2A00, 2, 1, 0x18}, /* XRX200_FDMA_PCTRL_DSCPRM DSCP Re-marking Enable */
3396 +// {0x2A00, 1, 1, 0x18}, /* XRX200_FDMA_PCTRL_STEN Special Tag Insertion Enable */
3397 +// {0x2A00, 0, 1, 0x18}, /* XRX200_FDMA_PCTRL_EN FDMA Port Enable */
3398 +// {0x2A04, 0, 16, 0x18}, /* XRX200_FDMA_PRIO Ethernet SwitchFetch DMA Port Priority Register */
3399 +// {0x2A04, 0, 2, 0x18}, /* XRX200_FDMA_PRIO_PRIO FDMA PRIO */
3400 +// {0x2A08, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT0 Ethernet SwitchFetch DMA Port Status Register 0 */
3401 +// {0x2A08, 15, 1, 0x18}, /* XRX200_FDMA_PSTAT0_PKT_AVAIL Port Egress Packet Available */
3402 +// {0x2A08, 14, 1, 0x18}, /* XRX200_FDMA_PSTAT0_POK Port Status OK */
3403 +// {0x2A08, 0, 6, 0x18}, /* XRX200_FDMA_PSTAT0_PSEG Port Egress Segment Count */
3404 +// {0x2A0C, 0, 16, 0x18}, /* XRX200_FDMA_PSTAT1_HDR Ethernet SwitchFetch DMA Port Status Register 1 */
3405 +// {0x2A0C, 0, 10, 0x18}, /* XRX200_FDMA_PSTAT1_HDR_PTR Header Pointer */
3406 +// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0 Egress TimeStamp Register 0 */
3407 +// {0x2A10, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP0_TSTL Time Stamp [15:0] */
3408 +// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1 Egress TimeStamp Register 1 */
3409 +// {0x2A14, 0, 16, 0x18}, /* XRX200_FDMA_TSTAMP1_TSTH Time Stamp [31:16] */
3410 +// {0x2D00, 0, 16, 0x00}, /* XRX200_SDMA_CTRL Ethernet Switch StoreDMA Control Register */
3411 +// {0x2D00, 0, 1, 0x00}, /* XRX200_SDMA_CTRL_TSTEN Time Stamp Enable */
3412 +// {0x2D04, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR1 SDMA Flow Control Threshold1 Register */
3413 +// {0x2D04, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR1_THR1 Threshold 1 */
3414 +// {0x2D08, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR2 SDMA Flow Control Threshold2 Register */
3415 +// {0x2D08, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR2_THR2 Threshold 2 */
3416 +// {0x2D0C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR3 SDMA Flow Control Threshold3 Register */
3417 +// {0x2D0C, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR3_THR3 Threshold 3 */
3418 +// {0x2D10, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR4 SDMA Flow Control Threshold4 Register */
3419 +// {0x2D10, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR4_THR4 Threshold 4 */
3420 +// {0x2D14, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR5 SDMA Flow Control Threshold5 Register */
3421 +// {0x2D14, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR5_THR5 Threshold 5 */
3422 +// {0x2D18, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR6 SDMA Flow Control Threshold6 Register */
3423 +// {0x2D18, 0, 10, 0x00}, /* XRX200_SDMA_FCTHR6_THR6 Threshold 6 */
3424 +// {0x2D1C, 0, 16, 0x00}, /* XRX200_SDMA_FCTHR7 SDMA Flow Control Threshold7 Register */
3425 +// {0x2D1C, 0, 11, 0x00}, /* XRX200_SDMA_FCTHR7_THR7 Threshold 7 */
3426 +// {0x2D20, 0, 16, 0x00}, /* XRX200_SDMA_STAT_0 SDMA Status Register0 */
3427 +// {0x2D20, 4, 3, 0x00}, /* XRX200_SDMA_STAT_0_BPS_FILL Back Pressure Status */
3428 +// {0x2D20, 2, 2, 0x00}, /* XRX200_SDMA_STAT_0_BPS_PNT Back Pressure Status */
3429 +// {0x2D20, 0, 2, 0x00}, /* XRX200_SDMA_STAT_0_DROP Back Pressure Status */
3430 +// {0x2D24, 0, 16, 0x00}, /* XRX200_SDMA_STAT_1 SDMA Status Register1 */
3431 +// {0x2D24, 0, 10, 0x00}, /* XRX200_SDMA_STAT_1_FILL Buffer Filling Level */
3432 +// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2 SDMA Status Register2 */
3433 +// {0x2D28, 0, 16, 0x00}, /* XRX200_SDMA_STAT_2_FSMS FSM states status */
3434 +// {0x2D2C, 0, 16, 0x00}, /* XRX200_SDMA_IER SDMA Interrupt Enable Register */
3435 +// {0x2D2C, 15, 1, 0x00}, /* XRX200_SDMA_IER_BPEX Buffer Pointers Exceeded */
3436 +// {0x2D2C, 14, 1, 0x00}, /* XRX200_SDMA_IER_BFULL Buffer Full */
3437 +// {0x2D2C, 13, 1, 0x00}, /* XRX200_SDMA_IER_FERR Frame Error */
3438 +// {0x2D2C, 0, 8, 0x00}, /* XRX200_SDMA_IER_FRX Frame Received Successfully */
3439 +// {0x2D30, 0, 16, 0x00}, /* XRX200_SDMA_ISR SDMA Interrupt Status Register */
3440 +// {0x2D30, 15, 1, 0x00}, /* XRX200_SDMA_ISR_BPEX Packet Descriptors Exceeded */
3441 +// {0x2D30, 14, 1, 0x00}, /* XRX200_SDMA_ISR_BFULL Buffer Full */
3442 +// {0x2D30, 13, 1, 0x00}, /* XRX200_SDMA_ISR_FERR Frame Error */
3443 +// {0x2D30, 0, 8, 0x00}, /* XRX200_SDMA_ISR_FRX Frame Received Successfully */
3444 +// {0x2F00, 0, 16, 0x18}, /* XRX200_SDMA_PCTRL Ethernet SwitchStore DMA Port Control Register */
3445 +// {0x2F00, 13, 2, 0x18}, /* XRX200_SDMA_PCTRL_DTHR Drop Threshold Selection */
3446 +// {0x2F00, 11, 2, 0x18}, /* XRX200_SDMA_PCTRL_PTHR Pause Threshold Selection */
3447 +// {0x2F00, 10, 1, 0x18}, /* XRX200_SDMA_PCTRL_PHYEFWD Forward PHY Error Frames */
3448 +// {0x2F00, 9, 1, 0x18}, /* XRX200_SDMA_PCTRL_ALGFWD Forward Alignment Error Frames */
3449 +// {0x2F00, 8, 1, 0x18}, /* XRX200_SDMA_PCTRL_LENFWD Forward Length Errored Frames */
3450 +// {0x2F00, 7, 1, 0x18}, /* XRX200_SDMA_PCTRL_OSFWD Forward Oversized Frames */
3451 +// {0x2F00, 6, 1, 0x18}, /* XRX200_SDMA_PCTRL_USFWD Forward Undersized Frames */
3452 +// {0x2F00, 5, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSIGN Ignore FCS Errors */
3453 +// {0x2F00, 4, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCSFWD Forward FCS Errored Frames */
3454 +// {0x2F00, 3, 1, 0x18}, /* XRX200_SDMA_PCTRL_PAUFWD Pause Frame Forwarding */
3455 +// {0x2F00, 2, 1, 0x18}, /* XRX200_SDMA_PCTRL_MFCEN Metering Flow Control Enable */
3456 +// {0x2F00, 1, 1, 0x18}, /* XRX200_SDMA_PCTRL_FCEN Flow Control Enable */
3457 +// {0x2F00, 0, 1, 0x18}, /* XRX200_SDMA_PCTRL_PEN Port Enable */
3458 +// {0x2F04, 0, 16, 0x18}, /* XRX200_SDMA_PRIO Ethernet SwitchStore DMA Port Priority Register */
3459 +// {0x2F04, 0, 2, 0x18}, /* XRX200_SDMA_PRIO_PRIO SDMA PRIO */
3460 +// {0x2F08, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT0_HDR Ethernet SwitchStore DMA Port Status Register 0 */
3461 +// {0x2F08, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT0_HDR_PTR Port Ingress Queue Header Pointer */
3462 +// {0x2F0C, 0, 16, 0x18}, /* XRX200_SDMA_PSTAT1 Ethernet SwitchStore DMA Port Status Register 1 */
3463 +// {0x2F0C, 0, 10, 0x18}, /* XRX200_SDMA_PSTAT1_PPKT Port Ingress Packet Count */
3464 +// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0 Ingress TimeStamp Register 0 */
3465 +// {0x2F10, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP0_TSTL Time Stamp [15:0] */
3466 +// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1 Ingress TimeStamp Register 1 */
3467 +// {0x2F14, 0, 16, 0x18}, /* XRX200_SDMA_TSTAMP1_TSTH Time Stamp [31:16] */
3468 +};
3469 +
3470 +
Staging tree of Mathias Kresin