b675ad0c4a8abf5b837766cc73b7b4de796c9803
[openwrt/staging/mkresin.git] / target / linux / ramips / files-4.9 / drivers / net / ethernet / mtk / gsw_mt7620.c
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/types.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_device.h>
20 #include <linux/of_irq.h>
21
22 #include <ralink_regs.h>
23
24 #include "mtk_eth_soc.h"
25 #include "gsw_mt7620.h"
26
27 void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
28 {
29 iowrite32(val, gsw->base + reg);
30 }
31
32 u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
33 {
34 return ioread32(gsw->base + reg);
35 }
36
37 static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
38 {
39 struct fe_priv *priv = (struct fe_priv *)_priv;
40 struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
41 u32 status;
42 int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
43
44 status = mtk_switch_r32(gsw, GSW_REG_ISR);
45 if (status & PORT_IRQ_ST_CHG)
46 for (i = 0; i <= max; i++) {
47 u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
48 int link = status & 0x1;
49
50 if (link != priv->link[i])
51 mt7620_print_link_state(priv, i, link,
52 (status >> 2) & 3,
53 (status & 0x2));
54
55 priv->link[i] = link;
56 }
57 mt7620_handle_carrier(priv);
58 mtk_switch_w32(gsw, status, GSW_REG_ISR);
59
60 return IRQ_HANDLED;
61 }
62
63 static void mt7620_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
64 {
65 u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
66
67 rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
68 mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
69
70 /* Enable MIB stats */
71 mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
72
73 if (of_property_read_bool(np, "mediatek,mt7530")) {
74 u32 val;
75
76 /* turn off ephy and set phy base addr to 12 */
77 mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
78 (0x1f << 24) | (0xc << 16),
79 GSW_REG_GPC1);
80
81 /* set MT7530 central align */
82 val = mt7530_mdio_r32(gsw, 0x7830);
83 val &= ~BIT(0);
84 val |= BIT(1);
85 mt7530_mdio_w32(gsw, 0x7830, val);
86
87 val = mt7530_mdio_r32(gsw, 0x7a40);
88 val &= ~BIT(30);
89 mt7530_mdio_w32(gsw, 0x7a40, val);
90
91 mt7530_mdio_w32(gsw, 0x7a78, 0x855);
92 } else {
93 /* global page 4 */
94 _mt7620_mii_write(gsw, 1, 31, 0x4000);
95
96 _mt7620_mii_write(gsw, 1, 17, 0x7444);
97 if (is_BGA)
98 _mt7620_mii_write(gsw, 1, 19, 0x0114);
99 else
100 _mt7620_mii_write(gsw, 1, 19, 0x0117);
101
102 _mt7620_mii_write(gsw, 1, 22, 0x10cf);
103 _mt7620_mii_write(gsw, 1, 25, 0x6212);
104 _mt7620_mii_write(gsw, 1, 26, 0x0777);
105 _mt7620_mii_write(gsw, 1, 29, 0x4000);
106 _mt7620_mii_write(gsw, 1, 28, 0xc077);
107 _mt7620_mii_write(gsw, 1, 24, 0x0000);
108
109 /* global page 3 */
110 _mt7620_mii_write(gsw, 1, 31, 0x3000);
111 _mt7620_mii_write(gsw, 1, 17, 0x4838);
112
113 /* global page 2 */
114 _mt7620_mii_write(gsw, 1, 31, 0x2000);
115 if (is_BGA) {
116 _mt7620_mii_write(gsw, 1, 21, 0x0515);
117 _mt7620_mii_write(gsw, 1, 22, 0x0053);
118 _mt7620_mii_write(gsw, 1, 23, 0x00bf);
119 _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
120 _mt7620_mii_write(gsw, 1, 25, 0x0fad);
121 _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
122 } else {
123 _mt7620_mii_write(gsw, 1, 21, 0x0517);
124 _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
125 _mt7620_mii_write(gsw, 1, 23, 0x00bf);
126 _mt7620_mii_write(gsw, 1, 24, 0x0aab);
127 _mt7620_mii_write(gsw, 1, 25, 0x00ae);
128 _mt7620_mii_write(gsw, 1, 26, 0x0fff);
129 }
130 /* global page 1 */
131 _mt7620_mii_write(gsw, 1, 31, 0x1000);
132 _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
133 }
134
135 /* global page 0 */
136 _mt7620_mii_write(gsw, 1, 31, 0x8000);
137 _mt7620_mii_write(gsw, 0, 30, 0xa000);
138 _mt7620_mii_write(gsw, 1, 30, 0xa000);
139 _mt7620_mii_write(gsw, 2, 30, 0xa000);
140 _mt7620_mii_write(gsw, 3, 30, 0xa000);
141
142 _mt7620_mii_write(gsw, 0, 4, 0x05e1);
143 _mt7620_mii_write(gsw, 1, 4, 0x05e1);
144 _mt7620_mii_write(gsw, 2, 4, 0x05e1);
145 _mt7620_mii_write(gsw, 3, 4, 0x05e1);
146
147 /* global page 2 */
148 _mt7620_mii_write(gsw, 1, 31, 0xa000);
149 _mt7620_mii_write(gsw, 0, 16, 0x1111);
150 _mt7620_mii_write(gsw, 1, 16, 0x1010);
151 _mt7620_mii_write(gsw, 2, 16, 0x1515);
152 _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
153
154 /* CPU Port6 Force Link 1G, FC ON */
155 mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
156
157 /* Set Port 6 as CPU Port */
158 mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
159
160 /* setup port 4 */
161 if (gsw->port4 == PORT4_EPHY) {
162 u32 val = rt_sysc_r32(SYSC_REG_CFG1);
163
164 val |= 3 << 14;
165 rt_sysc_w32(val, SYSC_REG_CFG1);
166 _mt7620_mii_write(gsw, 4, 30, 0xa000);
167 _mt7620_mii_write(gsw, 4, 4, 0x05e1);
168 _mt7620_mii_write(gsw, 4, 16, 0x1313);
169 pr_info("gsw: setting port4 to ephy mode\n");
170 }
171 }
172
173 static const struct of_device_id mediatek_gsw_match[] = {
174 { .compatible = "mediatek,mt7620-gsw" },
175 {},
176 };
177 MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
178
179 int mtk_gsw_init(struct fe_priv *priv)
180 {
181 struct device_node *np = priv->switch_np;
182 struct platform_device *pdev = of_find_device_by_node(np);
183 struct mt7620_gsw *gsw;
184
185 if (!pdev)
186 return -ENODEV;
187
188 if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
189 return -EINVAL;
190
191 gsw = platform_get_drvdata(pdev);
192 priv->soc->swpriv = gsw;
193
194 mt7620_hw_init(gsw, np);
195
196 if (gsw->irq) {
197 request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
198 "gsw", priv);
199 mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
200 }
201
202 return 0;
203 }
204
205 static int mt7620_gsw_probe(struct platform_device *pdev)
206 {
207 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208 const char *port4 = NULL;
209 struct mt7620_gsw *gsw;
210 struct device_node *np = pdev->dev.of_node;
211
212 gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
213 if (!gsw)
214 return -ENOMEM;
215
216 gsw->base = devm_ioremap_resource(&pdev->dev, res);
217 if (!gsw->base)
218 return -EADDRNOTAVAIL;
219
220 gsw->dev = &pdev->dev;
221
222 of_property_read_string(np, "mediatek,port4", &port4);
223 if (port4 && !strcmp(port4, "ephy"))
224 gsw->port4 = PORT4_EPHY;
225 else if (port4 && !strcmp(port4, "gmac"))
226 gsw->port4 = PORT4_EXT;
227 else
228 gsw->port4 = PORT4_EPHY;
229
230 gsw->irq = platform_get_irq(pdev, 0);
231
232 platform_set_drvdata(pdev, gsw);
233
234 return 0;
235 }
236
237 static int mt7620_gsw_remove(struct platform_device *pdev)
238 {
239 platform_set_drvdata(pdev, NULL);
240
241 return 0;
242 }
243
244 static struct platform_driver gsw_driver = {
245 .probe = mt7620_gsw_probe,
246 .remove = mt7620_gsw_remove,
247 .driver = {
248 .name = "mt7620-gsw",
249 .owner = THIS_MODULE,
250 .of_match_table = mediatek_gsw_match,
251 },
252 };
253
254 module_platform_driver(gsw_driver);
255
256 MODULE_LICENSE("GPL");
257 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
258 MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
259 MODULE_VERSION(MTK_FE_DRV_VERSION);