target/linux/ramips/patches-4.3/0503-net-next-mediatek-add-switch-driver-for-mt7620.patch

   1 From 322a9598692943961791ac6e5a3f385b379dcdc3 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Mon, 14 Dec 2015 21:23:18 +0100
   4 Subject: [PATCH 503/513] net-next: mediatek: add switch driver for mt7620
   5
   6 This driver is very basic and only provides basic init and irq support.
   7 Switchdev support for this device will follow.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  drivers/net/ethernet/mediatek/gsw_mt7620.c |  255 ++++++++++++++++++++++++++++
  12  drivers/net/ethernet/mediatek/gsw_mt7620.h |  117 +++++++++++++
  13  2 files changed, 372 insertions(+)
  14  create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7620.c
  15  create mode 100644 drivers/net/ethernet/mediatek/gsw_mt7620.h
  16
  17 --- /dev/null
  18 +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.c
  19 @@ -0,0 +1,255 @@
  20 +/*   This program is free software; you can redistribute it and/or modify
  21 + *   it under the terms of the GNU General Public License as published by
  22 + *   the Free Software Foundation; version 2 of the License
  23 + *
  24 + *   This program is distributed in the hope that it will be useful,
  25 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
  26 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27 + *   GNU General Public License for more details.
  28 + *
  29 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  30 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
  31 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  32 + */
  33 +
  34 +#include <linux/module.h>
  35 +#include <linux/kernel.h>
  36 +#include <linux/types.h>
  37 +#include <linux/platform_device.h>
  38 +#include <linux/of_device.h>
  39 +#include <linux/of_irq.h>
  40 +
  41 +#include <ralink_regs.h>
  42 +
  43 +#include "mtk_eth_soc.h"
  44 +#include "gsw_mt7620.h"
  45 +
  46 +void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
  47 +{
  48 +       iowrite32(val, gsw->base + reg);
  49 +}
  50 +
  51 +u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
  52 +{
  53 +       return ioread32(gsw->base + reg);
  54 +}
  55 +
  56 +static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
  57 +{
  58 +       struct fe_priv *priv = (struct fe_priv *)_priv;
  59 +       struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  60 +       u32 status;
  61 +       int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
  62 +
  63 +       status = mtk_switch_r32(gsw, GSW_REG_ISR);
  64 +       if (status & PORT_IRQ_ST_CHG)
  65 +               for (i = 0; i <= max; i++) {
  66 +                       u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
  67 +                       int link = status & 0x1;
  68 +
  69 +                       if (link != priv->link[i])
  70 +                               mt7620_print_link_state(priv, i, link,
  71 +                                                       (status >> 2) & 3,
  72 +                                                       (status & 0x2));
  73 +
  74 +                       priv->link[i] = link;
  75 +               }
  76 +       mtk_switch_w32(gsw, status, GSW_REG_ISR);
  77 +
  78 +       return IRQ_HANDLED;
  79 +}
  80 +
  81 +static void mt7620_hw_init(struct mt7620_gsw *gsw, struct device_node *np)
  82 +{
  83 +       u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
  84 +
  85 +       rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
  86 +       mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
  87 +
  88 +       if (of_property_read_bool(np, "mediatek,mt7530")) {
  89 +               u32 val;
  90 +
  91 +               /* turn off ephy and set phy base addr to 12 */
  92 +               mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
  93 +                       (0x1f << 24) | (0xc << 16),
  94 +                       GSW_REG_GPC1);
  95 +
  96 +               /* set MT7530 central align */
  97 +               val = mt7530_mdio_r32(gsw, 0x7830);
  98 +               val &= ~BIT(0);
  99 +               val |= BIT(1);
 100 +               mt7530_mdio_w32(gsw, 0x7830, val);
 101 +
 102 +               val = mt7530_mdio_r32(gsw, 0x7a40);
 103 +               val &= ~BIT(30);
 104 +               mt7530_mdio_w32(gsw, 0x7a40, val);
 105 +
 106 +               mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 107 +       } else {
 108 +               /* global page 4 */
 109 +               _mt7620_mii_write(gsw, 1, 31, 0x4000);
 110 +
 111 +               _mt7620_mii_write(gsw, 1, 17, 0x7444);
 112 +               if (is_BGA)
 113 +                       _mt7620_mii_write(gsw, 1, 19, 0x0114);
 114 +               else
 115 +                       _mt7620_mii_write(gsw, 1, 19, 0x0117);
 116 +
 117 +               _mt7620_mii_write(gsw, 1, 22, 0x10cf);
 118 +               _mt7620_mii_write(gsw, 1, 25, 0x6212);
 119 +               _mt7620_mii_write(gsw, 1, 26, 0x0777);
 120 +               _mt7620_mii_write(gsw, 1, 29, 0x4000);
 121 +               _mt7620_mii_write(gsw, 1, 28, 0xc077);
 122 +               _mt7620_mii_write(gsw, 1, 24, 0x0000);
 123 +
 124 +               /* global page 3 */
 125 +               _mt7620_mii_write(gsw, 1, 31, 0x3000);
 126 +               _mt7620_mii_write(gsw, 1, 17, 0x4838);
 127 +
 128 +               /* global page 2 */
 129 +               _mt7620_mii_write(gsw, 1, 31, 0x2000);
 130 +               if (is_BGA) {
 131 +                       _mt7620_mii_write(gsw, 1, 21, 0x0515);
 132 +                       _mt7620_mii_write(gsw, 1, 22, 0x0053);
 133 +                       _mt7620_mii_write(gsw, 1, 23, 0x00bf);
 134 +                       _mt7620_mii_write(gsw, 1, 24, 0x0aaf);
 135 +                       _mt7620_mii_write(gsw, 1, 25, 0x0fad);
 136 +                       _mt7620_mii_write(gsw, 1, 26, 0x0fc1);
 137 +               } else {
 138 +                       _mt7620_mii_write(gsw, 1, 21, 0x0517);
 139 +                       _mt7620_mii_write(gsw, 1, 22, 0x0fd2);
 140 +                       _mt7620_mii_write(gsw, 1, 23, 0x00bf);
 141 +                       _mt7620_mii_write(gsw, 1, 24, 0x0aab);
 142 +                       _mt7620_mii_write(gsw, 1, 25, 0x00ae);
 143 +                       _mt7620_mii_write(gsw, 1, 26, 0x0fff);
 144 +               }
 145 +               /* global page 1 */
 146 +               _mt7620_mii_write(gsw, 1, 31, 0x1000);
 147 +               _mt7620_mii_write(gsw, 1, 17, 0xe7f8);
 148 +       }
 149 +
 150 +       /* global page 0 */
 151 +       _mt7620_mii_write(gsw, 1, 31, 0x8000);
 152 +       _mt7620_mii_write(gsw, 0, 30, 0xa000);
 153 +       _mt7620_mii_write(gsw, 1, 30, 0xa000);
 154 +       _mt7620_mii_write(gsw, 2, 30, 0xa000);
 155 +       _mt7620_mii_write(gsw, 3, 30, 0xa000);
 156 +
 157 +       _mt7620_mii_write(gsw, 0, 4, 0x05e1);
 158 +       _mt7620_mii_write(gsw, 1, 4, 0x05e1);
 159 +       _mt7620_mii_write(gsw, 2, 4, 0x05e1);
 160 +       _mt7620_mii_write(gsw, 3, 4, 0x05e1);
 161 +
 162 +       /* global page 2 */
 163 +       _mt7620_mii_write(gsw, 1, 31, 0xa000);
 164 +       _mt7620_mii_write(gsw, 0, 16, 0x1111);
 165 +       _mt7620_mii_write(gsw, 1, 16, 0x1010);
 166 +       _mt7620_mii_write(gsw, 2, 16, 0x1515);
 167 +       _mt7620_mii_write(gsw, 3, 16, 0x0f0f);
 168 +
 169 +       /* CPU Port6 Force Link 1G, FC ON */
 170 +       mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
 171 +
 172 +       /* Set Port 6 as CPU Port */
 173 +       mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
 174 +
 175 +       /* setup port 4 */
 176 +       if (gsw->port4 == PORT4_EPHY) {
 177 +               u32 val = rt_sysc_r32(SYSC_REG_CFG1);
 178 +
 179 +               val |= 3 << 14;
 180 +               rt_sysc_w32(val, SYSC_REG_CFG1);
 181 +               _mt7620_mii_write(gsw, 4, 30, 0xa000);
 182 +               _mt7620_mii_write(gsw, 4, 4, 0x05e1);
 183 +               _mt7620_mii_write(gsw, 4, 16, 0x1313);
 184 +               pr_info("gsw: setting port4 to ephy mode\n");
 185 +       }
 186 +}
 187 +
 188 +static const struct of_device_id mediatek_gsw_match[] = {
 189 +       { .compatible = "mediatek,mt7620-gsw" },
 190 +       {},
 191 +};
 192 +MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
 193 +
 194 +int mtk_gsw_init(struct fe_priv *priv)
 195 +{
 196 +       struct device_node *np = priv->switch_np;
 197 +       struct platform_device *pdev = of_find_device_by_node(np);
 198 +       struct mt7620_gsw *gsw;
 199 +
 200 +       if (!pdev)
 201 +               return -ENODEV;
 202 +
 203 +       if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
 204 +               return -EINVAL;
 205 +
 206 +       gsw = platform_get_drvdata(pdev);
 207 +       priv->soc->swpriv = gsw;
 208 +
 209 +       mt7620_hw_init(gsw, np);
 210 +
 211 +       if (gsw->irq) {
 212 +               request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
 213 +                           "gsw", priv);
 214 +               mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
 215 +       }
 216 +
 217 +       return 0;
 218 +}
 219 +
 220 +static int mt7620_gsw_probe(struct platform_device *pdev)
 221 +{
 222 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 223 +       const char *port4 = NULL;
 224 +       struct mt7620_gsw *gsw;
 225 +       struct device_node *np;
 226 +
 227 +       gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
 228 +       if (!gsw)
 229 +               return -ENOMEM;
 230 +
 231 +       gsw->base = devm_ioremap_resource(&pdev->dev, res);
 232 +       if (!gsw->base)
 233 +               return -EADDRNOTAVAIL;
 234 +
 235 +       gsw->dev = &pdev->dev;
 236 +
 237 +       of_property_read_string(np, "mediatek,port4", &port4);
 238 +       if (port4 && !strcmp(port4, "ephy"))
 239 +               gsw->port4 = PORT4_EPHY;
 240 +       else if (port4 && !strcmp(port4, "gmac"))
 241 +               gsw->port4 = PORT4_EXT;
 242 +       else
 243 +               gsw->port4 = PORT4_EPHY;
 244 +
 245 +       gsw->irq = irq_of_parse_and_map(np, 0);
 246 +
 247 +       platform_set_drvdata(pdev, gsw);
 248 +
 249 +       return 0;
 250 +}
 251 +
 252 +static int mt7620_gsw_remove(struct platform_device *pdev)
 253 +{
 254 +       platform_set_drvdata(pdev, NULL);
 255 +
 256 +       return 0;
 257 +}
 258 +
 259 +static struct platform_driver gsw_driver = {
 260 +       .probe = mt7620_gsw_probe,
 261 +       .remove = mt7620_gsw_remove,
 262 +       .driver = {
 263 +               .name = "mt7620-gsw",
 264 +               .owner = THIS_MODULE,
 265 +               .of_match_table = mediatek_gsw_match,
 266 +       },
 267 +};
 268 +
 269 +module_platform_driver(gsw_driver);
 270 +
 271 +MODULE_LICENSE("GPL");
 272 +MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 273 +MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
 274 +MODULE_VERSION(MTK_FE_DRV_VERSION);
 275 --- /dev/null
 276 +++ b/drivers/net/ethernet/mediatek/gsw_mt7620.h
 277 @@ -0,0 +1,117 @@
 278 +/*   This program is free software; you can redistribute it and/or modify
 279 + *   it under the terms of the GNU General Public License as published by
 280 + *   the Free Software Foundation; version 2 of the License
 281 + *
 282 + *   This program is distributed in the hope that it will be useful,
 283 + *   but WITHOUT ANY WARRANTY; without even the implied warranty of
 284 + *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 285 + *   GNU General Public License for more details.
 286 + *
 287 + *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
 288 + *   Copyright (C) 2009-2015 Felix Fietkau <nbd@openwrt.org>
 289 + *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
 290 + */
 291 +
 292 +#ifndef _RALINK_GSW_MT7620_H__
 293 +#define _RALINK_GSW_MT7620_H__
 294 +
 295 +#define GSW_REG_PHY_TIMEOUT    (5 * HZ)
 296 +
 297 +#ifdef CONFIG_SOC_MT7621
 298 +#define MT7620A_GSW_REG_PIAC   0x0004
 299 +#else
 300 +#define MT7620A_GSW_REG_PIAC   0x7004
 301 +#endif
 302 +
 303 +#define GSW_NUM_VLANS          16
 304 +#define GSW_NUM_VIDS           4096
 305 +#define GSW_NUM_PORTS          7
 306 +#define GSW_PORT6              6
 307 +
 308 +#define GSW_MDIO_ACCESS                BIT(31)
 309 +#define GSW_MDIO_READ          BIT(19)
 310 +#define GSW_MDIO_WRITE         BIT(18)
 311 +#define GSW_MDIO_START         BIT(16)
 312 +#define GSW_MDIO_ADDR_SHIFT    20
 313 +#define GSW_MDIO_REG_SHIFT     25
 314 +
 315 +#define GSW_REG_PORT_PMCR(x)   (0x3000 + (x * 0x100))
 316 +#define GSW_REG_PORT_STATUS(x) (0x3008 + (x * 0x100))
 317 +#define GSW_REG_SMACCR0                0x3fE4
 318 +#define GSW_REG_SMACCR1                0x3fE8
 319 +#define GSW_REG_CKGCR          0x3ff0
 320 +
 321 +#define GSW_REG_IMR            0x7008
 322 +#define GSW_REG_ISR            0x700c
 323 +#define GSW_REG_GPC1           0x7014
 324 +
 325 +#define SYSC_REG_CHIP_REV_ID   0x0c
 326 +#define SYSC_REG_CFG1          0x14
 327 +#define RST_CTRL_MCM           BIT(2)
 328 +#define SYSC_PAD_RGMII2_MDIO   0x58
 329 +#define SYSC_GPIO_MODE         0x60
 330 +
 331 +#define PORT_IRQ_ST_CHG                0x7f
 332 +
 333 +#ifdef CONFIG_SOC_MT7621
 334 +#define ESW_PHY_POLLING                0x0000
 335 +#else
 336 +#define ESW_PHY_POLLING                0x7000
 337 +#endif
 338 +
 339 +#define        PMCR_IPG                BIT(18)
 340 +#define        PMCR_MAC_MODE           BIT(16)
 341 +#define        PMCR_FORCE              BIT(15)
 342 +#define        PMCR_TX_EN              BIT(14)
 343 +#define        PMCR_RX_EN              BIT(13)
 344 +#define        PMCR_BACKOFF            BIT(9)
 345 +#define        PMCR_BACKPRES           BIT(8)
 346 +#define        PMCR_RX_FC              BIT(5)
 347 +#define        PMCR_TX_FC              BIT(4)
 348 +#define        PMCR_SPEED(_x)          (_x << 2)
 349 +#define        PMCR_DUPLEX             BIT(1)
 350 +#define        PMCR_LINK               BIT(0)
 351 +
 352 +#define PHY_AN_EN              BIT(31)
 353 +#define PHY_PRE_EN             BIT(30)
 354 +#define PMY_MDC_CONF(_x)       ((_x & 0x3f) << 24)
 355 +
 356 +enum {
 357 +       /* Global attributes. */
 358 +       GSW_ATTR_ENABLE_VLAN,
 359 +       /* Port attributes. */
 360 +       GSW_ATTR_PORT_UNTAG,
 361 +};
 362 +
 363 +enum {
 364 +       PORT4_EPHY = 0,
 365 +       PORT4_EXT,
 366 +};
 367 +
 368 +struct mt7620_gsw {
 369 +       struct device           *dev;
 370 +       void __iomem            *base;
 371 +       int                     irq;
 372 +       int                     port4;
 373 +       unsigned long int       autopoll;
 374 +};
 375 +
 376 +void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
 377 +u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
 378 +int mtk_gsw_init(struct fe_priv *priv);
 379 +
 380 +int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
 381 +int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
 382 +void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
 383 +int mt7620_has_carrier(struct fe_priv *priv);
 384 +void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
 385 +                            int speed, int duplex);
 386 +
 387 +void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
 388 +u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
 389 +
 390 +u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
 391 +                            u32 phy_register, u32 write_data);
 392 +u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
 393 +
 394 +#endif