toolchain/gcc/patches/3.4.6-nonmips/001-non_mips.patch

   1 diff -urN gcc-3.4.6/gcc/config/mips/mips.c gcc-3.4.6-nonmips/gcc/config/mips/mips.c
   2 --- gcc-3.4.6/gcc/config/mips/mips.c    2005-07-31 10:35:15.000000000 +0200
   3 +++ gcc-3.4.6-nonmips/gcc/config/mips/mips.c    2006-07-19 20:25:03.000000000 +0200
   4 @@ -3466,26 +3466,26 @@
   5    for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
   6      {
   7        regs[i] = gen_reg_rtx (mode);
   8 -      if (MEM_ALIGN (src) >= bits)
   9 +      //if (MEM_ALIGN (src) >= bits)
  10         emit_move_insn (regs[i], adjust_address (src, mode, offset));
  11 -      else
  12 -       {
  13 -         rtx part = adjust_address (src, BLKmode, offset);
  14 -         if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
  15 -           abort ();
  16 -       }
  17 +      //else
  18 +       //{
  19 +         //rtx part = adjust_address (src, BLKmode, offset);
  20 +         //if (!mips_expand_unaligned_load (regs[i], part, bits, 0))
  21 +           //abort ();
  22 +       //}
  23      }
  24
  25    /* Copy the chunks to the destination.  */
  26    for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++)
  27 -    if (MEM_ALIGN (dest) >= bits)
  28 +    //if (MEM_ALIGN (dest) >= bits)
  29        emit_move_insn (adjust_address (dest, mode, offset), regs[i]);
  30 -    else
  31 -      {
  32 -       rtx part = adjust_address (dest, BLKmode, offset);
  33 -       if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
  34 -         abort ();
  35 -      }
  36 +    //else
  37 +      //{
  38 +       //rtx part = adjust_address (dest, BLKmode, offset);
  39 +       //if (!mips_expand_unaligned_store (part, regs[i], bits, 0))
  40 +         //abort ();
  41 +      //}
  42
  43    /* Mop up any left-over bytes.  */
  44    if (offset < length)
  45 @@ -4488,6 +4488,7 @@
  46  mips_expand_unaligned_load (rtx dest, rtx src, unsigned int width, int bitpos)
  47  {
  48    rtx left, right, temp;
  49 +       return false;
  50
  51    /* If TARGET_64BIT, the destination of a 32-bit load will be a
  52       paradoxical word_mode subreg.  This is the only case in which
  53 @@ -4514,8 +4515,9 @@
  54      }
  55    else
  56      {
  57 -      emit_insn (gen_mov_lwl (temp, src, left));
  58 -      emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
  59 +       return false;
  60 +      //emit_insn (gen_mov_lwl (temp, src, left));
  61 +      //emit_insn (gen_mov_lwr (dest, copy_rtx (src), right, temp));
  62      }
  63    return true;
  64  }
  65 @@ -4528,6 +4530,7 @@
  66  mips_expand_unaligned_store (rtx dest, rtx src, unsigned int width, int bitpos)
  67  {
  68    rtx left, right;
  69 +       return false;
  70
  71    if (!mips_get_unaligned_mem (&dest, width, bitpos, &left, &right))
  72      return false;
  73 @@ -4541,8 +4544,10 @@
  74      }
  75    else
  76      {
  77 -      emit_insn (gen_mov_swl (dest, src, left));
  78 -      emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
  79 +       /* Patented instructions */
  80 +      //emit_insn (gen_mov_swl (dest, src, left));
  81 +      //emit_insn (gen_mov_swr (copy_rtx (dest), copy_rtx (src), right));
  82 +       return false;
  83      }
  84    return true;
  85  }