arch/mips/ralink/mt7620.c | 21 ++++++++++++++++-----
3 files changed, 18 insertions(+), 5 deletions(-)
-diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
-index 0ef882b..455d406 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -17,6 +17,7 @@
#define SYSC_REG_CHIP_REV 0x0c
#define SYSC_REG_SYSTEM_CONFIG0 0x10
#define SYSC_REG_SYSTEM_CONFIG1 0x14
-diff --git a/arch/mips/include/asm/mach-ralink/ralink_regs.h b/arch/mips/include/asm/mach-ralink/ralink_regs.h
-index 8fcbd0f..69fbcec 100644
--- a/arch/mips/include/asm/mach-ralink/ralink_regs.h
+++ b/arch/mips/include/asm/mach-ralink/ralink_regs.h
@@ -24,6 +24,7 @@ enum ralink_soc_type {
};
extern enum ralink_soc_type ralink_soc;
-diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
-index 41b4a3e..6975ed8 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -46,6 +46,9 @@ enum mt762x_soc_type mt762x_soc;
/*
* When the CPU goes into sleep mode, the BUS clock will be too low for
* USB to function properly
-@@ -548,8 +552,15 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
+@@ -548,8 +552,15 @@ void prom_soc_init(struct ralink_soc_inf
soc_info->compatible = "ralink,mt7620n-soc";
}
} else if (n0 == MT7620_CHIP_NAME0 && n1 == MT7628_CHIP_NAME1) {
soc_info->compatible = "ralink,mt7628an-soc";
} else {
panic("mt762x: unknown SoC, n0:%08x n1:%08x\n", n0, n1);
-@@ -582,7 +593,7 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
+@@ -582,7 +593,7 @@ void prom_soc_init(struct ralink_soc_inf
pr_info("Digital PMU set to %s control\n",
(pmu1 & DIG_SW_SEL) ? ("sw") : ("hw"));
rt2880_pinmux_data = mt7628an_pinmux_data;
else
rt2880_pinmux_data = mt7620a_pinmux_data;
---
-1.7.10.4
-