ath79: fix QCA9557 eth PLL settings
authorDavid Bauer <mail@david-bauer.net>
Mon, 6 Aug 2018 14:21:02 +0000 (16:21 +0200)
committerJohn Crispin <john@phrozen.org>
Wed, 8 Aug 2018 06:38:45 +0000 (08:38 +0200)
The QCA9557 dtsi is currently missing pll-handle and pll-regs for both
eth0 and eth1, therefore PLL settings won't be applied. This commit
fixes this behavior.

Signed-off-by: David Bauer <mail@david-bauer.net>
target/linux/ath79/dts/qca9557.dtsi

index c3874bc..992ccff 100644 (file)
 
                        pll: pll-controller@18050000 {
                                compatible = "qca,ar9557-pll",
-                                               "qca,qca9550-pll";
+                                               "qca,qca9550-pll", "syscon";
                                reg = <0x18050000 0x50>;
 
                                #clock-cells = <1>;
 &eth0 {
        compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
 
+       pll-reg = <0 0x28 0>;
+       pll-handle = <&pll>;
+
        pll-data = <0x82000101 0x80000101 0x80001313>;
        phy-mode = "rgmii";
 
 &eth1 {
        compatible = "qca,qca9550-eth", "syscon", "simple-mfd";
 
+       pll-reg = <0 0x48 0>;
+       pll-handle = <&pll>;
+
        pll-data = <0x82000101 0x80000101 0x80001313>;
        phy-mode = "sgmii";