TODO: lantiq: dts: overhaul pci(e) nodes master
authorMathias Kresin <dev@kresin.me>
Tue, 29 Jan 2019 20:14:42 +0000 (21:14 +0100)
committerMathias Kresin <dev@kresin.me>
Thu, 11 Jul 2019 20:26:51 +0000 (22:26 +0200)
  - fix pci devices unit addresses
  - change pcie node label, it is the parent for two pci bridges
  - create subnodes for each pcie bus
  - disable pcie by default and enable where it wasn't disabled before
  - move the pcie reset gpio to the boards dts, if we have to overwrite
    a soc wide default, we shouldn't define a soc wide default

Signed-off-by: Mathias Kresin <dev@kresin.me>
33 files changed:
target/linux/lantiq/files/arch/mips/boot/dts/ARV7506PW11.dts
target/linux/lantiq/files/arch/mips/boot/dts/ARV7510PW22.dts
target/linux/lantiq/files/arch/mips/boot/dts/ARV7518PW.dts
target/linux/lantiq/files/arch/mips/boot/dts/ARV7519PW.dts
target/linux/lantiq/files/arch/mips/boot/dts/ARV7519RW22.dts
target/linux/lantiq/files/arch/mips/boot/dts/ARV7525PW.dts
target/linux/lantiq/files/arch/mips/boot/dts/ARV752DPW.dts
target/linux/lantiq/files/arch/mips/boot/dts/ARV752DPW22.dts
target/linux/lantiq/files/arch/mips/boot/dts/ARV8539PW22.dts
target/linux/lantiq/files/arch/mips/boot/dts/ASL56026.dts
target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV2B.dts
target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV3A.dts
target/linux/lantiq/files/arch/mips/boot/dts/BTHOMEHUBV5A.dts
target/linux/lantiq/files/arch/mips/boot/dts/DGN3500.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/DM200.dts
target/linux/lantiq/files/arch/mips/boot/dts/EASY80920.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/FRITZ3370-REV2.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7312.dts
target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7320.dts
target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7362SL.dts
target/linux/lantiq/files/arch/mips/boot/dts/FRITZ736X.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/FRITZ7412.dts
target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUF1.dts
target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUF3.dts
target/linux/lantiq/files/arch/mips/boot/dts/P2812HNUFX.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/TDW8980.dts
target/linux/lantiq/files/arch/mips/boot/dts/TDW89X0.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/VG3503J.dts
target/linux/lantiq/files/arch/mips/boot/dts/VGV7510KW22.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/VGV7519.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/VR200.dtsi
target/linux/lantiq/files/arch/mips/boot/dts/WBMR300.dts
target/linux/lantiq/files/arch/mips/boot/dts/vr9.dtsi

index 6903523..cc18607 100644 (file)
        lantiq,external-clock;
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
-       wifi@1814,3592 {
+       wifi@0,e {
                compatible = "pci1814,3592";
                reg = <0x7000 0 0 0 0>;
                ralink,mtd-eeprom = <&boardconfig 0x410>;
index b844560..27fa7e4 100644 (file)
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        req-mask = <0x3>;
 
-       wifi@1814,3592 {
+       wifi@0,e {
                compatible = "pci1814,3592";
                reg = <0x7000 0 0 0 0>;
                ralink,mtd-eeprom = <&boardconfig 0x410>;
index 3cea61f..12439a3 100644 (file)
        lantiq,external-clock;
        req-mask = <0xf>;
 
-       wifi@168c,0029 {
+       wifi@0,e {
                compatible = "pci168c,0029";
                reg = <0x7000 0 0 0 0>;
                qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */
index ad519ae..c2256da 100644 (file)
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        req-mask = <0xf>;
 
-       wifi@0,0 {
+       wifi@0,e {
                compatible = "pci0,0";
                reg = <0x7000 0 0 0 0>;
                ralink,mtd-eeprom = <&boardconfig 0x410>;
index f245fe3..060a200 100644 (file)
        };
 };
 
-&pcie0 {
+&pcie {
        status = "okay";
        gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
 };
index bcdc224..7afc771 100644 (file)
        status = "okay";
        interrupt-map = <0x7000 0 0 1 &icu0 135 1>;
 
-       wifi@0,0 {
+       wifi@0,e {
                compatible = "pci0,0";
                reg = <0x7000 0 0 0 0>;
                ralink,mtd-eeprom = <&boardconfig 0x410>;
index ed4be8d..0ffdf20 100644 (file)
        interrupt-map = <0x7000 0 0 1 &icu0 135>;
        req-mask = <0x3>;
 
-       wifi@1814,0601 {
+       wifi@0,e {
                compatible = "pci1814,0601";
                reg = <0x7000 0 0 0 0>;
                ralink,mtd-eeprom = <&boardconfig 0x410>;
index f2d571f..0819296 100644 (file)
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
        req-mask = <0x3>;
 
-       wifi@1814,3592 {
+       wifi@0,e {
                compatible = "pci1814,3592";
                reg = <0x7000 0 0 0 0>;
                ralink,mtd-eeprom = <&boardconfig 0x410>;
index 1ca655d..135eb8b 100644 (file)
        status = "okay";
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
-       wifi@168c,0029 {
+       wifi@0,e {
                compatible = "pci168c,0029";
                reg = <0x7000 0 0 0 0>;
                qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */
index 1c7f03c..7296a7e 100644 (file)
                };
        };
 };
+
+&pcie {
+       status = "okay";
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+};
index a1b66d4..7cba642 100644 (file)
        status = "okay";
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
-       wifi@168c,0027 {
+       wifi@0,e {
                compatible = "pci168c,0027";
                reg = <0x7000 0 0 0 0>;
                qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */
index 67b8a5c..1d7ebcc 100644 (file)
        status = "okay";
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
-       wifi@7000 {
+       wifi@0,e {
                reg = <0x7000 0 0 0 0>;
                qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */
        };
index 187657e..97cbdb8 100644 (file)
        status = "okay";
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
-       wifi@168c,002d {
+       wifi@0,e {
                compatible = "pci168c,002d";
                reg = <0x7000 0 0 0 0>;
                qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */
        };
 };
 
+&pcie {
+       status = "okay";
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+};
+
 &usb_phy0 {
        status = "okay";
 };
index f4f3552..eabf0d0 100644 (file)
        status = "okay";
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
-       wifi@168c,0029 {
+       wifi@0,e {
                compatible = "pci168c,0029";
                reg = <0x7000 0 0 0 0>;
                qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */
index 4796123..0055bc9 100644 (file)
        };
 };
 
-&pcie0 {
-       status = "disabled";
-};
-
 &spi {
        status = "okay";
 
index b7ccb4e..f8b1406 100644 (file)
        status = "okay";
        vbus-supply = <&usb_vbus>;
 };
+
+&pcie {
+       status = "okay";
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+};
index 8dc34a9..7ce232a 100644 (file)
        };
 };
 
-&pcie0 {
+&pcie {
+       status = "okay";
        gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
+};
 
-       pcie@0 {
+&pcie0 {
+       wifi@0,0 {
+               compatible = "pci0,0";
                reg = <0 0 0 0 0>;
-               #interrupt-cells = <1>;
-               #size-cells = <2>;
-               #address-cells = <3>;
-
-               wifi@0,0 {
-                       compatible = "pci0,0";
-                       reg = <0 0 0 0 0>;
-                       qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */
-               };
+               qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */
        };
 };
 
index 86fa250..dc944db 100644 (file)
        req-mask = <0xf>;
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
-       wifi@0,0 {
+       wifi@0,e {
                compatible = "pci0,0";
                reg = <0x7000 0 0 0 0>;
                qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */
index 6bbeb5a..4a6539d 100644 (file)
        req-mask = <0xf>;
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
-       wifi@0,0 {
+       wifi@0,e {
                compatible = "pci0,0";
                reg = <0x7000 0 0 0 0>;
                qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:00:0e.0.bin */
index cca79c9..9ab34a6 100644 (file)
                };
        };
 };
-
-&pcie0 {
-       gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;
-
-       pcie@0 {
-               #size-cells = <1>;
-               #address-cells = <2>;
-       };
-};
index e7e7510..d5aed95 100644 (file)
 
 };
 
-&pcie0 {
+&pcie {
        status = "okay";
+       gpio-reset = <&gpio 21 GPIO_ACTIVE_LOW>;
+};
 
-       pcie@0 {
+&pcie0 {
+       wifi@0,0 {
+               compatible = "pci168c,002e";
                reg = <0 0 0 0 0>;
-               #interrupt-cells = <1>;
-               #size-cells = <1>;
-               #address-cells = <2>;
-
-               wifi@168c,002e {
-                       compatible = "pci168c,002e";
-                       reg = <0 0 0 0 0>;
-                       qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */
-               };
+               qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */
        };
 };
 
index dfd13ef..31b3026 100644 (file)
        };
 };
 
-&pcie0 {
+&pcie {
        status = "okay";
        gpio-reset = <&gpio 11 GPIO_ACTIVE_HIGH>;
+};
 
-       pcie@0 {
+&pcie0 {
+       wifi@0,0 {
+               compatible = "pci168c,002e";
                reg = <0 0 0 0 0>;
-               #interrupt-cells = <1>;
-               #size-cells = <2>;
-               #address-cells = <3>;
-
-               wifi@168c,002e {
-                       compatible = "pci168c,002e";
-                       reg = <0 0 0 0 0>;
-                       qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */
-               };
+               qca,no-eeprom; /* load from ath9k-eeprom-pci-0000:01:00.0.bin */
        };
 };
 
index 3159a5a..dfe649b 100644 (file)
 };
 
 &pci0 {
-       wifi@1814,3062 {
+       wifi@0,e {
                compatible = "pci1814,3062";
                reg = <0x7000 0 0 0 0>;
                ralink,eeprom = "RT3062.eeprom";
        };
 };
-
-&pcie0 {
-       status = "disabled";
-};
index f6e8fd8..1e4d82e 100644 (file)
@@ -8,7 +8,7 @@
 };
 
 &pci0 {
-       wifi@1814,3092 {
+       wifi@0,e {
                compatible = "pci1814,3092";
                reg = <0x7000 0 0 0 0>;
                ralink,eeprom = "RT3092.eeprom";
index e639613..b96fddf 100644 (file)
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
+&pcie {
+       status = "okay";
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+};
+
 &stp {
        status = "okay";
 
index 00cf361..848ef51 100644 (file)
@@ -26,8 +26,5 @@
 
 &pci0 {
        status = "okay";
-       lantiq,bus-clock = <33333333>;
-       interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-       interrupt-map = <0x7000 0 0 1 &icu0 30 1>;
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
index 6d0ddc4..f67ea67 100644 (file)
        };
 };
 
+&pcie {
+       status = "okay";
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+};
+
 &pcie0 {
-       pcie@0 {
+       ath9k: wifi@0,0 {
+               compatible = "pci168c,002e";
                reg = <0 0 0 0 0>;
-               #interrupt-cells = <1>;
-               #size-cells = <2>;
-               #address-cells = <3>;
-
-               ath9k: wifi@168c,002e {
-                       compatible = "pci168c,002e";
-                       reg = <0 0 0 0 0>;
-                       #gpio-cells = <2>;
-                       gpio-controller;
-                       qca,no-eeprom;
-                       qca,disable-5ghz;
-                       mtd-mac-address = <&ath9k_cal 0xf100>;
-                       mtd-mac-address-increment = <2>;
-               };
+               #gpio-cells = <2>;
+               gpio-controller;
+               qca,no-eeprom;
+               qca,disable-5ghz;
+               mtd-mac-address = <&ath9k_cal 0xf100>;
+               mtd-mac-address-increment = <2>;
        };
 };
 
index 2d52176..71cdeb2 100644 (file)
                };
        };
 };
+
+&pcie {
+       status = "okay";
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+};
index 6356ddf..0ba6b5c 100644 (file)
        status = "okay";
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
-       wifi@1814,3592 {
+       wifi@0,e {
                compatible = "pci1814,3592";
                reg = <0x7000 0 0 0 0>;
                ralink,mtd-eeprom = <&boardconfig 0x410>;
        };
 };
 
-&pcie0 {
-       status = "disabled";
-};
-
 &usb_phy0 {
        status = "okay";
 };
index 7b5713e..e35e8aa 100644 (file)
        status = "okay";
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 
-       wifi@1814,3091 {
+       wifi@0,e {
                compatible = "pci1814,3091";
                reg = <0x7000 0 0 0 0>;
                ralink,mtd-eeprom = <&boardconfig 0x410>;
        };
 };
 
-&pcie0 {
-       status = "disabled";
-};
-
 &stp {
        status = "okay";
        lantiq,shadow = <0xffff>;
index cb6765e..0d38fce 100644 (file)
        reset-gpios = <&gpio 21 GPIO_ACTIVE_LOW>;
 };
 
+&pcie {
+       status = "okay";
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+};
+
 &spi {
        status = "okay";
 
index 48f6dc7..5922940 100644 (file)
        };
 };
 
+&pcie {
+       status = "okay";
+       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+};
+
 &spi {
        status = "okay";
 
index a069adc..a3e33de 100644 (file)
                        reset-names = "dsp", "dfe", "tc";
                };
 
-               pcie0: pcie@d900000 {
+               pcie: pcie@d900000 {
+                       status = "disabled";
+
                        compatible = "lantiq,pcie-xrx200";
 
                        #interrupt-cells = <1>;
 
                        device_type = "pci";
 
-                       gpio-reset = <&gpio 38 GPIO_ACTIVE_HIGH>;
+                       pcie0: bridge@0,0 {
+                               #size-cells = <2>;
+                               #address-cells = <3>;
+                               reg = <0 0 0 0 0>;
+                               ranges;
+                       };
+
+                       pcie1: bridge@1,0 {
+                               #size-cells = <2>;
+                               #address-cells = <3>;
+                               reg = <0x10000 0 0 0 0>;
+                               ranges;
+                       };
                };
 
                pci0: pci@e105400 {