package/boot/uboot-layerscape/patches/0041-DNCPE-4-LS1012A-PPFE-driver.patch

   1 From 487b9b2e5c767ee2110cce57539f0ebeb5a74872 Mon Sep 17 00:00:00 2001
   2 From: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
   3 Date: Tue, 24 May 2016 14:05:18 +0530
   4 Subject: [PATCH 41/93] DNCPE-4: LS1012A PPFE driver
   5
   6 [context adjustment]
   7
   8 - Ported PFE driver from LS1024
   9 - Did changes for GEMAC/MDIO/PHY
  10 - LS1012A address translation changes
  11 - Added pfe command  to the U-boot.
  12 - Added gemac_stat command
  13 - Added config PFE_START to conditionally start pfe on bootup time.
  14 - Change Rx packet ack model
  15 - Class firmware changes to ignore Rx error status
  16
  17 - SCFG changes for pfe
  18 - Configure CCI-400 QoS settings
  19 - Configure transaction attributes
  20 - Configure RGMII port config
  21
  22 Testing status on board
  23
  24 RGMII - Works fine, can download file through tftp.
  25 SGMII - CRC errors are seen, but basic rx/tx works.
  26
  27 Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>>
  28 Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
  29 Integrated-by: Jiang Yutang <yutang.jiang@nxp.com>
  30 ---
  31  arch/arm/cpu/armv8/fsl-layerscape/cpu.c            |    5 +
  32  .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |   42 +-
  33  board/freescale/ls1012aqds/Makefile                |    1 +
  34  board/freescale/ls1012aqds/eth.c                   |  199 +++
  35  board/freescale/ls1012aqds/ls1012aqds.c            |    5 -
  36  board/freescale/ls1012aqds/ls1012aqds.h            |  149 ++
  37  board/freescale/ls1012aqds/ls1012aqds_qixis.h      |    2 +-
  38  board/freescale/ls1012ardb/Makefile                |    1 +
  39  board/freescale/ls1012ardb/eth.c                   |   68 +
  40  board/freescale/ls1012ardb/ls1012ardb.c            |    4 -
  41  common/Makefile                                    |    2 +
  42  common/cmd_gemac_stat.c                            |  147 ++
  43  common/cmd_pfe_commands.c                          |  983 ++++++++++++
  44  drivers/net/Makefile                               |    1 +
  45  drivers/net/pfe_eth/Makefile                       |    1 +
  46  drivers/net/pfe_eth/class_sbl_elf.fw               |    1 +
  47  drivers/net/pfe_eth/hal.h                          |   64 +
  48  drivers/net/pfe_eth/pfe.c                          | 1677 ++++++++++++++++++++
  49  drivers/net/pfe_eth/pfe/cbus.h                     |   74 +
  50  drivers/net/pfe_eth/pfe/cbus/bmu.h                 |   37 +
  51  drivers/net/pfe_eth/pfe/cbus/class_csr.h           |  206 +++
  52  drivers/net/pfe_eth/pfe/cbus/emac.h                |  232 +++
  53  drivers/net/pfe_eth/pfe/cbus/gpi.h                 |   60 +
  54  drivers/net/pfe_eth/pfe/cbus/gpt.h                 |   11 +
  55  drivers/net/pfe_eth/pfe/cbus/hif.h                 |   62 +
  56  drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h           |   33 +
  57  drivers/net/pfe_eth/pfe/cbus/tmu_csr.h             |  102 ++
  58  drivers/net/pfe_eth/pfe/cbus/util_csr.h            |   43 +
  59  drivers/net/pfe_eth/pfe/class.h                    |  142 ++
  60  drivers/net/pfe_eth/pfe/class/ccu.h                |   10 +
  61  drivers/net/pfe_eth/pfe/class/efet.h               |   21 +
  62  drivers/net/pfe_eth/pfe/class/mac_hash.h           |   28 +
  63  drivers/net/pfe_eth/pfe/class/perg.h               |   21 +
  64  drivers/net/pfe_eth/pfe/class/vlan_hash.h          |   28 +
  65  drivers/net/pfe_eth/pfe/gpt.h                      |   11 +
  66  drivers/net/pfe_eth/pfe/pe.h                       |  147 ++
  67  drivers/net/pfe_eth/pfe/pfe.h                      |  250 +++
  68  drivers/net/pfe_eth/pfe/tmu.h                      |   48 +
  69  drivers/net/pfe_eth/pfe/tmu/phy_queue.h            |   31 +
  70  drivers/net/pfe_eth/pfe/tmu/sched.h                |   47 +
  71  drivers/net/pfe_eth/pfe/tmu/shaper.h               |   19 +
  72  drivers/net/pfe_eth/pfe/uart.h                     |   13 +
  73  drivers/net/pfe_eth/pfe/util.h                     |   30 +
  74  drivers/net/pfe_eth/pfe/util/eape.h                |   10 +
  75  drivers/net/pfe_eth/pfe/util/efet.h                |   20 +
  76  drivers/net/pfe_eth/pfe/util/inq.h                 |   10 +
  77  drivers/net/pfe_eth/pfe_driver.c                   |  710 +++++++++
  78  drivers/net/pfe_eth/pfe_driver.h                   |  141 ++
  79  drivers/net/pfe_eth/pfe_eth.c                      |  521 ++++++
  80  drivers/net/pfe_eth/pfe_eth.h                      |  161 ++
  81  drivers/net/pfe_eth/pfe_firmware.c                 |  193 +++
  82  drivers/net/pfe_eth/pfe_firmware.h                 |   20 +
  83  drivers/net/pfe_eth/pfe_mod.h                      |  140 ++
  84  drivers/net/pfe_eth/tmu_sbl_elf.fw                 |    1 +
  85  drivers/net/pfe_eth/util_sbl_elf.fw                |    1 +
  86  include/configs/ls1012a_common.h                   |   10 +
  87  include/configs/ls1012aqds.h                       |   13 +-
  88  include/configs/ls1012ardb.h                       |    6 +-
  89  58 files changed, 6994 insertions(+), 21 deletions(-)
  90  create mode 100644 board/freescale/ls1012aqds/eth.c
  91  create mode 100644 board/freescale/ls1012aqds/ls1012aqds.h
  92  create mode 100644 board/freescale/ls1012ardb/eth.c
  93  create mode 100644 common/cmd_gemac_stat.c
  94  create mode 100644 common/cmd_pfe_commands.c
  95  create mode 100644 drivers/net/pfe_eth/Makefile
  96  create mode 100644 drivers/net/pfe_eth/class_sbl_elf.fw
  97  create mode 100644 drivers/net/pfe_eth/hal.h
  98  create mode 100644 drivers/net/pfe_eth/pfe.c
  99  create mode 100644 drivers/net/pfe_eth/pfe/cbus.h
 100  create mode 100644 drivers/net/pfe_eth/pfe/cbus/bmu.h
 101  create mode 100644 drivers/net/pfe_eth/pfe/cbus/class_csr.h
 102  create mode 100644 drivers/net/pfe_eth/pfe/cbus/emac.h
 103  create mode 100644 drivers/net/pfe_eth/pfe/cbus/gpi.h
 104  create mode 100644 drivers/net/pfe_eth/pfe/cbus/gpt.h
 105  create mode 100644 drivers/net/pfe_eth/pfe/cbus/hif.h
 106  create mode 100644 drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
 107  create mode 100644 drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
 108  create mode 100644 drivers/net/pfe_eth/pfe/cbus/util_csr.h
 109  create mode 100644 drivers/net/pfe_eth/pfe/class.h
 110  create mode 100644 drivers/net/pfe_eth/pfe/class/ccu.h
 111  create mode 100644 drivers/net/pfe_eth/pfe/class/efet.h
 112  create mode 100644 drivers/net/pfe_eth/pfe/class/mac_hash.h
 113  create mode 100644 drivers/net/pfe_eth/pfe/class/perg.h
 114  create mode 100644 drivers/net/pfe_eth/pfe/class/vlan_hash.h
 115  create mode 100644 drivers/net/pfe_eth/pfe/gpt.h
 116  create mode 100644 drivers/net/pfe_eth/pfe/pe.h
 117  create mode 100644 drivers/net/pfe_eth/pfe/pfe.h
 118  create mode 100644 drivers/net/pfe_eth/pfe/tmu.h
 119  create mode 100644 drivers/net/pfe_eth/pfe/tmu/phy_queue.h
 120  create mode 100644 drivers/net/pfe_eth/pfe/tmu/sched.h
 121  create mode 100644 drivers/net/pfe_eth/pfe/tmu/shaper.h
 122  create mode 100644 drivers/net/pfe_eth/pfe/uart.h
 123  create mode 100644 drivers/net/pfe_eth/pfe/util.h
 124  create mode 100644 drivers/net/pfe_eth/pfe/util/eape.h
 125  create mode 100644 drivers/net/pfe_eth/pfe/util/efet.h
 126  create mode 100644 drivers/net/pfe_eth/pfe/util/inq.h
 127  create mode 100644 drivers/net/pfe_eth/pfe_driver.c
 128  create mode 100644 drivers/net/pfe_eth/pfe_driver.h
 129  create mode 100644 drivers/net/pfe_eth/pfe_eth.c
 130  create mode 100644 drivers/net/pfe_eth/pfe_eth.h
 131  create mode 100644 drivers/net/pfe_eth/pfe_firmware.c
 132  create mode 100644 drivers/net/pfe_eth/pfe_firmware.h
 133  create mode 100644 drivers/net/pfe_eth/pfe_mod.h
 134  create mode 100644 drivers/net/pfe_eth/tmu_sbl_elf.fw
 135  create mode 100644 drivers/net/pfe_eth/util_sbl_elf.fw
 136
 137 diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
 138 index 340d9f9..8f59577 100644
 139 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
 140 +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
 141 @@ -573,6 +573,11 @@ int cpu_eth_init(bd_t *bis)
 142  {
 143         int error = 0;
 144
 145 +#if defined(CONFIG_FSL_PPFE) && !defined(CONFIG_CMD_PFE_START)
 146 +       ls1012a_gemac_initialize(bis, 0 , "pfe_eth0");
 147 +       ls1012a_gemac_initialize(bis, 1 , "pfe_eth1");
 148 +#endif
 149 +
 150  #ifdef CONFIG_FSL_MC_ENET
 151         error = fsl_mc_ldpaa_init(bis);
 152  #endif
 153 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
 154 index 6918757..a264f9a 100644
 155 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
 156 +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
 157 @@ -41,6 +41,7 @@
 158  #define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
 159  #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
 160  #define CONFIG_SYS_PCIE3_ADDR                  (CONFIG_SYS_IMMR + 0x2600000)
 161 +#define CONFIG_SYS_PPFE_ADDR                   (CONFIG_SYS_IMMR + 0x3000000)
 162  #define CONFIG_SYS_SEC_MON_ADDR                        (CONFIG_SYS_IMMR + 0xe90000)
 163  #define CONFIG_SYS_SFP_ADDR                    (CONFIG_SYS_IMMR + 0xe80200)
 164
 165 @@ -364,6 +365,24 @@ struct ccsr_gur {
 166  #define SCFG_SNPCNFGCR_USB3RDSNP       0x00002000
 167  #define SCFG_SNPCNFGCR_USB3WRSNP       0x00004000
 168
 169 +/* RGMIIPCR bit definitions*/
 170 +#define SCFG_RGMIIPCR_EN_AUTO          (0x00000008)
 171 +#define SCFG_RGMIIPCR_SETSP_1000M      (0x00000004)
 172 +#define SCFG_RGMIIPCR_SETSP_100M       (0x00000000)
 173 +#define SCFG_RGMIIPCR_SETSP_10M                (0x00000002)
 174 +#define SCFG_RGMIIPCR_SETFD            (0x00000001)
 175 +
 176 +/*PFEASBCR bit definitions */
 177 +#define SCFG_PPFEASBCR_ARCACHE0                (0x80000000)
 178 +#define SCFG_PPFEASBCR_AWCACHE0                (0x40000000)
 179 +#define SCFG_PPFEASBCR_ARCACHE1                (0x20000000)
 180 +#define SCFG_PPFEASBCR_AWCACHE1                (0x10000000)
 181 +#define SCFG_PPFEASBCR_ARSNP           (0x08000000)
 182 +#define SCFG_PPFEASBCR_AWSNP           (0x04000000)
 183 +
 184 +
 185 +
 186 +
 187  /* Supplemental Configuration Unit */
 188  struct ccsr_scfg {
 189         u8 res_000[0x100-0x000];
 190 @@ -381,7 +400,12 @@ struct ccsr_scfg {
 191         u8 res_140[0x158-0x140];
 192         u32 altcbar;
 193         u32 qspi_cfg;
 194 -       u8 res_160[0x180-0x160];
 195 +       u8 res_160[0x164-0x160];
 196 +       u32 wr_qos1;
 197 +       u32 wr_qos2;
 198 +       u32 rd_qos1;
 199 +       u32 rd_qos2;
 200 +       u8 res_174[0x180-0x174];
 201         u32 dmamcr;
 202         u8 res_184[0x18c-0x184];
 203         u32 debug_icid;
 204 @@ -411,7 +435,21 @@ struct ccsr_scfg {
 205         u32 usb_refclk_selcr1;
 206         u32 usb_refclk_selcr2;
 207         u32 usb_refclk_selcr3;
 208 -       u8 res_424[0x600-0x424];
 209 +       u8 res_424[0x434-0x424];
 210 +       u32 rgmiipcr;
 211 +       u32 res_438;
 212 +       u32 rgmiipsr;
 213 +       u32 pfepfcssr1;
 214 +       u32 pfeintencr1;
 215 +       u32 pfepfcssr2;
 216 +       u32 pfeintencr2;
 217 +       u32 pfeerrcr;
 218 +       u32 pfeeerrintencr;
 219 +       u32 pfeasbcr;
 220 +       u32 pfebsbcr;
 221 +       u8 res_460[0x484-0x460];
 222 +       u32 mdioselcr;
 223 +       u8 res_468[0x600-0x468];
 224         u32 scratchrw[4];
 225         u8 res_610[0x680-0x610];
 226         u32 corebcr;
 227 diff --git a/board/freescale/ls1012aqds/Makefile b/board/freescale/ls1012aqds/Makefile
 228 index 0b813f9..b18494a 100644
 229 --- a/board/freescale/ls1012aqds/Makefile
 230 +++ b/board/freescale/ls1012aqds/Makefile
 231 @@ -5,3 +5,4 @@
 232  #
 233
 234  obj-y += ls1012aqds.o
 235 +obj-y += eth.o
 236 diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c
 237 new file mode 100644
 238 index 0000000..1bd7c9d
 239 --- /dev/null
 240 +++ b/board/freescale/ls1012aqds/eth.c
 241 @@ -0,0 +1,199 @@
 242 +/*
 243 + * Copyright 2016 Freescale Semiconductor, Inc.
 244 + *
 245 + * SPDX-License-Identifier:    GPL-2.0+
 246 + */
 247 +
 248 +#include <common.h>
 249 +#include <asm/io.h>
 250 +#include <netdev.h>
 251 +#include <fm_eth.h>
 252 +#include <fsl_mdio.h>
 253 +#include <malloc.h>
 254 +#include <fsl_dtsec.h>
 255 +#include <asm/arch/soc.h>
 256 +#include <asm/arch-fsl-layerscape/config.h>
 257 +#include <asm/arch/fsl_serdes.h>
 258 +
 259 +#include "../common/qixis.h"
 260 +#include "../../../drivers/net/pfe_eth/pfe_eth.h"
 261 +#include "ls1012aqds_qixis.h"
 262 +#include <asm/arch-fsl-layerscape/immap_lsch2.h>
 263 +
 264 +#define EMI_NONE       0xFF
 265 +#define EMI1_RGMII     1
 266 +#define EMI1_SLOT1     2
 267 +#define EMI1_SLOT2     3
 268 +
 269 +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
 270 +
 271 +static int mdio_mux[NUM_FM_PORTS];
 272 +
 273 +static const char * const mdio_names[] = {
 274 +       "NULL",
 275 +       "LS1012AQDS_MDIO_RGMII",
 276 +       "LS1012AQDS_MDIO_SLOT1",
 277 +       "LS1012AQDS_MDIO_SLOT2",
 278 +       "NULL",
 279 +};
 280 +
 281 +static const char *ls1012aqds_mdio_name_for_muxval(u8 muxval)
 282 +{
 283 +       return mdio_names[muxval];
 284 +}
 285 +
 286 +struct ls1012aqds_mdio {
 287 +       u8 muxval;
 288 +       struct mii_dev *realbus;
 289 +};
 290 +
 291 +static void ls1012aqds_mux_mdio(u8 muxval)
 292 +{
 293 +       u8 brdcfg4;
 294 +
 295 +       if (muxval < 7) {
 296 +               brdcfg4 = QIXIS_READ(brdcfg[4]);
 297 +               brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
 298 +               brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 299 +               QIXIS_WRITE(brdcfg[4], brdcfg4);
 300 +       }
 301 +}
 302 +
 303 +static int ls1012aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
 304 +                             int regnum)
 305 +{
 306 +       struct ls1012aqds_mdio *priv = bus->priv;
 307 +
 308 +       ls1012aqds_mux_mdio(priv->muxval);
 309 +
 310 +       return priv->realbus->read(priv->realbus, addr, devad, regnum);
 311 +}
 312 +
 313 +static int ls1012aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
 314 +                              int regnum, u16 value)
 315 +{
 316 +       struct ls1012aqds_mdio *priv = bus->priv;
 317 +
 318 +       ls1012aqds_mux_mdio(priv->muxval);
 319 +
 320 +       return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 321 +}
 322 +
 323 +static int ls1012aqds_mdio_reset(struct mii_dev *bus)
 324 +{
 325 +       struct ls1012aqds_mdio *priv = bus->priv;
 326 +
 327 +       if(priv->realbus->reset)
 328 +               return priv->realbus->reset(priv->realbus);
 329 +}
 330 +
 331 +static int ls1012aqds_mdio_init(char *realbusname, u8 muxval)
 332 +{
 333 +       struct ls1012aqds_mdio *pmdio;
 334 +       struct mii_dev *bus = mdio_alloc();
 335 +
 336 +       if (!bus) {
 337 +               printf("Failed to allocate ls1012aqds MDIO bus\n");
 338 +               return -1;
 339 +       }
 340 +
 341 +       pmdio = malloc(sizeof(*pmdio));
 342 +       if (!pmdio) {
 343 +               printf("Failed to allocate ls1012aqds private data\n");
 344 +               free(bus);
 345 +               return -1;
 346 +       }
 347 +
 348 +       bus->read = ls1012aqds_mdio_read;
 349 +       bus->write = ls1012aqds_mdio_write;
 350 +       bus->reset = ls1012aqds_mdio_reset;
 351 +       sprintf(bus->name, ls1012aqds_mdio_name_for_muxval(muxval));
 352 +
 353 +       pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 354 +
 355 +       if (!pmdio->realbus) {
 356 +               printf("No bus with name %s\n", realbusname);
 357 +               free(bus);
 358 +               free(pmdio);
 359 +               return -1;
 360 +       }
 361 +
 362 +       pmdio->muxval = muxval;
 363 +       bus->priv = pmdio;
 364 +       return mdio_register(bus);
 365 +}
 366 +
 367 +int board_eth_init(bd_t *bis)
 368 +{
 369 +#ifdef CONFIG_FSL_PPFE
 370 +        struct mii_dev *bus;
 371 +       struct mdio_info mac1_mdio_info;
 372 +       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 373 +       u8 data8;
 374 +
 375 +
 376 +       /*TODO Following config should be done for all boards, where is the right place to put this */
 377 +       out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
 378 +       out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
 379 +
 380 +       /*CCI-400 QoS settings for PFE */
 381 +       out_be32(&scfg->wr_qos1, 0x0ff00000);
 382 +       out_be32(&scfg->rd_qos1, 0x0ff00000);
 383 +
 384 +       /* Set RGMII into 1G + Full duplex mode */
 385 +       out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
 386 +
 387 +       out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
 388 +       out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
 389 +
 390 +       ls1012aqds_mux_mdio(2);
 391 +
 392 +#ifdef RGMII_RESET_WA
 393 +       /* Work around for FPGA registers initialization
 394 +        * This is needed for RGMII to work */
 395 +       printf("Reset RGMII WA....\n");
 396 +       data8 = QIXIS_READ(rst_frc[0]);
 397 +       data8 |= 0x2;
 398 +       QIXIS_WRITE(rst_frc[0], data8);
 399 +       data8 = QIXIS_READ(rst_frc[0]);
 400 +
 401 +       data8 = QIXIS_READ(res8[6]);
 402 +       data8 |= 0xff;
 403 +       QIXIS_WRITE(res8[6], data8);
 404 +       data8 = QIXIS_READ(res8[6]);
 405 +
 406 +#endif
 407 +
 408 +       mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
 409 +       mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
 410 +
 411 +       bus = ls1012a_mdio_init(&mac1_mdio_info);
 412 +       if(!bus)
 413 +       {
 414 +               printf("Failed to register mdio \n");
 415 +               return -1;
 416 +       }
 417 +
 418 +       /*Based on RCW config initialize correctly */
 419 +       /*MAC2 */
 420 +       if(ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_RGMII) < 0)
 421 +       {
 422 +               printf("Failed to register mdio for %s\n", ls1012aqds_mdio_name_for_muxval(EMI1_RGMII));
 423 +               return -1;
 424 +       }
 425 +       ls1012a_set_mdio(1, miiphy_get_dev_by_name(ls1012aqds_mdio_name_for_muxval(EMI1_RGMII)));
 426 +       ls1012a_set_phy_address_mode(1,  EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_RGMII);
 427 +
 428 +       /*MAC1 */
 429 +       if(ls1012aqds_mdio_init(DEFAULT_PFE_MDIO_NAME, EMI1_SLOT1) < 0)
 430 +       {
 431 +               printf("Failed to register mdio for %s\n", ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1));
 432 +               return -1;
 433 +       }
 434 +       ls1012a_set_mdio(0, miiphy_get_dev_by_name(ls1012aqds_mdio_name_for_muxval(EMI1_SLOT1)));
 435 +       ls1012a_set_phy_address_mode(0,  EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
 436 +
 437 +       cpu_eth_init(bis);
 438 +#endif
 439 +       return pci_eth_init(bis);
 440 +}
 441 diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c
 442 index 446989b..b7365e8 100644
 443 --- a/board/freescale/ls1012aqds/ls1012aqds.c
 444 +++ b/board/freescale/ls1012aqds/ls1012aqds.c
 445 @@ -211,11 +211,6 @@ int board_init(void)
 446         return 0;
 447  }
 448
 449 -int board_eth_init(bd_t *bis)
 450 -{
 451 -       return pci_eth_init(bis);
 452 -}
 453 -
 454  #ifdef CONFIG_OF_BOARD_SETUP
 455  int ft_board_setup(void *blob, bd_t *bd)
 456  {
 457 diff --git a/board/freescale/ls1012aqds/ls1012aqds.h b/board/freescale/ls1012aqds/ls1012aqds.h
 458 new file mode 100644
 459 index 0000000..42e10f5
 460 --- /dev/null
 461 +++ b/board/freescale/ls1012aqds/ls1012aqds.h
 462 @@ -0,0 +1,149 @@
 463 +/*
 464 + * Copyright 2016 Freescale Semiconductor, Inc.
 465 + *
 466 + * SPDX-License-Identifier:    GPL-2.0+
 467 + */
 468 +
 469 +#ifndef __LS1012AQDS_H__
 470 +#define __LS1012AQDS_H__
 471 +
 472 +#include "ls1012a_common.h"
 473 +
 474 +
 475 +#define CONFIG_DIMM_SLOTS_PER_CTLR     1
 476 +#define CONFIG_CHIP_SELECTS_PER_CTRL   1
 477 +#define CONFIG_NR_DRAM_BANKS           2
 478 +
 479 +#ifdef CONFIG_FSL_PPFE
 480 +/*#define CONFIG_CMD_PFE_START */
 481 +#define EMAC1_PHY_ADDR          0x1e
 482 +#define EMAC2_PHY_ADDR          0x1
 483 +#define CONFIG_PHYLIB
 484 +#define CONFIG_PHY_VITESSE
 485 +#define CONFIG_PHY_REALTEK
 486 +#endif
 487 +
 488 +#define CONFIG_QIXIS_I2C_ACCESS
 489 +#define CONFIG_SYS_I2C_FPGA_ADDR       0x66
 490 +
 491 +/*
 492 + * I2C bus multiplexer
 493 + */
 494 +#define I2C_MUX_PCA_ADDR_PRI           0x77
 495 +#define I2C_MUX_PCA_ADDR_SEC           0x76 /* Secondary multiplexer */
 496 +#define I2C_RETIMER_ADDR               0x18
 497 +#define I2C_MUX_CH_DEFAULT             0x8
 498 +#define I2C_MUX_CH_CH7301              0xC
 499 +#define I2C_MUX_CH5                    0xD
 500 +#define I2C_MUX_CH7                    0xF
 501 +
 502 +#define I2C_MUX_CH_VOL_MONITOR 0xa
 503 +
 504 +/*
 505 +* RTC configuration
 506 +*/
 507 +#define RTC
 508 +#define CONFIG_RTC_PCF8563 1
 509 +#define CONFIG_SYS_I2C_RTC_ADDR         0x51  /* Channel 3*/
 510 +#define CONFIG_CMD_DATE
 511 +
 512 +/* EEPROM */
 513 +#define CONFIG_ID_EEPROM
 514 +#define CONFIG_CMD_EEPROM
 515 +#define CONFIG_SYS_I2C_EEPROM_NXID
 516 +#define CONFIG_SYS_EEPROM_BUS_NUM    0
 517 +#define CONFIG_SYS_I2C_EEPROM_ADDR   0x57
 518 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN     1
 519 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 520 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 521 +
 522 +
 523 +/* Voltage monitor on channel 2*/
 524 +#define I2C_VOL_MONITOR_ADDR           0x40
 525 +#define I2C_VOL_MONITOR_BUS_V_OFFSET   0x2
 526 +#define I2C_VOL_MONITOR_BUS_V_OVF      0x1
 527 +#define I2C_VOL_MONITOR_BUS_V_SHIFT    3
 528 +
 529 +
 530 +/* DSPI */
 531 +#define CONFIG_FSL_DSPI
 532 +#define CONFIG_FSL_DSPI1
 533 +#define CONFIG_DEFAULT_SPI_BUS 1
 534 +
 535 +#define CONFIG_CMD_SPI
 536 +#define MMAP_DSPI          DSPI1_BASE_ADDR
 537 +
 538 +#define CONFIG_SYS_DSPI_CTAR0   1
 539 +
 540 +#define CONFIG_SYS_DSPI_CTAR1  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
 541 +                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
 542 +                               DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
 543 +                               DSPI_CTAR_DT(0))
 544 +#define CONFIG_SPI_FLASH_SST /* cs1 */
 545 +
 546 +#define CONFIG_SYS_DSPI_CTAR2  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
 547 +                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
 548 +                               DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
 549 +                               DSPI_CTAR_DT(0))
 550 +#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
 551 +
 552 +#define CONFIG_SYS_DSPI_CTAR3  (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
 553 +                               DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
 554 +                               DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
 555 +                               DSPI_CTAR_DT(0))
 556 +#define CONFIG_SPI_FLASH_EON /* cs3 */
 557 +
 558 +#define CONFIG_SF_DEFAULT_SPEED      10000000
 559 +#define CONFIG_SF_DEFAULT_MODE       SPI_MODE_0
 560 +#define CONFIG_SF_DEFAULT_BUS        1
 561 +#define CONFIG_SF_DEFAULT_CS         0
 562 +
 563 +/*
 564 +* USB
 565 +*/
 566 +/* EHCI Support - disbaled by default */
 567 +/*#define CONFIG_HAS_FSL_DR_USB*/
 568 +
 569 +#ifdef CONFIG_HAS_FSL_DR_USB
 570 +#define CONFIG_USB_EHCI
 571 +#define CONFIG_USB_EHCI_FSL
 572 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 573 +#endif
 574 +
 575 +/*XHCI Support - enabled by default*/
 576 +#define CONFIG_HAS_FSL_XHCI_USB
 577 +
 578 +#ifdef CONFIG_HAS_FSL_XHCI_USB
 579 +#define CONFIG_USB_XHCI
 580 +#define CONFIG_USB_XHCI_FSL
 581 +#define CONFIG_USB_XHCI_DWC3
 582 +#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
 583 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
 584 +#define CONFIG_CMD_USB
 585 +#define CONFIG_USB_STORAGE
 586 +#define CONFIG_CMD_EXT2
 587 +
 588 +#define CONFIG_USB_DWC3
 589 +#define CONFIG_USB_DWC3_GADGET
 590 +
 591 +#define CONFIG_USB_GADGET
 592 +#define CONFIG_USB_FUNCTION_MASS_STORAGE
 593 +#define CONFIG_USB_GADGET_DOWNLOAD
 594 +#define CONFIG_USB_GADGET_VBUS_DRAW 2
 595 +#define CONFIG_G_DNL_MANUFACTURER "NXP Semiconductor"
 596 +#define CONFIG_G_DNL_VENDOR_NUM 0x1234
 597 +#define CONFIG_G_DNL_PRODUCT_NUM 0x1234
 598 +#define CONFIG_USB_GADGET_DUALSPEED
 599 +
 600 +/* USB Gadget ums command */
 601 +#define CONFIG_CMD_USB_MASS_STORAGE
 602 +#endif
 603 +
 604 +#define CONFIG_CMD_MEMINFO
 605 +#define CONFIG_CMD_MEMTEST
 606 +#define CONFIG_SYS_MEMTEST_START       0x80000000
 607 +#define CONFIG_SYS_MEMTEST_END         0x9fffffff
 608 +
 609 +#define CONFIG_MISC_INIT_R
 610 +
 611 +#endif /* __LS1012AQDS_H__ */
 612 diff --git a/board/freescale/ls1012aqds/ls1012aqds_qixis.h b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
 613 index 584f604..7a1ba3d 100644
 614 --- a/board/freescale/ls1012aqds/ls1012aqds_qixis.h
 615 +++ b/board/freescale/ls1012aqds/ls1012aqds_qixis.h
 616 @@ -11,7 +11,7 @@
 617
 618  /* BRDCFG4[4:7] select EC1 and EC2 as a pair */
 619  #define BRDCFG4_EMISEL_MASK            0xe0
 620 -#define BRDCFG4_EMISEL_SHIFT           5
 621 +#define BRDCFG4_EMISEL_SHIFT           6
 622
 623  /* SYSCLK */
 624  #define QIXIS_SYSCLK_66                        0x0
 625 diff --git a/board/freescale/ls1012ardb/Makefile b/board/freescale/ls1012ardb/Makefile
 626 index 05fa9d9..bd80ce5 100644
 627 --- a/board/freescale/ls1012ardb/Makefile
 628 +++ b/board/freescale/ls1012ardb/Makefile
 629 @@ -5,3 +5,4 @@
 630  #
 631
 632  obj-y += ls1012ardb.o
 633 +obj-y += eth.o
 634 diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
 635 new file mode 100644
 636 index 0000000..29830e8
 637 --- /dev/null
 638 +++ b/board/freescale/ls1012ardb/eth.c
 639 @@ -0,0 +1,68 @@
 640 +/*
 641 + * Copyright 2016 Freescale Semiconductor, Inc.
 642 + *
 643 + * SPDX-License-Identifier:    GPL-2.0+
 644 + */
 645 +
 646 +#include <common.h>
 647 +#include <asm/io.h>
 648 +#include <netdev.h>
 649 +#include <fm_eth.h>
 650 +#include <fsl_mdio.h>
 651 +#include <malloc.h>
 652 +#include <fsl_dtsec.h>
 653 +#include <asm/arch/soc.h>
 654 +#include <asm/arch-fsl-layerscape/config.h>
 655 +#include <asm/arch/fsl_serdes.h>
 656 +
 657 +#include "../../../drivers/net/pfe_eth/pfe_eth.h"
 658 +#include <asm/arch-fsl-layerscape/immap_lsch2.h>
 659 +
 660 +#define DEFAULT_PFE_MDIO_NAME "PFE_MDIO"
 661 +
 662 +int board_eth_init(bd_t *bis)
 663 +{
 664 +#ifdef CONFIG_FSL_PPFE
 665 +        struct mii_dev *bus;
 666 +       struct mdio_info mac1_mdio_info;
 667 +       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 668 +
 669 +
 670 +       /*TODO Following config should be done for all boards, where is the right place to put this */
 671 +       out_be32(&scfg->pfeasbcr, in_be32(&scfg->pfeasbcr) | SCFG_PPFEASBCR_AWCACHE0);
 672 +       out_be32(&scfg->pfebsbcr, in_be32(&scfg->pfebsbcr) | SCFG_PPFEASBCR_AWCACHE0);
 673 +
 674 +       /*CCI-400 QoS settings for PFE */
 675 +       out_be32(&scfg->wr_qos1, 0x0ff00000);
 676 +       out_be32(&scfg->rd_qos1, 0x0ff00000);
 677 +
 678 +       /* Set RGMII into 1G + Full duplex mode */
 679 +       out_be32(&scfg->rgmiipcr, in_be32(&scfg->rgmiipcr) | (SCFG_RGMIIPCR_SETSP_1000M | SCFG_RGMIIPCR_SETFD));
 680 +
 681 +
 682 +       out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x520), 0xFFFFFFFF);
 683 +       out_be32((CONFIG_SYS_DCSR_DCFG_ADDR + 0x524), 0xFFFFFFFF);
 684 +
 685 +       mac1_mdio_info.reg_base = (void *)0x04200000; /*EMAC1_BASE_ADDR*/
 686 +       mac1_mdio_info.name = DEFAULT_PFE_MDIO_NAME;
 687 +
 688 +       bus = ls1012a_mdio_init(&mac1_mdio_info);
 689 +       if(!bus)
 690 +       {
 691 +               printf("Failed to register mdio \n");
 692 +               return -1;
 693 +       }
 694 +
 695 +       /*MAC1 */
 696 +       ls1012a_set_mdio(0, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
 697 +       ls1012a_set_phy_address_mode(0,  EMAC1_PHY_ADDR, PHY_INTERFACE_MODE_SGMII);
 698 +
 699 +       /*MAC2 */
 700 +       ls1012a_set_mdio(1, miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
 701 +       ls1012a_set_phy_address_mode(1,  EMAC2_PHY_ADDR, PHY_INTERFACE_MODE_RGMII);
 702 +
 703 +
 704 +       cpu_eth_init(bis);
 705 +#endif
 706 +       return pci_eth_init(bis);
 707 +}
 708 diff --git a/board/freescale/ls1012ardb/ls1012ardb.c b/board/freescale/ls1012ardb/ls1012ardb.c
 709 index 347b8c8..90cbd5e 100644
 710 --- a/board/freescale/ls1012ardb/ls1012ardb.c
 711 +++ b/board/freescale/ls1012ardb/ls1012ardb.c
 712 @@ -163,10 +163,6 @@ int dram_init(void)
 713         return 0;
 714  }
 715
 716 -int board_eth_init(bd_t *bis)
 717 -{
 718 -       return pci_eth_init(bis);
 719 -}
 720
 721  int board_early_init_f(void)
 722  {
 723 diff --git a/common/Makefile b/common/Makefile
 724 index 2a1d9f8..f5db77e 100644
 725 --- a/common/Makefile
 726 +++ b/common/Makefile
 727 @@ -136,6 +136,8 @@ obj-$(CONFIG_CMD_MII) += cmd_mii.o
 728  ifdef CONFIG_PHYLIB
 729  obj-$(CONFIG_CMD_MII) += cmd_mdio.o
 730  endif
 731 +obj-$(CONFIG_CMD_PFE_COMMANDS) += cmd_pfe_commands.o
 732 +obj-$(CONFIG_CMD_PFE_COMMANDS) += cmd_gemac_stat.o
 733  obj-$(CONFIG_CMD_MISC) += cmd_misc.o
 734  obj-$(CONFIG_CMD_MMC) += cmd_mmc.o
 735  obj-$(CONFIG_CMD_MMC_SPI) += cmd_mmc_spi.o
 736 diff --git a/common/cmd_gemac_stat.c b/common/cmd_gemac_stat.c
 737 new file mode 100644
 738 index 0000000..49bb1aa
 739 --- /dev/null
 740 +++ b/common/cmd_gemac_stat.c
 741 @@ -0,0 +1,147 @@
 742 +/*
 743 + * (C) Copyright 2003
 744 + *  Author : Laurent Brando (Mindspeed Technologies)
 745 + *
 746 + * See file CREDITS for list of people who contributed to this
 747 + * project.
 748 + *
 749 + * This program is free software; you can redistribute it and/or
 750 + * modify it under the terms of the GNU General Public License as
 751 + * published by the Free Software Foundation; either version 2 of
 752 + * the License, or (at your option) any later version.
 753 + *
 754 + * This program is distributed in the hope that it will be useful,
 755 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 756 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 757 + * GNU General Public License for more details.
 758 + *
 759 + * You should have received a copy of the GNU General Public License
 760 + * along with this program; if not, write to the Free Software
 761 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 762 + * MA 02111-1307 USA
 763 + */
 764 +
 765 +/**
 766 + * @file
 767 + * @brief Retrieve GEMAC Statistics
 768 + */
 769 +
 770 +#include <common.h>
 771 +#include <command.h>
 772 +#include "../drivers/net/pfe_eth/pfe_eth.h"
 773 +#include "../drivers/net/pfe_eth/pfe/pfe.h"
 774 +#include "../drivers/net/pfe_eth/pfe_firmware.h"
 775 +#include "../drivers/net/pfe_eth/pfe/cbus.h"
 776 +#include "../drivers/net/pfe_eth/pfe/cbus/class_csr.h"
 777 +#include "../drivers/net/pfe_eth/pfe/cbus/emac.h"
 778 +
 779 +#define ETH_GSTRING_LEN         32 /* from linux/include/ethtool.h */
 780 +
 781 +static const struct fec_stat {
 782 +       char name[ETH_GSTRING_LEN];
 783 +       u16 offset;
 784 +} fec_stats[] = {
 785 +       /* RMON TX */
 786 +       { "tx_dropped", RMON_T_DROP },
 787 +       { "tx_packets", RMON_T_PACKETS },
 788 +       { "tx_broadcast", RMON_T_BC_PKT },
 789 +       { "tx_multicast", RMON_T_MC_PKT },
 790 +       { "tx_crc_errors", RMON_T_CRC_ALIGN },
 791 +       { "tx_undersize", RMON_T_UNDERSIZE },
 792 +       { "tx_oversize", RMON_T_OVERSIZE },
 793 +       { "tx_fragment", RMON_T_FRAG },
 794 +       { "tx_jabber", RMON_T_JAB },
 795 +       { "tx_collision", RMON_T_COL },
 796 +       { "tx_64byte", RMON_T_P64 },
 797 +       { "tx_65to127byte", RMON_T_P65TO127 },
 798 +       { "tx_128to255byte", RMON_T_P128TO255 },
 799 +       { "tx_256to511byte", RMON_T_P256TO511 },
 800 +       { "tx_512to1023byte", RMON_T_P512TO1023 },
 801 +       { "tx_1024to2047byte", RMON_T_P1024TO2047 },
 802 +       { "tx_GTE2048byte", RMON_T_P_GTE2048 },
 803 +       { "tx_octets", RMON_T_OCTETS },
 804 +
 805 +       /* IEEE TX */
 806 +       { "IEEE_tx_drop", IEEE_T_DROP },
 807 +       { "IEEE_tx_frame_ok", IEEE_T_FRAME_OK },
 808 +       { "IEEE_tx_1col", IEEE_T_1COL },
 809 +       { "IEEE_tx_mcol", IEEE_T_MCOL },
 810 +       { "IEEE_tx_def", IEEE_T_DEF },
 811 +       { "IEEE_tx_lcol", IEEE_T_LCOL },
 812 +       { "IEEE_tx_excol", IEEE_T_EXCOL },
 813 +       { "IEEE_tx_macerr", IEEE_T_MACERR },
 814 +       { "IEEE_tx_cserr", IEEE_T_CSERR },
 815 +       { "IEEE_tx_sqe", IEEE_T_SQE },
 816 +       { "IEEE_tx_fdxfc", IEEE_T_FDXFC },
 817 +       { "IEEE_tx_octets_ok", IEEE_T_OCTETS_OK },
 818 +
 819 +       /* RMON RX */
 820 +       { "rx_packets", RMON_R_PACKETS },
 821 +       { "rx_broadcast", RMON_R_BC_PKT },
 822 +       { "rx_multicast", RMON_R_MC_PKT },
 823 +       { "rx_crc_errors", RMON_R_CRC_ALIGN },
 824 +       { "rx_undersize", RMON_R_UNDERSIZE },
 825 +       { "rx_oversize", RMON_R_OVERSIZE },
 826 +       { "rx_fragment", RMON_R_FRAG },
 827 +       { "rx_jabber", RMON_R_JAB },
 828 +       { "rx_64byte", RMON_R_P64 },
 829 +       { "rx_65to127byte", RMON_R_P65TO127 },
 830 +       { "rx_128to255byte", RMON_R_P128TO255 },
 831 +       { "rx_256to511byte", RMON_R_P256TO511 },
 832 +       { "rx_512to1023byte", RMON_R_P512TO1023 },
 833 +       { "rx_1024to2047byte", RMON_R_P1024TO2047 },
 834 +       { "rx_GTE2048byte", RMON_R_P_GTE2048 },
 835 +       { "rx_octets", RMON_R_OCTETS },
 836 +
 837 +       /* IEEE RX */
 838 +       { "IEEE_rx_drop", IEEE_R_DROP },
 839 +       { "IEEE_rx_frame_ok", IEEE_R_FRAME_OK },
 840 +       { "IEEE_rx_crc", IEEE_R_CRC },
 841 +       { "IEEE_rx_align", IEEE_R_ALIGN },
 842 +       { "IEEE_rx_macerr", IEEE_R_MACERR },
 843 +       { "IEEE_rx_fdxfc", IEEE_R_FDXFC },
 844 +       { "IEEE_rx_octets_ok", IEEE_R_OCTETS_OK },
 845 +};
 846 +
 847 +static void ls1012a_emac_print_stats(void *base)
 848 +{
 849 +       int i;
 850 +
 851 +       for (i = 0; i < ARRAY_SIZE(fec_stats); i++)
 852 +               printf("%s: %d\n", fec_stats[i].name, readl(base + fec_stats[i].offset));
 853 +}
 854 +
 855 +static int gemac_stats(cmd_tbl_t *cmdtp, int flag, int argc,
 856 +                      char * const argv[])
 857 +{
 858 +       void *gemac_base = NULL;
 859 +
 860 +       if (argc != 2) {
 861 +               printf("Usage: \n" "gemac_stat [ethx]\n");
 862 +               return CMD_RET_SUCCESS;
 863 +       }
 864 +
 865 +       if ( strcmp(argv[1], "eth0") == 0)
 866 +               gemac_base = (void *)EMAC1_BASE_ADDR;
 867 +       else if ( strcmp(argv[1], "eth1") == 0)
 868 +               gemac_base = (void *)EMAC2_BASE_ADDR;
 869 +
 870 +       if (gemac_base)
 871 +       {
 872 +               ls1012a_emac_print_stats(gemac_base);
 873 +       }
 874 +       else
 875 +       {
 876 +               printf("no such net device: %s\n", argv[1]);
 877 +               return 1;
 878 +       }
 879 +
 880 +       return 0;
 881 +}
 882 +
 883 +U_BOOT_CMD(
 884 +       gemac_stat,     2,      1,      gemac_stats,
 885 +       "retrieve GEMAC statistics",
 886 +       "Usage: \n"
 887 +       "gemac_stat [ethx]\n"
 888 +);
 889 diff --git a/common/cmd_pfe_commands.c b/common/cmd_pfe_commands.c
 890 new file mode 100644
 891 index 0000000..f9f92c7
 892 --- /dev/null
 893 +++ b/common/cmd_pfe_commands.c
 894 @@ -0,0 +1,983 @@
 895 +/*
 896 + * (C) Copyright 2012
 897 + *  Author : Bill Westland (Mindspeed Technologies)
 898 + *
 899 + * See file CREDITS for list of people who contributed to this
 900 + * project.
 901 + *
 902 + * This program is free software; you can redistribute it and/or
 903 + * modify it under the terms of the GNU General Public License as
 904 + * published by the Free Software Foundation; either version 2 of
 905 + * the License, or (at your option) any later version.
 906 + *
 907 + * This program is distributed in the hope that it will be useful,
 908 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
 909 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 910 + * GNU General Public License for more details.
 911 + *
 912 + * You should have received a copy of the GNU General Public License
 913 + * along with this program; if not, write to the Free Software
 914 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 915 + * MA 02111-1307 USA
 916 + */
 917 +
 918 +/**
 919 + * @file
 920 + * @brief PFE utility commands
 921 + */
 922 +
 923 +#include <common.h>
 924 +#include <command.h>
 925 +#include "../drivers/net/pfe_eth/pfe_eth.h"
 926 +#include "../drivers/net/pfe_eth/pfe/pfe.h"
 927 +#include "../drivers/net/pfe_eth/pfe_firmware.h"
 928 +#include "../drivers/net/pfe_eth/pfe/cbus/class_csr.h"
 929 +#include "../drivers/net/pfe_eth/pfe/cbus/gpi.h"
 930 +DECLARE_GLOBAL_DATA_PTR;
 931 +
 932 +int pfe_load_elf(int pe_mask, const struct firmware *fw);
 933 +int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname);
 934 +
 935 +static void pfe_command_help(void)
 936 +{
 937 +       printf("Usage: pfe [start | firmware | load | lib | pe | gemac | gem | gpi | class | tmu | util | hif | status | expt | fftest] <options>\n");
 938 +}
 939 +
 940 +static void pfe_command_firmware(int argc, char * const argv[])
 941 +{
 942 +       if (argc == 3 && strcmp(argv[2], "init") == 0)
 943 +       {
 944 +               pfe_firmware_init((u8 *)0x80100000, (u8 *)0x80180000, (u8 *)0x80200000);
 945 +       }
 946 +       else if (argc == 3 && strcmp(argv[2], "exit") == 0)
 947 +       {
 948 +               pfe_firmware_exit();
 949 +       }
 950 +       else
 951 +       {
 952 +               if (argc >= 3 && strcmp(argv[2], "help") != 0)
 953 +               {
 954 +                       printf("Unknown option: %s\n", argv[2]);
 955 +               }
 956 +               printf("Usage: pfe firmware [init | exit]\n");
 957 +       }
 958 +}
 959 +
 960 +static void pfe_command_load(int argc, char * const argv[])
 961 +{
 962 +       if (argc >= 3 && strcmp(argv[2], "elf") == 0)
 963 +       {
 964 +               if (argc == 5)
 965 +               {
 966 +                       u32 mask;
 967 +                       unsigned long image_start;
 968 +                       struct firmware fw;
 969 +                       mask = simple_strtoul(argv[3], NULL, 0);
 970 +                       image_start = simple_strtoul(argv[4], NULL, 16);
 971 +                       fw.data = (u8 *)image_start;
 972 +                       pfe_load_elf(mask, &fw);
 973 +               }
 974 +               else
 975 +               {
 976 +                       printf("Usage: pfe load elf <pe_mask> <image_start>\n");
 977 +               }
 978 +       }
 979 +       else
 980 +       {
 981 +               if (argc >= 3 && strcmp(argv[2], "help") != 0)
 982 +               {
 983 +                       printf("Unknown option: %s\n", argv[2]);
 984 +               }
 985 +               printf("Usage: pfe load elf <parameters>\n");
 986 +       }
 987 +}
 988 +#if 0
 989 +static void pfe_command_lib(int argc, char *argv[])
 990 +{
 991 +       if (argc >= 3 && strcmp(argv[2], "init") == 0)
 992 +       {
 993 +               if (argc == 3)
 994 +                       pfe_lib_init((void *)COMCERTO_AXI_HFE_CFG_BASE, (void *)CONFIG_DDR_BASEADDR, CONFIG_DDR_PHYS_BASEADDR);
 995 +               else if (argc == 6)
 996 +               {
 997 +                       u32 cbus_base;
 998 +                       u32 ddr_base;
 999 +                       u32 ddr_phys_base;
1000 +                       cbus_base = simple_strtoul(argv[3], NULL, 16);
1001 +                       ddr_base = simple_strtoul(argv[4], NULL, 16);
1002 +                       ddr_phys_base = simple_strtoul(argv[5], NULL, 16);
1003 +                       pfe_lib_init((void *)cbus_base, (void *)ddr_base, ddr_phys_base);
1004 +               }
1005 +               else
1006 +               {
1007 +                       printf("Usage: pfe lib init [<cbus_base> <ddr_base> <ddr_phys_base>]\n");
1008 +               }
1009 +       }
1010 +       else
1011 +       {
1012 +               if (argc >= 3 && strcmp(argv[2], "help") != 0)
1013 +               {
1014 +                       printf("Unknown option: %s\n", argv[2]);
1015 +               }
1016 +               printf("Usage: pfe lib init <parameters>\n");
1017 +       }
1018 +}
1019 +#endif
1020 +static void pfe_command_pe(int argc, char * const argv[])
1021 +{
1022 +       if (argc >= 3 && strcmp(argv[2], "pmem") == 0)
1023 +       {
1024 +               if (argc >= 4 && strcmp(argv[3], "read") == 0)
1025 +               {
1026 +                       int i;
1027 +                       int num;
1028 +                       int id;
1029 +                       u32 addr;
1030 +                       u32 size;
1031 +                       u32 val;
1032 +                       if (argc == 7)
1033 +                               num = simple_strtoul(argv[6], NULL, 0);
1034 +                       else if (argc == 6)
1035 +                               num = 1;
1036 +                       else
1037 +                       {
1038 +                               printf("Usage: pfe pe pmem read <id> <addr> [<num>]\n");
1039 +                               return;
1040 +                       }
1041 +                       id = simple_strtoul(argv[4], NULL, 0);
1042 +                       addr = simple_strtoul(argv[5], NULL, 16);
1043 +                       size = 4;
1044 +                       for (i = 0; i < num; i++, addr += 4)
1045 +                       {
1046 +                               val = pe_pmem_read(id, addr, size);
1047 +                               val = be32_to_cpu(val);
1048 +                               if(!(i&3)) printf("%08x: ", addr);
1049 +                               printf("%08x%s", val, i == num - 1 || (i & 3) == 3 ? "\n" : " ");
1050 +                       }
1051 +               }
1052 +               else
1053 +               {
1054 +                       printf("Usage: pfe pe pmem read <parameters>\n");
1055 +               }
1056 +       }
1057 +       else if (argc >= 3 && strcmp(argv[2], "dmem") == 0)
1058 +       {
1059 +               if (argc >= 4 && strcmp(argv[3], "read") == 0)
1060 +               {
1061 +                       int i;
1062 +                       int num;
1063 +                       int id;
1064 +                       u32 addr;
1065 +                       u32 size;
1066 +                       u32 val;
1067 +                       if (argc == 7)
1068 +                               num = simple_strtoul(argv[6], NULL, 0);
1069 +                       else if (argc == 6)
1070 +                               num = 1;
1071 +                       else
1072 +                       {
1073 +                               printf("Usage: pfe pe dmem read <id> <addr> [<num>]\n");
1074 +                               return;
1075 +                       }
1076 +                       id = simple_strtoul(argv[4], NULL, 0);
1077 +                       addr = simple_strtoul(argv[5], NULL, 16);
1078 +                       size = 4;
1079 +                       for (i = 0; i < num; i++, addr += 4)
1080 +                       {
1081 +                               val = pe_dmem_read(id, addr, size);
1082 +                               val = be32_to_cpu(val);
1083 +                               if(!(i&3)) printf("%08x: ", addr);
1084 +                               printf("%08x%s", val, i == num - 1 || (i & 3) == 3 ? "\n" : " ");
1085 +                       }
1086 +               }
1087 +               else if (argc >= 4 && strcmp(argv[3], "write") == 0)
1088 +               {
1089 +                       int id;
1090 +                       u32 val;
1091 +                       u32 addr;
1092 +                       u32 size;
1093 +                       if (argc != 7)
1094 +                       {
1095 +                               printf("Usage: pfe pe dmem write <id> <val> <addr>\n");
1096 +                               return;
1097 +                       }
1098 +                       id = simple_strtoul(argv[4], NULL, 0);
1099 +                       val = simple_strtoul(argv[5], NULL, 16);
1100 +                       val = cpu_to_be32(val);
1101 +                       addr = simple_strtoul(argv[6], NULL, 16);
1102 +                       size = 4;
1103 +                       pe_dmem_write(id, val, addr, size);
1104 +               }
1105 +               else
1106 +               {
1107 +                       printf("Usage: pfe pe dmem [read | write] <parameters>\n");
1108 +               }
1109 +       }
1110 +       else if (argc >= 3 && strcmp(argv[2], "lmem") == 0)
1111 +       {
1112 +               if (argc >= 4 && strcmp(argv[3], "read") == 0)
1113 +               {
1114 +                       int i;
1115 +                       int num;
1116 +                       u32 val;
1117 +                       u32 offset;
1118 +                       if (argc == 6)
1119 +                               num = simple_strtoul(argv[5], NULL, 0);
1120 +                       else if (argc == 5)
1121 +                               num = 1;
1122 +                       else
1123 +                       {
1124 +                               printf("Usage: pfe pe lmem read <offset> [<num>]\n");
1125 +                               return;
1126 +                       }
1127 +                       offset = simple_strtoul(argv[4], NULL, 16);
1128 +                       for (i = 0; i < num; i++, offset += 4)
1129 +                       {
1130 +                               pe_lmem_read(&val, 4, offset);
1131 +                               val = be32_to_cpu(val);
1132 +                               printf("%08x%s", val, i == num - 1 || (i & 7) == 7 ? "\n" : " ");
1133 +                       }
1134 +               }
1135 +               else if (argc >= 4 && strcmp(argv[3], "write") == 0)
1136 +               {
1137 +                       u32 val;
1138 +                       u32 offset;
1139 +                       if (argc != 6)
1140 +                       {
1141 +                               printf("Usage: pfe pe lmem write <val> <offset>\n");
1142 +                               return;
1143 +                       }
1144 +                       val = simple_strtoul(argv[4], NULL, 16);
1145 +                       val = cpu_to_be32(val);
1146 +                       offset = simple_strtoul(argv[5], NULL, 16);
1147 +                       pe_lmem_write(&val, 4, offset);
1148 +               }
1149 +               else
1150 +               {
1151 +                       printf("Usage: pfe pe lmem [read | write] <parameters>\n");
1152 +               }
1153 +       }
1154 +       else
1155 +       {
1156 +               if (strcmp(argv[2], "help") != 0)
1157 +               {
1158 +                       printf("Unknown option: %s\n", argv[2]);
1159 +               }
1160 +               printf("Usage: pfe pe <parameters>\n");
1161 +       }
1162 +       //void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len)
1163 +       //void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
1164 +       //void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
1165 +       //int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
1166 +}
1167 +
1168 +#if 0
1169 +static void pfe_command_gemac(int argc, char *argv[])
1170 +{
1171 +void gemac_init(void *base, void *cfg)
1172 +void gemac_set_speed(void *base, MAC_SPEED gem_speed)
1173 +void gemac_set_duplex(void *base, int duplex)
1174 +void gemac_set_mode(void *base, int mode)
1175 +void gemac_reset(void *base)
1176 +void gemac_enable(void *base)
1177 +void gemac_disable(void *base)
1178 +void gemac_set_address(void *base, SPEC_ADDR *addr)
1179 +SPEC_ADDR gemac_get_address(void *base)
1180 +void gemac_set_laddr1(void *base, MAC_ADDR *address)
1181 +void gemac_set_laddr2(void *base, MAC_ADDR *address)
1182 +void gemac_set_laddr3(void *base, MAC_ADDR *address)
1183 +void gemac_set_laddr4(void *base, MAC_ADDR *address)
1184 +void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index)
1185 +void gemac_allow_broadcast(void *base)
1186 +void gemac_no_broadcast(void *base)
1187 +void gemac_enable_unicast(void *base)
1188 +void gemac_disable_unicast(void *base)
1189 +void gemac_enable_multicast(void *base)
1190 +void gemac_disable_multicast(void *base)
1191 +void gemac_enable_fcs_rx(void *base)
1192 +void gemac_disable_fcs_rx(void *base)
1193 +void gemac_enable_1536_rx(void *base)
1194 +void gemac_disable_1536_rx(void *base)
1195 +void gemac_enable_pause_rx(void *base)
1196 +void gemac_disable_pause_rx(void *base)
1197 +void gemac_set_config(void *base, GEMAC_CFG *cfg)
1198 +unsigned int * gemac_get_stats(void *base)
1199 +}
1200 +#endif
1201 +
1202 +#if 0
1203 +static void pfe_command_gem(int argc, char *argv[])
1204 +{
1205 +MAC_ADDR gem_get_laddr1(void *base)
1206 +MAC_ADDR gem_get_laddr2(void *base)
1207 +MAC_ADDR gem_get_laddr3(void *base)
1208 +MAC_ADDR gem_get_laddr4(void *base)
1209 +MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index)
1210 +}
1211 +#endif
1212 +
1213 +#if 0
1214 +static void pfe_command_gpi(int argc, char *argv[])
1215 +{
1216 +void gpi_init(void *base, GPI_CFG *cfg)
1217 +void gpi_reset(void *base)
1218 +void gpi_enable(void *base)
1219 +void gpi_disable(void *base)
1220 +void gpi_set_config(void *base, GPI_CFG *cfg)
1221 +}
1222 +#endif
1223 +
1224 +#if 1
1225 +static void pfe_command_class(int argc, char * const argv[])
1226 +{
1227 +       if (argc >= 3 && strcmp(argv[2], "init") == 0)
1228 +       {
1229 +               CLASS_CFG cfg;
1230 +               if (argc == 3)
1231 +               {
1232 +#define CONFIG_DDR_PHYS_BASEADDR       0x03800000
1233 +                       cfg.route_table_hash_bits = ROUTE_TABLE_HASH_BITS;
1234 +                       cfg.route_table_baseaddr = CONFIG_DDR_PHYS_BASEADDR + ROUTE_TABLE_BASEADDR;
1235 +               }
1236 +               else if (argc == 5)
1237 +               {
1238 +                       cfg.route_table_hash_bits = simple_strtoul(argv[3], NULL, 16);
1239 +                       cfg.route_table_baseaddr = simple_strtoul(argv[4], NULL, 16);
1240 +               }
1241 +               else
1242 +               {
1243 +                       printf("Usage: pfe class init <route_table_hash_bits> <route_table_baseaddr>\n");
1244 +               }
1245 +               class_init(&cfg);
1246 +       }
1247 +       else if (argc == 3 && strcmp(argv[2], "reset") == 0)
1248 +       {
1249 +               class_reset();
1250 +       }
1251 +       else if (argc == 3 && strcmp(argv[2], "enable") == 0)
1252 +       {
1253 +               class_enable();
1254 +       }
1255 +       else if (argc == 3 && strcmp(argv[2], "disable") == 0)
1256 +       {
1257 +               class_disable();
1258 +       }
1259 +       else if (argc >= 3 && strcmp(argv[2], "config") == 0)
1260 +       {
1261 +               CLASS_CFG cfg;
1262 +               if (argc == 3)
1263 +               {
1264 +                       cfg.route_table_hash_bits = ROUTE_TABLE_HASH_BITS;
1265 +                       cfg.route_table_baseaddr = CONFIG_DDR_PHYS_BASEADDR + ROUTE_TABLE_BASEADDR;
1266 +               }
1267 +               else if (argc == 5)
1268 +               {
1269 +                       cfg.route_table_hash_bits = simple_strtoul(argv[3], NULL, 16);
1270 +                       cfg.route_table_baseaddr = simple_strtoul(argv[4], NULL, 16);
1271 +               }
1272 +               else
1273 +               {
1274 +                       printf("Usage: pfe class config <route_table_hash_bits> <route_table_baseaddr>\n");
1275 +               }
1276 +               class_set_config(&cfg);
1277 +       }
1278 +       else if (argc >= 3 && strcmp(argv[2], "bus") == 0)
1279 +       {
1280 +               if (argc >= 4 && strcmp(argv[3], "read") == 0)
1281 +               {
1282 +                       u32 addr;
1283 +                       u32 size;
1284 +                       u32 val;
1285 +                       if (argc != 6)
1286 +                       {
1287 +                               printf("Usage: pfe class bus read <addr> <size>\n");
1288 +                               return;
1289 +                       }
1290 +                       addr = simple_strtoul(argv[4], NULL, 16);
1291 +                       size = simple_strtoul(argv[5], NULL, 16);
1292 +                       val = class_bus_read(addr, size);
1293 +                       printf("%08x\n", val);
1294 +               }
1295 +               else if (argc >= 4 && strcmp(argv[3], "write") == 0)
1296 +               {
1297 +                       u32 val;
1298 +                       u32 addr;
1299 +                       u32 size;
1300 +                       if (argc != 7)
1301 +                       {
1302 +                               printf("Usage: pfe class bus write <val> <addr> <size>\n");
1303 +                               return;
1304 +                       }
1305 +                       val = simple_strtoul(argv[4], NULL, 16);
1306 +                       addr = simple_strtoul(argv[5], NULL, 16);
1307 +                       size = simple_strtoul(argv[6], NULL, 16);
1308 +                       class_bus_write(val, addr, size);
1309 +               }
1310 +               else
1311 +               {
1312 +                       printf("Usage: pfe class bus [read | write] <parameters>\n");
1313 +               }
1314 +       }
1315 +       else
1316 +       {
1317 +               if (argc >= 3 && strcmp(argv[2], "help") != 0)
1318 +               {
1319 +                       printf("Unknown option: %s\n", argv[2]);
1320 +               }
1321 +               printf("Usage: pfe class [init | reset | enable | disable | config | bus] <parameters>\n");
1322 +       }
1323 +}
1324 +
1325 +static void pfe_command_tmu(int argc, char * const argv[])
1326 +{
1327 +       if (argc >= 3 && strcmp(argv[2], "init") == 0)
1328 +       {
1329 +               if (argc == 5)
1330 +               {
1331 +                       TMU_CFG cfg;
1332 +                       cfg.llm_base_addr = simple_strtoul(argv[3], NULL, 16);
1333 +                       cfg.llm_queue_len = simple_strtoul(argv[4], NULL, 16);
1334 +                       tmu_init(&cfg);
1335 +               }
1336 +               else
1337 +               {
1338 +                       printf("Usage: pfe tmu init <llm_base_addr> <llm_queue_len>\n");
1339 +               }
1340 +       }
1341 +       else if (argc >= 3 && strcmp(argv[2], "enable") == 0)
1342 +       {
1343 +               if (argc == 4)
1344 +               {
1345 +                       u32 mask;
1346 +                       mask = simple_strtoul(argv[3], NULL, 16);
1347 +                       tmu_enable(mask);
1348 +               }
1349 +               else
1350 +               {
1351 +                       printf("Usage: pfe tmu enable <pe_mask>\n");
1352 +               }
1353 +       }
1354 +       else if (argc >= 3 && strcmp(argv[2], "disable") == 0)
1355 +       {
1356 +               if (argc == 4)
1357 +               {
1358 +                       u32 mask;
1359 +                       mask = simple_strtoul(argv[3], NULL, 16);
1360 +                       tmu_disable(mask);
1361 +               }
1362 +               else
1363 +               {
1364 +                       printf("Usage: pfe tmu disable <pe_mask>\n");
1365 +               }
1366 +       }
1367 +       else
1368 +       {
1369 +               if (argc >= 3 && strcmp(argv[2], "help") != 0)
1370 +               {
1371 +                       printf("Unknown option: %s\n", argv[2]);
1372 +               }
1373 +               printf("Usage: pfe tmu [init | enable | disable] <parameters>\n");
1374 +       }
1375 +}
1376 +#endif
1377 +
1378 +/** qm_read_drop_stat
1379 + * This function is used to read the drop statistics from the TMU
1380 + * hw drop counter.  Since the hw counter is always cleared afer
1381 + * reading, this function maintains the previous drop count, and
1382 + * adds the new value to it.  That value can be retrieved by
1383 + * passing a pointer to it with the total_drops arg.
1384 + *
1385 + * @param tmu           TMU number (0 - 3)
1386 + * @param queue         queue number (0 - 15)
1387 + * @param total_drops   pointer to location to store total drops (or NULL)
1388 + * @param do_reset      if TRUE, clear total drops after updating
1389 + *
1390 + */
1391 +
1392 +u32 qm_read_drop_stat(u32 tmu, u32 queue, u32 *total_drops, int do_reset)
1393 +{
1394 +#define NUM_QUEUES             16
1395 +       static u32 qtotal[TMU_MAX_ID + 1][NUM_QUEUES];
1396 +       u32 val;
1397 +       writel((tmu << 8) | queue, TMU_TEQ_CTRL);
1398 +       writel((tmu << 8) | queue, TMU_LLM_CTRL);
1399 +       val = readl(TMU_TEQ_DROP_STAT);
1400 +       qtotal[tmu][queue] += val;
1401 +       if (total_drops)
1402 +               *total_drops = qtotal[tmu][queue];
1403 +       if (do_reset)
1404 +               qtotal[tmu][queue] = 0;
1405 +       return val;
1406 +}
1407 +
1408 +static ssize_t tmu_queue_stats(char *buf, int tmu, int queue)
1409 +{
1410 +       ssize_t len = 0;
1411 +       u32 drops;
1412 +
1413 +       printf("%d-%02d, ", tmu, queue);
1414 +
1415 +       drops = qm_read_drop_stat(tmu, queue, NULL, 0);
1416 +
1417 +       /* Select queue */
1418 +       writel((tmu << 8) | queue, TMU_TEQ_CTRL);
1419 +       writel((tmu << 8) | queue, TMU_LLM_CTRL);
1420 +
1421 +       printf("(teq) drop: %10u, tx: %10u (llm) head: %08x, tail: %08x, drop: %10u\n",
1422 +                       drops, readl(TMU_TEQ_TRANS_STAT),
1423 +                       readl(TMU_LLM_QUE_HEADPTR), readl(TMU_LLM_QUE_TAILPTR),
1424 +                       readl(TMU_LLM_QUE_DROPCNT));
1425 +
1426 +       return len;
1427 +}
1428 +
1429 +
1430 +static ssize_t tmu_queues(char *buf, int tmu)
1431 +{
1432 +       ssize_t len = 0;
1433 +       int queue;
1434 +
1435 +       for (queue = 0; queue < 16; queue++)
1436 +               len += tmu_queue_stats(buf + len, tmu, queue);
1437 +
1438 +       return len;
1439 +}
1440 +
1441 +void hif_status(void)
1442 +{
1443 +       printf("hif:\n");
1444 +
1445 +       printf("  tx curr bd:    %x\n", readl(HIF_TX_CURR_BD_ADDR));
1446 +       printf("  tx status:     %x\n", readl(HIF_TX_STATUS));
1447 +       printf("  tx dma status: %x\n", readl(HIF_TX_DMA_STATUS));
1448 +
1449 +       printf("  rx curr bd:    %x\n", readl(HIF_RX_CURR_BD_ADDR));
1450 +       printf("  rx status:     %x\n", readl(HIF_RX_STATUS));
1451 +       printf("  rx dma status: %x\n", readl(HIF_RX_DMA_STATUS));
1452 +
1453 +       printf("hif nocopy:\n");
1454 +
1455 +       printf("  tx curr bd:    %x\n", readl(HIF_NOCPY_TX_CURR_BD_ADDR));
1456 +       printf("  tx status:     %x\n", readl(HIF_NOCPY_TX_STATUS));
1457 +       printf("  tx dma status: %x\n", readl(HIF_NOCPY_TX_DMA_STATUS));
1458 +
1459 +       printf("  rx curr bd:    %x\n", readl(HIF_NOCPY_RX_CURR_BD_ADDR));
1460 +       printf("  rx status:     %x\n", readl(HIF_NOCPY_RX_STATUS));
1461 +       printf("  rx dma status: %x\n", readl(HIF_NOCPY_RX_DMA_STATUS));
1462 +}
1463 +
1464 +static void  gpi(int id, void *base)
1465 +{
1466 +        u32 val;
1467 +
1468 +        printf("gpi%d:\n  ", id);
1469 +
1470 +        printf("  tx under stick: %x\n", readl(base + GPI_FIFO_STATUS));
1471 +        val = readl(base + GPI_FIFO_DEBUG);
1472 +        printf("  tx pkts:        %x\n", (val >> 23) & 0x3f);
1473 +        printf("  rx pkts:        %x\n", (val >> 18) & 0x3f);
1474 +        printf("  tx bytes:       %x\n", (val >> 9) & 0x1ff);
1475 +        printf("  rx bytes:       %x\n", (val >> 0) & 0x1ff);
1476 +        printf("  overrun:        %x\n", readl(base + GPI_OVERRUN_DROPCNT));
1477 +}
1478 +
1479 +void  bmu(int id, void *base)
1480 +{
1481 +       printf("bmu: %d\n", id);
1482 +       printf("  buf size:  %x\n", (1 << readl(base + BMU_BUF_SIZE)));
1483 +       printf("  buf count: %x\n", readl(base + BMU_BUF_CNT));
1484 +       printf("  buf rem:   %x\n", readl(base + BMU_REM_BUF_CNT));
1485 +       printf("  buf curr:  %x\n", readl(base + BMU_CURR_BUF_CNT));
1486 +       printf("  free err:  %x\n", readl(base + BMU_FREE_ERR_ADDR));
1487 +}
1488 +
1489 +#define        PESTATUS_ADDR_CLASS     0x800
1490 +#define        PESTATUS_ADDR_TMU       0x80
1491 +#define        PESTATUS_ADDR_UTIL      0x0
1492 +
1493 +static void pfe_pe_status(int argc, char * const argv[])
1494 +{
1495 +       int do_clear = 0;
1496 +       int j;
1497 +       u32 id;
1498 +       u32 dmem_addr;
1499 +       u32 cpu_state;
1500 +       u32 activity_counter;
1501 +       u32 rx;
1502 +       u32 tx;
1503 +       u32 drop;
1504 +       char statebuf[5];
1505 +       u32 class_debug_reg = 0;
1506 +       u32 debug_indicator;
1507 +       u32 debug[16];
1508 +
1509 +       if (argc == 4 && strcmp(argv[3], "clear") == 0)
1510 +               do_clear = 1;
1511 +
1512 +       for (id = CLASS0_ID; id < MAX_PE; id++)
1513 +       {
1514 +#if !defined(CONFIG_UTIL_PE_DISABLED)
1515 +               if (id == UTIL_ID)
1516 +               {
1517 +                       printf("util:\n");
1518 +                       dmem_addr = PESTATUS_ADDR_UTIL;
1519 +               }
1520 +               else if (id >= TMU0_ID)
1521 +#else
1522 +               if (id >= TMU0_ID)
1523 +#endif
1524 +               {
1525 +                       if (id == TMU2_ID)
1526 +                               continue;
1527 +                       if (id == TMU0_ID)
1528 +                               printf("tmu:\n");
1529 +                       dmem_addr = PESTATUS_ADDR_TMU;
1530 +               }
1531 +               else
1532 +               {
1533 +                       if (id == CLASS0_ID)
1534 +                               printf("class:\n");
1535 +                       dmem_addr = PESTATUS_ADDR_CLASS;
1536 +                       class_debug_reg = readl(CLASS_PE0_DEBUG + id * 4);
1537 +               }
1538 +               cpu_state = pe_dmem_read(id, dmem_addr, 4);
1539 +               dmem_addr += 4;
1540 +               memcpy(statebuf, (char *)&cpu_state, 4);
1541 +               statebuf[4] = '\0';
1542 +               activity_counter = pe_dmem_read(id, dmem_addr, 4);
1543 +               dmem_addr += 4;
1544 +               rx = pe_dmem_read(id, dmem_addr, 4);
1545 +               if (do_clear)
1546 +                       pe_dmem_write(id, 0, dmem_addr, 4);
1547 +               dmem_addr += 4;
1548 +               tx = pe_dmem_read(id, dmem_addr, 4);
1549 +               if (do_clear)
1550 +                       pe_dmem_write(id, 0, dmem_addr, 4);
1551 +               dmem_addr += 4;
1552 +               drop = pe_dmem_read(id, dmem_addr, 4);
1553 +               if (do_clear)
1554 +                       pe_dmem_write(id, 0, dmem_addr, 4);
1555 +               dmem_addr += 4;
1556 +#if !defined(CONFIG_UTIL_PE_DISABLED)
1557 +               if (id == UTIL_ID)
1558 +               {
1559 +                       printf("state=%4s ctr=%08x rx=%x tx=%x\n",
1560 +                                       statebuf, cpu_to_be32(activity_counter),
1561 +                                       cpu_to_be32(rx), cpu_to_be32(tx));
1562 +               }
1563 +               else
1564 +#endif
1565 +               if (id >= TMU0_ID)
1566 +               {
1567 +                       printf("%d: state=%4s ctr=%08x rx=%x qstatus=%x\n",
1568 +                                       id - TMU0_ID, statebuf, cpu_to_be32(activity_counter),
1569 +                                       cpu_to_be32(rx), cpu_to_be32(tx));
1570 +               }
1571 +               else
1572 +               {
1573 +                       printf("%d: pc=1%04x ldst=%04x state=%4s ctr=%08x rx=%x tx=%x drop=%x\n",
1574 +                                       id - CLASS0_ID, class_debug_reg & 0xFFFF, class_debug_reg >> 16,
1575 +                                       statebuf, cpu_to_be32(activity_counter),
1576 +                                       cpu_to_be32(rx), cpu_to_be32(tx), cpu_to_be32(drop));
1577 +               }
1578 +               debug_indicator = pe_dmem_read(id, dmem_addr, 4);
1579 +               dmem_addr += 4;
1580 +               if (debug_indicator == cpu_to_be32('DBUG'))
1581 +               {
1582 +                       int last = 0;
1583 +                       for (j = 0; j < 16; j++)
1584 +                       {
1585 +                               debug[j] = pe_dmem_read(id, dmem_addr, 4);
1586 +                               if (debug[j])
1587 +                               {
1588 +                                       last = j + 1;
1589 +                                       if (do_clear)
1590 +                                               pe_dmem_write(id, 0, dmem_addr, 4);
1591 +                               }
1592 +                               dmem_addr += 4;
1593 +                       }
1594 +                       for (j = 0; j < last; j++)
1595 +                       {
1596 +                               printf("%08x%s", cpu_to_be32(debug[j]), (j & 0x7) == 0x7 || j == last - 1 ? "\n" : " ");
1597 +                       }
1598 +               }
1599 +       }
1600 +
1601 +}
1602 +
1603 +static void pfe_command_status(int argc, char * const argv[])
1604 +{
1605 +
1606 +       if (argc >= 3 && strcmp(argv[2], "pe") == 0)
1607 +       {
1608 +               pfe_pe_status(argc, argv);
1609 +       }
1610 +       else if (argc == 3 && strcmp(argv[2], "bmu") == 0)
1611 +       {
1612 +               bmu(1, BMU1_BASE_ADDR);
1613 +               bmu(2, BMU2_BASE_ADDR);
1614 +       }
1615 +       else if (argc == 3 && strcmp(argv[2], "hif") == 0)
1616 +       {
1617 +               hif_status();
1618 +       }
1619 +       else if (argc == 3 && strcmp(argv[2], "gpi") == 0)
1620 +       {
1621 +               gpi(0, EGPI1_BASE_ADDR);
1622 +               gpi(1, EGPI2_BASE_ADDR);
1623 +               gpi(3, HGPI_BASE_ADDR);
1624 +       }
1625 +       else if (argc == 3 && strcmp(argv[2], "tmu0_queues") == 0)
1626 +       {
1627 +               tmu_queues(NULL, 0);
1628 +       }
1629 +       else if (argc == 3 && strcmp(argv[2], "tmu1_queues") == 0)
1630 +       {
1631 +               tmu_queues(NULL, 1);
1632 +       }
1633 +       else if (argc == 3 && strcmp(argv[2], "tmu3_queues") == 0)
1634 +       {
1635 +               tmu_queues(NULL, 3);
1636 +       }
1637 +       else
1638 +               printf("Usage: pfe status [pe <clear> | bmu | gpi | hif | tmuX_queues ]\n");
1639 +
1640 +       return;
1641 +}
1642 +
1643 +
1644 +#define EXPT_DUMP_ADDR 0x1fa8
1645 +#define EXPT_REG_COUNT 20
1646 +static const char *register_names[EXPT_REG_COUNT] = {
1647 +               "  pc", "ECAS", " EID", "  ED",
1648 +               "  sp", "  r1", "  r2", "  r3",
1649 +               "  r4", "  r5", "  r6", "  r7",
1650 +               "  r8", "  r9", " r10", " r11",
1651 +               " r12", " r13", " r14", " r15"
1652 +};
1653 +
1654 +static void pfe_command_expt(int argc, char * const argv[])
1655 +{
1656 +       unsigned int id, i, val, addr;
1657 +
1658 +       if (argc == 3)
1659 +       {
1660 +               id = simple_strtoul(argv[2], NULL, 0);
1661 +               addr = EXPT_DUMP_ADDR;
1662 +               printf("Exception information for PE %d:\n", id);
1663 +               for (i = 0; i < EXPT_REG_COUNT; i++)
1664 +               {
1665 +                       val = pe_dmem_read(id, addr, 4);
1666 +                       val = be32_to_cpu(val);
1667 +                       printf("%s:%08x%s", register_names[i], val, (i & 3) == 3 ? "\n" : " ");
1668 +                       addr += 4;
1669 +               }
1670 +       }
1671 +       else
1672 +       {
1673 +               printf("Usage: pfe expt <id>\n");
1674 +       }
1675 +}
1676 +
1677 +static void pfe_command_util(int argc, char * const argv[])
1678 +{
1679 +       if (argc == 3 && strcmp(argv[2], "init") == 0)
1680 +       {
1681 +               UTIL_CFG cfg;
1682 +               util_init(&cfg);
1683 +       }
1684 +       else if (argc == 3 && strcmp(argv[2], "reset") == 0)
1685 +       {
1686 +               util_reset();
1687 +       }
1688 +       else if (argc == 3 && strcmp(argv[2], "enable") == 0)
1689 +       {
1690 +               util_enable();
1691 +       }
1692 +       else if (argc == 3 && strcmp(argv[2], "disable") == 0)
1693 +       {
1694 +               util_disable();
1695 +       }
1696 +       else if (argc >= 3 && strcmp(argv[2], "bus") == 0)
1697 +               {
1698 +                       if (argc >= 4 && strcmp(argv[3], "read") == 0)
1699 +                       {
1700 +                               u32 addr;
1701 +                               u32 size;
1702 +                               u32 val;
1703 +                               if (argc != 6)
1704 +                               {
1705 +                                       printf("Usage: pfe util bus read <addr> <size>\n");
1706 +                                       return;
1707 +                               }
1708 +                               addr = simple_strtoul(argv[4], NULL, 16);
1709 +                               size = simple_strtoul(argv[5], NULL, 16);
1710 +                               val = util_bus_read(addr, size);
1711 +                               printf("%08x\n", val);
1712 +                       }
1713 +                       else if (argc >= 4 && strcmp(argv[3], "write") == 0)
1714 +                       {
1715 +                               u32 val;
1716 +                               u32 addr;
1717 +                               u32 size;
1718 +                               if (argc != 7)
1719 +                               {
1720 +                                       printf("Usage: pfe util bus write <val> <addr> <size>\n");
1721 +                                       return;
1722 +                               }
1723 +                               val = simple_strtoul(argv[4], NULL, 16);
1724 +                               addr = simple_strtoul(argv[5], NULL, 16);
1725 +                               size = simple_strtoul(argv[6], NULL, 16);
1726 +                               util_bus_write(val, addr, size);
1727 +                       }
1728 +                       else
1729 +                       {
1730 +                               printf("Usage: pfe util bus [read | write] <parameters>\n");
1731 +                       }
1732 +               }
1733 +       else
1734 +       {
1735 +               if (argc >= 3 && strcmp(argv[2], "help") != 0)
1736 +               {
1737 +                       printf("Unknown option: %s\n", argv[2]);
1738 +               }
1739 +               printf("Usage: pfe util [init | reset | enable | disable | bus] <parameters>\n");
1740 +       }
1741 +}
1742 +
1743 +#if 0
1744 +static void pfe_command_hif(int argc, char *argv[])
1745 +{
1746 +void hif_nocpy_init(void)
1747 +void hif_init(void)
1748 +void hif_tx_enable(void)
1749 +void hif_tx_disable(void)
1750 +void hif_rx_enable(void)
1751 +void hif_rx_disable(void)
1752 +}
1753 +#endif
1754 +
1755 +#define ROUTE_TABLE_START      (CONFIG_DDR_PHYS_BASEADDR+ROUTE_TABLE_BASEADDR)
1756 +static void pfe_command_fftest(int argc, char * const argv[])
1757 +{
1758 +       bd_t *bd = gd->bd;
1759 +       struct eth_device *edev_eth0;
1760 +       struct eth_device *edev_eth1;
1761 +
1762 +
1763 +       // open eth0 and eth1
1764 +       edev_eth0 = eth_get_dev_by_name("pfe_eth0");
1765 +       if (!edev_eth0)
1766 +       {
1767 +               printf("Cannot access eth0\n");
1768 +               return;
1769 +       }
1770 +
1771 +       if (eth_write_hwaddr(edev_eth0, "eth", edev_eth0->index))
1772 +               puts("\nWarning: failed to set MAC address for c2000_gemac0\n");
1773 +
1774 +       if (edev_eth0->state != ETH_STATE_ACTIVE)
1775 +       {
1776 +               if (edev_eth0->init(edev_eth0, bd) < 0) {
1777 +                       printf("eth0 init failed\n");
1778 +                       return;
1779 +               }
1780 +               edev_eth0->state = ETH_STATE_ACTIVE;
1781 +       }
1782 +
1783 +       edev_eth1 = eth_get_dev_by_name("pfe_eth1");
1784 +       if (!edev_eth1)
1785 +       {
1786 +               printf("Cannot access eth1\n");
1787 +               return;
1788 +       }
1789 +
1790 +       if (eth_write_hwaddr(edev_eth1, "eth", edev_eth1->index))
1791 +               puts("\nWarning: failed to set MAC address for c2000_gemac1\n");
1792 +
1793 +       if (edev_eth1->state != ETH_STATE_ACTIVE)
1794 +       {
1795 +               if (edev_eth1->init(edev_eth1, bd) < 0) {
1796 +                       printf("eth1 init failed\n");
1797 +                       return;
1798 +               }
1799 +               edev_eth1->state = ETH_STATE_ACTIVE;
1800 +       }
1801 +
1802 +}
1803 +
1804 +#ifdef CONFIG_CMD_PFE_START
1805 +static void pfe_command_start(int argc, char * const argv[])
1806 +{
1807 +       printf("Starting PFE \n");
1808 +       ls1012a_gemac_initialize(gd->bd, 0 , "pfe_eth0");
1809 +       ls1012a_gemac_initialize(gd->bd, 1 , "pfe_eth1");
1810 +}
1811 +#endif
1812 +
1813 +
1814 +static int pfe_command(cmd_tbl_t *cmdtp, int flag, int argc,
1815 +                      char * const argv[])
1816 +{
1817 +       if (argc == 1 || strcmp(argv[1], "help") == 0)
1818 +       {
1819 +               pfe_command_help();
1820 +               return CMD_RET_SUCCESS;
1821 +       }
1822 +       if (strcmp(argv[1], "firmware") == 0)
1823 +               pfe_command_firmware(argc, argv);
1824 +       else if (strcmp(argv[1], "load") == 0)
1825 +               pfe_command_load(argc, argv);
1826 +#if 0
1827 +       else if (strcmp(argv[1], "lib") == 0)
1828 +               pfe_command_lib(argc, argv);
1829 +#endif
1830 +       else if (strcmp(argv[1], "pe") == 0)
1831 +               pfe_command_pe(argc, argv);
1832 +#if 0
1833 +       else if (strcmp(argv[1], "gemac") == 0)
1834 +               pfe_command_gemac(argc, argv);
1835 +       else if (strcmp(argv[1], "gem") == 0)
1836 +               pfe_command_gem(argc, argv);
1837 +       else if (strcmp(argv[1], "gpi") == 0)
1838 +               pfe_command_gpi(argc, argv);
1839 +#endif
1840 +#if 1
1841 +       else if (strcmp(argv[1], "class") == 0)
1842 +               pfe_command_class(argc, argv);
1843 +       else if (strcmp(argv[1], "tmu") == 0)
1844 +               pfe_command_tmu(argc, argv);
1845 +#endif
1846 +       else if (strcmp(argv[1], "status") == 0)
1847 +               pfe_command_status(argc, argv);
1848 +       else if (strcmp(argv[1], "expt") == 0)
1849 +               pfe_command_expt(argc, argv);
1850 +       else if (strcmp(argv[1], "util") == 0)
1851 +               pfe_command_util(argc, argv);
1852 +#if 0
1853 +       else if (strcmp(argv[1], "hif") == 0)
1854 +               pfe_command_hif(argc, argv);
1855 +#endif
1856 +       else if (strcmp(argv[1], "fftest") == 0)
1857 +               pfe_command_fftest(argc, argv);
1858 +#ifdef CONFIG_CMD_PFE_START
1859 +       else if (strcmp(argv[1], "start") == 0)
1860 +               pfe_command_start(argc, argv);
1861 +#endif
1862 +       else
1863 +       {
1864 +               printf("Unknown option: %s\n", argv[1]);
1865 +               pfe_command_help();
1866 +               return CMD_RET_FAILURE;
1867 +       }
1868 +       return CMD_RET_SUCCESS;
1869 +}
1870 +
1871 +
1872 +U_BOOT_CMD(
1873 +       pfe,    7,      1,      pfe_command,
1874 +       "Performs PFE lib utility functions",
1875 +       "Usage: \n"
1876 +       "pfe <options>"
1877 +);
1878 diff --git a/drivers/net/Makefile b/drivers/net/Makefile
1879 index 150470c..c683b8f 100644
1880 --- a/drivers/net/Makefile
1881 +++ b/drivers/net/Makefile
1882 @@ -72,3 +72,4 @@ obj-$(CONFIG_FSL_MC_ENET) += fsl-mc/
1883  obj-$(CONFIG_FSL_MC_ENET) += ldpaa_eth/
1884  obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
1885  obj-$(CONFIG_VSC9953) += vsc9953.o
1886 +obj-$(CONFIG_FSL_PPFE) += pfe_eth/
1887 diff --git a/drivers/net/pfe_eth/Makefile b/drivers/net/pfe_eth/Makefile
1888 new file mode 100644
1889 index 0000000..1af837d
1890 --- /dev/null
1891 +++ b/drivers/net/pfe_eth/Makefile
1892 @@ -0,0 +1 @@
1893 +obj-y += pfe_eth.o pfe_firmware.o pfe.o pfe_driver.o
1894 diff --git a/drivers/net/pfe_eth/class_sbl_elf.fw b/drivers/net/pfe_eth/class_sbl_elf.fw
1895 new file mode 100644
1896 index 0000000..3745d9a
1897 --- /dev/null
1898 +++ b/drivers/net/pfe_eth/class_sbl_elf.fw
1899 @@ -0,0 +1 @@
1900 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1901 \ No newline at end of file
1902 diff --git a/drivers/net/pfe_eth/hal.h b/drivers/net/pfe_eth/hal.h
1903 new file mode 100644
1904 index 0000000..e795fe6
1905 --- /dev/null
1906 +++ b/drivers/net/pfe_eth/hal.h
1907 @@ -0,0 +1,64 @@
1908 +/*
1909 + *  (C) Copyright 2011
1910 + *  Author : Mindspeed Technologes
1911 + *
1912 + *  See file CREDITS for list of people who contributed to this
1913 + *  project.
1914 + *
1915 + *  This program is free software; you can redistribute it and/or
1916 + *  modify it under the terms of the GNU General Public License as
1917 + *  published by the Free Software Foundation; either version 2 of
1918 + *  the License, or (at your option) any later version.
1919 + *
1920 + *  This program is distributed in the hope that it will be useful,
1921 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
1922 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
1923 + *  GNU General Public License for more details.
1924 + *
1925 + *  You should have received a copy of the GNU General Public License
1926 + *  along with this program; if not, write to the Free Software
1927 + *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
1928 + *  MA 02111-1307 USA
1929 + * */
1930 +
1931 +#ifndef _HAL_H_
1932 +#define _HAL_H_
1933 +
1934 +#if defined(CONFIG_PLATFORM_PCI)
1935 +/* For ChipIT */
1936 +
1937 +#include <linux/types.h>
1938 +#include <linux/elf.h>
1939 +#include <linux/errno.h>
1940 +#include <linux/pci.h>
1941 +#include <asm/io.h>
1942 +#include <linux/slab.h>
1943 +#include <linux/firmware.h>
1944 +
1945 +
1946 +#define free(x)  kfree(x)
1947 +#define xzalloc(x)  kmalloc(x, GFP_DMA)
1948 +#define printf  printk
1949 +
1950 +//#define dprint(fmt, arg...)  printk(fmt, ##arg)
1951 +#define dprint(fmt, arg...)
1952 +
1953 +#else
1954 +
1955 +#include <linux/types.h>
1956 +#include <elf.h>
1957 +#include <common.h>
1958 +//#include <errno.h>
1959 +#include <asm/byteorder.h>
1960 +#include <miiphy.h>
1961 +#include <malloc.h>
1962 +#include <asm/io.h>
1963 +
1964 +
1965 +#include "pfe_eth.h"
1966 +
1967 +#endif
1968 +
1969 +
1970 +#endif /* _HAL_H_ */
1971 +
1972 diff --git a/drivers/net/pfe_eth/pfe.c b/drivers/net/pfe_eth/pfe.c
1973 new file mode 100644
1974 index 0000000..3b5570a
1975 --- /dev/null
1976 +++ b/drivers/net/pfe_eth/pfe.c
1977 @@ -0,0 +1,1677 @@
1978 +#include "hal.h"
1979 +#include "pfe/pfe.h"
1980 +
1981 +void *cbus_base_addr;
1982 +void *ddr_base_addr;
1983 +unsigned long ddr_phys_base_addr;
1984 +#if 0
1985 +#define dprintf(fmt, arg...) printf(fmt, ##arg)
1986 +#else
1987 +#define dprintf(fmt, arg...)
1988 +#endif
1989 +static struct pe_info pe[MAX_PE];
1990 +
1991 +/** Initializes the PFE library.
1992 +* Must be called before using any of the library functions.
1993 +*
1994 +* @param[in] cbus_base         CBUS virtual base address (as mapped in the host CPU address space)
1995 +* @param[in] ddr_base          DDR virtual base address (as mapped in the host CPU address space)
1996 +* @param[in] ddr_phys_base     DDR physical base address (as mapped in platform)
1997 +*/
1998 +void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base)
1999 +{
2000 +       cbus_base_addr = cbus_base;
2001 +       ddr_base_addr = ddr_base;
2002 +       ddr_phys_base_addr = ddr_phys_base;
2003 +
2004 +       pe[CLASS0_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(0);
2005 +       pe[CLASS0_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(0);
2006 +       pe[CLASS0_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
2007 +       pe[CLASS0_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
2008 +       pe[CLASS0_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
2009 +       pe[CLASS0_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
2010 +
2011 +       pe[CLASS1_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(1);
2012 +       pe[CLASS1_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(1);
2013 +       pe[CLASS1_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
2014 +       pe[CLASS1_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
2015 +       pe[CLASS1_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
2016 +       pe[CLASS1_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
2017 +
2018 +       pe[CLASS2_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(2);
2019 +       pe[CLASS2_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(2);
2020 +       pe[CLASS2_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
2021 +       pe[CLASS2_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
2022 +       pe[CLASS2_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
2023 +       pe[CLASS2_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
2024 +
2025 +       pe[CLASS3_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(3);
2026 +       pe[CLASS3_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(3);
2027 +       pe[CLASS3_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
2028 +       pe[CLASS3_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
2029 +       pe[CLASS3_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
2030 +       pe[CLASS3_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
2031 +
2032 +#if !defined(CONFIG_PLATFORM_PCI)
2033 +       pe[CLASS4_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(4);
2034 +       pe[CLASS4_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(4);
2035 +       pe[CLASS4_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
2036 +       pe[CLASS4_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
2037 +       pe[CLASS4_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
2038 +       pe[CLASS4_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
2039 +
2040 +       pe[CLASS5_ID].dmem_base_addr = (u32)CLASS_DMEM_BASE_ADDR(5);
2041 +       pe[CLASS5_ID].pmem_base_addr = (u32)CLASS_IMEM_BASE_ADDR(5);
2042 +       pe[CLASS5_ID].pmem_size = (u32)CLASS_IMEM_SIZE;
2043 +       pe[CLASS5_ID].mem_access_wdata = (void *)CLASS_MEM_ACCESS_WDATA;
2044 +       pe[CLASS5_ID].mem_access_addr = (void *)CLASS_MEM_ACCESS_ADDR;
2045 +       pe[CLASS5_ID].mem_access_rdata = (void *)CLASS_MEM_ACCESS_RDATA;
2046 +#endif
2047 +       pe[TMU0_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(0);
2048 +       pe[TMU0_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(0);
2049 +       pe[TMU0_ID].pmem_size = (u32)TMU_IMEM_SIZE;
2050 +       pe[TMU0_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
2051 +       pe[TMU0_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
2052 +       pe[TMU0_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
2053 +
2054 +#if !defined(CONFIG_TMU_DUMMY)
2055 +       pe[TMU1_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(1);
2056 +       pe[TMU1_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(1);
2057 +       pe[TMU1_ID].pmem_size = (u32)TMU_IMEM_SIZE;
2058 +       pe[TMU1_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
2059 +       pe[TMU1_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
2060 +       pe[TMU1_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
2061 +
2062 +#if !defined(CONFIG_LS1012A)
2063 +       pe[TMU2_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(2);
2064 +       pe[TMU2_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(2);
2065 +       pe[TMU2_ID].pmem_size = (u32)TMU_IMEM_SIZE;
2066 +       pe[TMU2_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
2067 +       pe[TMU2_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
2068 +       pe[TMU2_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
2069 +#endif
2070 +
2071 +       pe[TMU3_ID].dmem_base_addr = (u32)TMU_DMEM_BASE_ADDR(3);
2072 +       pe[TMU3_ID].pmem_base_addr = (u32)TMU_IMEM_BASE_ADDR(3);
2073 +       pe[TMU3_ID].pmem_size = (u32)TMU_IMEM_SIZE;
2074 +       pe[TMU3_ID].mem_access_wdata = (void *)TMU_MEM_ACCESS_WDATA;
2075 +       pe[TMU3_ID].mem_access_addr = (void *)TMU_MEM_ACCESS_ADDR;
2076 +       pe[TMU3_ID].mem_access_rdata = (void *)TMU_MEM_ACCESS_RDATA;
2077 +#endif
2078 +
2079 +#if !defined(CONFIG_UTIL_PE_DISABLED)
2080 +       pe[UTIL_ID].dmem_base_addr = (u32)UTIL_DMEM_BASE_ADDR;
2081 +       pe[UTIL_ID].mem_access_wdata = (void *)UTIL_MEM_ACCESS_WDATA;
2082 +       pe[UTIL_ID].mem_access_addr = (void *)UTIL_MEM_ACCESS_ADDR;
2083 +       pe[UTIL_ID].mem_access_rdata = (void *)UTIL_MEM_ACCESS_RDATA;
2084 +#endif
2085 +}
2086 +
2087 +
2088 +/** Writes a buffer to PE internal memory from the host
2089 + * through indirect access registers.
2090 + *
2091 + * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
2092 + * @param[in] src              Buffer source address
2093 + * @param[in] mem_access_addr  DMEM destination address (must be 32bit aligned)
2094 + * @param[in] len              Number of bytes to copy
2095 + */
2096 +void pe_mem_memcpy_to32(int id, u32 mem_access_addr, const void *src, unsigned int len)
2097 +{
2098 +       u32 offset = 0, val, addr;
2099 +       unsigned int len32 = len >> 2;
2100 +       int i;
2101 +
2102 +       addr = mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, 4);
2103 +
2104 +       for (i = 0; i < len32; i++, offset += 4, src += 4) {
2105 +               val = *(u32 *)src;
2106 +               writel(cpu_to_be32(val), pe[id].mem_access_wdata);
2107 +               writel(addr + offset, pe[id].mem_access_addr);
2108 +       }
2109 +
2110 +       if ((len = (len & 0x3))) {
2111 +               val = 0;
2112 +
2113 +               addr = (mem_access_addr | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(0, len)) + offset;
2114 +
2115 +               for (i = 0; i < len; i++, src++)
2116 +                       val |= (*(u8 *)src) << (8 * i);
2117 +
2118 +               writel(cpu_to_be32(val), pe[id].mem_access_wdata);
2119 +               writel(addr, pe[id].mem_access_addr);
2120 +       }
2121 +}
2122 +
2123 +/** Writes a buffer to PE internal data memory (DMEM) from the host
2124 + * through indirect access registers.
2125 + * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
2126 + * @param[in] src              Buffer source address
2127 + * @param[in] dst              DMEM destination address (must be 32bit aligned)
2128 + * @param[in] len              Number of bytes to copy
2129 + */
2130 +void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
2131 +{
2132 +       pe_mem_memcpy_to32(id, pe[id].dmem_base_addr | dst | PE_MEM_ACCESS_DMEM, src, len);
2133 +}
2134 +
2135 +
2136 +/** Writes a buffer to PE internal program memory (PMEM) from the host
2137 + * through indirect access registers.
2138 + * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
2139 + * @param[in] src              Buffer source address
2140 + * @param[in] dst              PMEM destination address (must be 32bit aligned)
2141 + * @param[in] len              Number of bytes to copy
2142 + */
2143 +void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len)
2144 +{
2145 +       pe_mem_memcpy_to32(id, pe[id].pmem_base_addr | (dst & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_IMEM, src, len);
2146 +}
2147 +
2148 +
2149 +/** Reads PE internal program memory (IMEM) from the host
2150 + * through indirect access registers.
2151 + * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
2152 + * @param[in] addr             PMEM read address (must be aligned on size)
2153 + * @param[in] size             Number of bytes to read (maximum 4, must not cross 32bit boundaries)
2154 + * @return                     the data read (in PE endianess, i.e BE).
2155 + */
2156 +u32 pe_pmem_read(int id, u32 addr, u8 size)
2157 +{
2158 +       u32 offset = addr & 0x3;
2159 +       u32 mask = 0xffffffff >> ((4 - size) << 3);
2160 +       u32 val;
2161 +
2162 +       addr = pe[id].pmem_base_addr | ((addr & ~0x3) & (pe[id].pmem_size - 1)) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_IMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
2163 +
2164 +       writel(addr, pe[id].mem_access_addr);
2165 +       val = be32_to_cpu(readl(pe[id].mem_access_rdata));
2166 +
2167 +       return (val >> (offset << 3)) & mask;
2168 +}
2169 +
2170 +
2171 +/** Writes PE internal data memory (DMEM) from the host
2172 + * through indirect access registers.
2173 + * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
2174 + * @param[in] addr             DMEM write address (must be aligned on size)
2175 + * @param[in] val              Value to write (in PE endianess, i.e BE)
2176 + * @param[in] size             Number of bytes to write (maximum 4, must not cross 32bit boundaries)
2177 + */
2178 +void pe_dmem_write(int id, u32 val, u32 addr, u8 size)
2179 +{
2180 +       u32 offset = addr & 0x3;
2181 +
2182 +       addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
2183 +
2184 +       /* Indirect access interface is byte swapping data being written */
2185 +       writel(cpu_to_be32(val << (offset << 3)), pe[id].mem_access_wdata);
2186 +       writel(addr, pe[id].mem_access_addr);
2187 +}
2188 +
2189 +
2190 +/** Reads PE internal data memory (DMEM) from the host
2191 + * through indirect access registers.
2192 + * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
2193 + * @param[in] addr             DMEM read address (must be aligned on size)
2194 + * @param[in] size             Number of bytes to read (maximum 4, must not cross 32bit boundaries)
2195 + * @return                     the data read (in PE endianess, i.e BE).
2196 + */
2197 +u32 pe_dmem_read(int id, u32 addr, u8 size)
2198 +{
2199 +       u32 offset = addr & 0x3;
2200 +       u32 mask = 0xffffffff >> ((4 - size) << 3);
2201 +       u32 val;
2202 +
2203 +       addr = pe[id].dmem_base_addr | (addr & ~0x3) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_DMEM | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
2204 +
2205 +       writel(addr, pe[id].mem_access_addr);
2206 +
2207 +       /* Indirect access interface is byte swapping data being read */
2208 +       val = be32_to_cpu(readl(pe[id].mem_access_rdata));
2209 +
2210 +       return (val >> (offset << 3)) & mask;
2211 +}
2212 +
2213 +/** This function is used to write to CLASS internal bus peripherals (ccu, pe-lem) from the host
2214 +* through indirect access registers.
2215 +* @param[in]   val     value to write
2216 +* @param[in]   addr    Address to write to (must be aligned on size)
2217 +* @param[in]   size    Number of bytes to write (1, 2 or 4)
2218 +*
2219 +*/
2220 +void class_bus_write(u32 val, u32 addr, u8 size)
2221 +{
2222 +       u32 offset = addr & 0x3;
2223 +
2224 +       writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
2225 +
2226 +       addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | PE_MEM_ACCESS_WRITE | (size << 24);
2227 +
2228 +       writel(cpu_to_be32(val << (offset << 3)), CLASS_BUS_ACCESS_WDATA);
2229 +       writel(addr, CLASS_BUS_ACCESS_ADDR);
2230 +}
2231 +
2232 +
2233 +/** Reads from CLASS internal bus peripherals (ccu, pe-lem) from the host
2234 +* through indirect access registers.
2235 +* @param[in] addr      Address to read from (must be aligned on size)
2236 +* @param[in] size      Number of bytes to read (1, 2 or 4)
2237 +* @return              the read data
2238 +*
2239 +*/
2240 +u32 class_bus_read(u32 addr, u8 size)
2241 +{
2242 +       u32 offset = addr & 0x3;
2243 +       u32 mask = 0xffffffff >> ((4 - size) << 3);
2244 +       u32 val;
2245 +
2246 +       writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
2247 +
2248 +       addr = (addr & ~CLASS_BUS_ACCESS_BASE_MASK) | (size << 24);
2249 +
2250 +       writel(addr, CLASS_BUS_ACCESS_ADDR);
2251 +       val = be32_to_cpu(readl(CLASS_BUS_ACCESS_RDATA));
2252 +
2253 +       return (val >> (offset << 3)) & mask;
2254 +}
2255 +
2256 +/** Writes data to the cluster memory (PE_LMEM)
2257 +* @param[in] dst       PE LMEM destination address (must be 32bit aligned)
2258 +* @param[in] src       Buffer source address
2259 +* @param[in] len       Number of bytes to copy
2260 +*/
2261 +void class_pe_lmem_memcpy_to32(u32 dst, const void *src, unsigned int len)
2262 +{
2263 +       u32 len32 = len >> 2;
2264 +       int i;
2265 +
2266 +       for (i = 0; i < len32; i++, src += 4, dst += 4)
2267 +               class_bus_write(*(u32 *)src, dst, 4);
2268 +
2269 +       if (len & 0x2)
2270 +       {
2271 +               class_bus_write(*(u16 *)src, dst, 2);
2272 +               src += 2;
2273 +               dst += 2;
2274 +       }
2275 +
2276 +       if (len & 0x1)
2277 +       {
2278 +               class_bus_write(*(u8 *)src, dst, 1);
2279 +               src++;
2280 +               dst++;
2281 +       }
2282 +}
2283 +
2284 +/** Writes value to the cluster memory (PE_LMEM)
2285 +* @param[in] dst       PE LMEM destination address (must be 32bit aligned)
2286 +* @param[in] val       Value to write
2287 +* @param[in] len       Number of bytes to write
2288 +*/
2289 +void class_pe_lmem_memset(u32 dst, int val, unsigned int len)
2290 +{
2291 +       u32 len32 = len >> 2;
2292 +       int i;
2293 +
2294 +       val = val | (val << 8) | (val << 16) | (val << 24);
2295 +
2296 +       for (i = 0; i < len32; i++, dst += 4)
2297 +               class_bus_write(val, dst, 4);
2298 +
2299 +       if (len & 0x2)
2300 +       {
2301 +               class_bus_write(val, dst, 2);
2302 +               dst += 2;
2303 +       }
2304 +
2305 +       if (len & 0x1)
2306 +       {
2307 +               class_bus_write(val, dst, 1);
2308 +               dst++;
2309 +       }
2310 +}
2311 +
2312 +/** Reads data from the cluster memory (PE_LMEM)
2313 +* @param[out] dst              pointer to the source buffer data are copied to
2314 +* @param[in] len               length in bytes of the amount of data to read from cluster memory
2315 +* @param[in] offset    offset in bytes in the cluster memory where data are read from
2316 +*/
2317 +void pe_lmem_read(u32 *dst, u32 len, u32 offset)
2318 +{
2319 +       u32 len32 = len >> 2;
2320 +       int i = 0;
2321 +
2322 +       for (i = 0; i < len32; dst++, i++, offset += 4)
2323 +               *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, 4);
2324 +
2325 +       /* FIXME we may have an out of bounds access on dst */
2326 +       if (len & 0x03)
2327 +               *dst = class_bus_read(PE_LMEM_BASE_ADDR + offset, (len & 0x03));
2328 +}
2329 +
2330 +/** Writes data to the cluster memory (PE_LMEM)
2331 +* @param[in] src       pointer to the source buffer data are copied from
2332 +* @param[in] len       length in bytes of the amount of data to write to the cluster memory
2333 +* @param[in] offset    offset in bytes in the cluster memory where data are written to
2334 +*/
2335 +void pe_lmem_write(u32 *src, u32 len, u32 offset)
2336 +{
2337 +       u32 len32 = len >> 2;
2338 +       int i = 0;
2339 +
2340 +       for (i = 0; i < len32; src++, i++, offset += 4)
2341 +               class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, 4);
2342 +
2343 +       /* FIXME we may have an out of bounds access on src */
2344 +       if (len & 0x03)
2345 +               class_bus_write(*src, PE_LMEM_BASE_ADDR + offset, (len & 0x03));
2346 +}
2347 +
2348 +/** Writes UTIL program memory (DDR) from the host.
2349 + *
2350 + * @param[in] addr     Address to write (virtual, must be aligned on size)
2351 + * @param[in] val              Value to write (in PE endianess, i.e BE)
2352 + * @param[in] size             Number of bytes to write (2 or 4)
2353 + */
2354 +static void util_pmem_write(u32 val, void *addr, u8 size)
2355 +{
2356 +       void *addr64 = (void *)((unsigned long)addr & ~0x7);
2357 +       unsigned long off = 8 - ((unsigned long)addr & 0x7) - size;
2358 +
2359 +       //IMEM should  be loaded as a 64bit swapped value in a 64bit aligned location
2360 +       if (size == 4)
2361 +               writel(be32_to_cpu(val), addr64 + off);
2362 +       else
2363 +               writew(be16_to_cpu((u16)val), addr64 + off);
2364 +}
2365 +
2366 +
2367 +/** Writes a buffer to UTIL program memory (DDR) from the host.
2368 + *
2369 + * @param[in] dst      Address to write (virtual, must be at least 16bit aligned)
2370 + * @param[in] src      Buffer to write (in PE endianess, i.e BE, must have same alignment as dst)
2371 + * @param[in] len      Number of bytes to write (must be at least 16bit aligned)
2372 + */
2373 +static void util_pmem_memcpy(void *dst, const void *src, unsigned int len)
2374 +{
2375 +       unsigned int len32;
2376 +       int i;
2377 +
2378 +       if ((unsigned long)src & 0x2) {
2379 +               util_pmem_write(*(u16 *)src, dst, 2);
2380 +               src += 2;
2381 +               dst += 2;
2382 +               len -= 2;
2383 +       }
2384 +
2385 +       len32 = len >> 2;
2386 +
2387 +       for (i = 0; i < len32; i++, dst += 4, src += 4)
2388 +               util_pmem_write(*(u32 *)src, dst, 4);
2389 +
2390 +       if (len & 0x2)
2391 +               util_pmem_write(*(u16 *)src, dst, len & 0x2);
2392 +}
2393 +
2394 +
2395 +/** Loads an elf section into pmem
2396 + * Code needs to be at least 16bit aligned and only PROGBITS sections are supported
2397 + *
2398 + * @param[in] id       PE identification (CLASS0_ID, ..., TMU0_ID, ..., TMU3_ID)
2399 + * @param[in] data     pointer to the elf firmware
2400 + * @param[in] shdr     pointer to the elf section header
2401 + *
2402 + */
2403 +static int pe_load_pmem_section(int id, const void *data, Elf32_Shdr *shdr)
2404 +{
2405 +       u32 offset = be32_to_cpu(shdr->sh_offset);
2406 +       u32 addr = be32_to_cpu(shdr->sh_addr);
2407 +       u32 size = be32_to_cpu(shdr->sh_size);
2408 +       u32 type = be32_to_cpu(shdr->sh_type);
2409 +
2410 +#if !defined(CONFIG_UTIL_PE_DISABLED)
2411 +       if (id == UTIL_ID)
2412 +       {
2413 +               printf("%s: unsuported pmem section for UTIL\n", __func__);
2414 +               return -1;
2415 +       }
2416 +#endif
2417 +
2418 +       if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
2419 +       {
2420 +               printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
2421 +                       __func__, addr, (unsigned long) data + offset);
2422 +
2423 +               return -1;
2424 +       }
2425 +
2426 +       if (addr & 0x1)
2427 +       {
2428 +               printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
2429 +               return -1;
2430 +       }
2431 +
2432 +       if (size & 0x1)
2433 +       {
2434 +               printf("%s: load size(%x) is not 16bit aligned\n", __func__, size);
2435 +               return -1;
2436 +       }
2437 +
2438 +               dprintf("pmem pe%d @%x len %d\n",id, addr, size);
2439 +       switch (type)
2440 +        {
2441 +        case SHT_PROGBITS:
2442 +               pe_pmem_memcpy_to32(id, addr, data + offset, size);
2443 +               break;
2444 +
2445 +       default:
2446 +               printf("%s: unsuported section type(%x)\n", __func__, type);
2447 +               return -1;
2448 +               break;
2449 +       }
2450 +
2451 +       return 0;
2452 +}
2453 +
2454 +
2455 +/** Loads an elf section into dmem
2456 + * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
2457 + *
2458 + * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
2459 + * @param[in] data             pointer to the elf firmware
2460 + * @param[in] shdr             pointer to the elf section header
2461 + *
2462 + */
2463 +static int pe_load_dmem_section(int id, const void *data, Elf32_Shdr *shdr)
2464 +{
2465 +       u32 offset = be32_to_cpu(shdr->sh_offset);
2466 +       u32 addr = be32_to_cpu(shdr->sh_addr);
2467 +       u32 size = be32_to_cpu(shdr->sh_size);
2468 +       u32 type = be32_to_cpu(shdr->sh_type);
2469 +       u32 size32 = size >> 2;
2470 +       int i;
2471 +
2472 +       if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
2473 +       {
2474 +               printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
2475 +                       __func__, addr, (unsigned long)data + offset);
2476 +
2477 +               return -1;
2478 +       }
2479 +
2480 +       if (addr & 0x3)
2481 +       {
2482 +               printf("%s: load address(%x) is not 32bit aligned\n", __func__, addr);
2483 +               return -1;
2484 +       }
2485 +
2486 +       switch (type)
2487 +        {
2488 +        case SHT_PROGBITS:
2489 +               dprintf("dmem pe%d @%x len %d\n",id, addr, size);
2490 +               pe_dmem_memcpy_to32(id, addr, data + offset, size);
2491 +               break;
2492 +
2493 +       case SHT_NOBITS:
2494 +               dprintf("dmem zero pe%d @%x len %d\n",id, addr, size);
2495 +               for (i = 0; i < size32; i++, addr += 4)
2496 +                       pe_dmem_write(id, 0, addr, 4);
2497 +
2498 +               if (size & 0x3)
2499 +                       pe_dmem_write(id, 0, addr, size & 0x3);
2500 +
2501 +               break;
2502 +
2503 +       default:
2504 +               printf("%s: unsuported section type(%x)\n", __func__, type);
2505 +               return -1;
2506 +               break;
2507 +       }
2508 +
2509 +       return 0;
2510 +}
2511 +
2512 +
2513 +/** Loads an elf section into DDR
2514 + * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
2515 + *
2516 + * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
2517 + * @param[in] data             pointer to the elf firmware
2518 + * @param[in] shdr             pointer to the elf section header
2519 + *
2520 + */
2521 +static int pe_load_ddr_section(int id, const void *data, Elf32_Shdr *shdr)
2522 +{
2523 +       u32 offset = be32_to_cpu(shdr->sh_offset);
2524 +       u32 addr = be32_to_cpu(shdr->sh_addr);
2525 +       u32 size = be32_to_cpu(shdr->sh_size);
2526 +       u32 type = be32_to_cpu(shdr->sh_type);
2527 +       u32 flags = be32_to_cpu(shdr->sh_flags);
2528 +
2529 +       switch (type)
2530 +       {
2531 +       case SHT_PROGBITS:
2532 +               dprintf("ddr  pe%d @%x len %d\n",id, addr, size);
2533 +               if (flags & SHF_EXECINSTR)
2534 +               {
2535 +                       if (id <= CLASS_MAX_ID)
2536 +                       {
2537 +                               /* DO the loading only once in DDR */
2538 +                               if (id == CLASS0_ID)
2539 +                               {
2540 +                                       dprintf("%s: load address(%x) and elf file address(%lx) rcvd\n", __func__, addr, (unsigned long)data + offset);
2541 +                                       if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
2542 +                                       {
2543 +                                               printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
2544 +                                                               __func__, addr, (unsigned long)data + offset);
2545 +
2546 +                                               return -1;
2547 +                                       }
2548 +
2549 +                                       if (addr & 0x1)
2550 +                                       {
2551 +                                               printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
2552 +                                               return -1;
2553 +                                       }
2554 +
2555 +                                       if (size & 0x1)
2556 +                                       {
2557 +                                               printf("%s: load length(%x) is not 16bit aligned\n", __func__, size);
2558 +                                               return -1;
2559 +                                       }
2560 +
2561 +                                       memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
2562 +                               }
2563 +                       }
2564 +
2565 +#if !defined(CONFIG_UTIL_PE_DISABLED)
2566 +                       else if (id == UTIL_ID)
2567 +                       {
2568 +                               if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
2569 +                               {
2570 +                                       printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
2571 +                                                               __func__, addr, (unsigned long)data + offset);
2572 +
2573 +                                       return -1;
2574 +                               }
2575 +
2576 +                               if (addr & 0x1)
2577 +                               {
2578 +                                       printf("%s: load address(%x) is not 16bit aligned\n", __func__, addr);
2579 +                                       return -1;
2580 +                               }
2581 +
2582 +                               if (size & 0x1)
2583 +                               {
2584 +                                       printf("%s: load length(%x) is not 16bit aligned\n", __func__, size);
2585 +                                       return -1;
2586 +                               }
2587 +
2588 +                               util_pmem_memcpy((void *)DDR_PFE_TO_VIRT(addr), data + offset, size);
2589 +                       }
2590 +#endif
2591 +                       else
2592 +                       {
2593 +                               printf("%s: unsuported ddr section type(%x) for PE(%d)\n", __func__, type, id);
2594 +                               return -1;
2595 +                       }
2596 +
2597 +               }
2598 +               else
2599 +               {
2600 +                       memcpy(DDR_PFE_TO_VIRT(addr), data + offset, size);
2601 +               }
2602 +
2603 +               break;
2604 +
2605 +       case SHT_NOBITS:
2606 +               dprintf("ddr zero pe%d @%x len %d\n",id, addr, size);
2607 +               memset((void *)DDR_PFE_TO_VIRT(addr), 0, size);
2608 +
2609 +               break;
2610 +
2611 +       default:
2612 +               printf("%s: unsuported section type(%x)\n", __func__, type);
2613 +               return -1;
2614 +               break;
2615 +       }
2616 +
2617 +       return 0;
2618 +}
2619 +
2620 +/** Loads an elf section into pe lmem
2621 + * Data needs to be at least 32bit aligned, NOBITS sections are correctly initialized to 0
2622 + *
2623 + * @param[in] id               PE identification (CLASS0_ID,..., CLASS5_ID)
2624 + * @param[in] data             pointer to the elf firmware
2625 + * @param[in] shdr             pointer to the elf section header
2626 + *
2627 + */
2628 +static int pe_load_pe_lmem_section(int id, const void *data, Elf32_Shdr *shdr)
2629 +{
2630 +       u32 offset = be32_to_cpu(shdr->sh_offset);
2631 +       u32 addr = be32_to_cpu(shdr->sh_addr);
2632 +       u32 size = be32_to_cpu(shdr->sh_size);
2633 +       u32 type = be32_to_cpu(shdr->sh_type);
2634 +
2635 +       if (id > CLASS_MAX_ID)
2636 +       {
2637 +               printf("%s: unsuported pe-lmem section type(%x) for PE(%d)\n", __func__, type, id);
2638 +               return -1;
2639 +       }
2640 +
2641 +       if (((unsigned long)(data + offset) & 0x3) != (addr & 0x3))
2642 +       {
2643 +               printf("%s: load address(%x) and elf file address(%lx) don't have the same alignment\n",
2644 +                       __func__, addr, (unsigned long)data + offset);
2645 +
2646 +               return -1;
2647 +       }
2648 +
2649 +       if (addr & 0x3)
2650 +       {
2651 +               printf("%s: load address(%x) is not 32bit aligned\n", __func__, addr);
2652 +               return -1;
2653 +       }
2654 +       dprintf("lmem  pe%d @%x len %d\n",id, addr, size);
2655 +       switch (type)
2656 +       {
2657 +       case SHT_PROGBITS:
2658 +               class_pe_lmem_memcpy_to32(addr, data + offset, size);
2659 +               break;
2660 +
2661 +       case SHT_NOBITS:
2662 +               class_pe_lmem_memset(addr, 0, size);
2663 +               break;
2664 +
2665 +       default:
2666 +               printf("%s: unsuported section type(%x)\n", __func__, type);
2667 +               return -1;
2668 +               break;
2669 +       }
2670 +
2671 +       return 0;
2672 +}
2673 +
2674 +
2675 +/** Loads an elf section into a PE
2676 + * For now only supports loading a section to dmem (all PE's), pmem (class and tmu PE's),
2677 + * DDDR (util PE code)
2678 + *
2679 + * @param[in] id               PE identification (CLASS0_ID, ..., TMU0_ID, ..., UTIL_ID)
2680 + * @param[in] data             pointer to the elf firmware
2681 + * @param[in] shdr             pointer to the elf section header
2682 + *
2683 + */
2684 +int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr)
2685 +{
2686 +       u32 addr = be32_to_cpu(shdr->sh_addr);
2687 +       u32 size = be32_to_cpu(shdr->sh_size);
2688 +
2689 +       //printf(".");
2690 +       if (IS_DMEM(addr, size))
2691 +               return pe_load_dmem_section(id, data, shdr);
2692 +       else if (IS_PMEM(addr, size))
2693 +               return pe_load_pmem_section(id, data, shdr);
2694 +       else if (IS_PFE_LMEM(addr, size))
2695 +               return 0; /* FIXME */
2696 +       else if (IS_PHYS_DDR(addr, size))
2697 +               return pe_load_ddr_section(id, data, shdr);
2698 +       else if (IS_PE_LMEM(addr, size))
2699 +               return pe_load_pe_lmem_section(id, data, shdr);
2700 +       else {
2701 +               printf("%s: unsuported memory range(%x)\n", __func__, addr);
2702 +               /*FIXME this should be remove after testing UTIL from 0x20000 */
2703 +               //printf("loading DDR section \n");
2704 +               //return pe_load_ddr_section(id, data, shdr);
2705 +//             return -1;
2706 +       }
2707 +
2708 +       return 0;
2709 +}
2710 +
2711 +/** This function is used to write to UTIL internal bus peripherals from the host
2712 +* through indirect access registers.
2713 +* @param[in]   val     32bits value to write
2714 +* @param[in]   addr    Address to write to
2715 +* @param[in]   size    Number of bytes to write
2716 +*
2717 +*/
2718 +void util_bus_write(u32 val, u32 addr, u8 size)
2719 +{
2720 +       u32 offset = addr & 0x3;
2721 +       u32 access_addr;
2722 +
2723 +       access_addr = ((addr & ~0x3) & CLASS_BUS_ACCESS_ADDR_MASK) | PE_MEM_ACCESS_WRITE | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
2724 +
2725 +//     writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
2726 +
2727 +       writel(cpu_to_be32(val << (offset << 3)), UTIL_BUS_ACCESS_WDATA);
2728 +       writel(access_addr, UTIL_BUS_ACCESS_ADDR);
2729 +}
2730 +
2731 +
2732 +/** Reads from UTIL internal bus peripherals from the host
2733 +* through indirect access registers.
2734 +* @param[in] addr      Address to read from
2735 +* @param[in] size      Number of bytes to read
2736 +* @return              the read data
2737 +*
2738 +*/
2739 +u32 util_bus_read(u32 addr, u8 size)
2740 +{
2741 +       u32 offset = addr & 0x3;
2742 +       u32 mask = 0xffffffff >> ((4 - size) << 3);
2743 +       u32 access_addr, val;
2744 +
2745 +       access_addr = ((addr & ~0x3) & CLASS_BUS_ACCESS_ADDR_MASK) | PE_MEM_ACCESS_READ | PE_MEM_ACCESS_BYTE_ENABLE(offset, size);
2746 +
2747 +//     writel((addr & CLASS_BUS_ACCESS_BASE_MASK), CLASS_BUS_ACCESS_BASE);
2748 +
2749 +       writel(access_addr, UTIL_BUS_ACCESS_ADDR);
2750 +       val = be32_to_cpu(readl(UTIL_BUS_ACCESS_RDATA));
2751 +
2752 +       return (val >> (offset << 3)) & mask;
2753 +}
2754 +
2755 +
2756 +
2757 +/**************************** BMU ***************************/
2758 +
2759 +/** Initializes a BMU block.
2760 +* @param[in] base      BMU block base address
2761 +* @param[in] cfg       BMU configuration
2762 +*/
2763 +void bmu_init(void *base, BMU_CFG *cfg)
2764 +{
2765 +
2766 +       bmu_disable(base);
2767 +
2768 +       bmu_set_config(base, cfg);
2769 +
2770 +       bmu_reset(base);
2771 +}
2772 +
2773 +/** Resets a BMU block.
2774 +* @param[in] base      BMU block base address
2775 +*/
2776 +void bmu_reset(void *base)
2777 +{
2778 +       writel(CORE_SW_RESET, base + BMU_CTRL);
2779 +
2780 +       /* Wait for self clear */
2781 +       while (readl(base + BMU_CTRL) & CORE_SW_RESET) ;
2782 +}
2783 +
2784 +/** Enabled a BMU block.
2785 +* @param[in] base      BMU block base address
2786 +*/
2787 +void bmu_enable(void *base)
2788 +{
2789 +       writel (CORE_ENABLE, base + BMU_CTRL);
2790 +}
2791 +
2792 +/** Disables a BMU block.
2793 +* @param[in] base      BMU block base address
2794 +*/
2795 +void bmu_disable(void *base)
2796 +{
2797 +       writel (CORE_DISABLE, base + BMU_CTRL);
2798 +}
2799 +
2800 +/** Sets the configuration of a BMU block.
2801 +* @param[in] base      BMU block base address
2802 +* @param[in] cfg       BMU configuration
2803 +*/
2804 +void bmu_set_config(void *base, BMU_CFG *cfg)
2805 +{
2806 +       writel (cfg->baseaddr, base + BMU_UCAST_BASE_ADDR);
2807 +       writel (cfg->count & 0xffff, base + BMU_UCAST_CONFIG);
2808 +       writel (cfg->size & 0xffff, base + BMU_BUF_SIZE);
2809 +//     writel (BMU1_THRES_CNT, base + BMU_THRES);
2810 +
2811 +       /* Interrupts are never used */
2812 +//     writel (0x0, base + BMU_INT_SRC);
2813 +       writel (0x0, base + BMU_INT_ENABLE);
2814 +}
2815 +
2816 +
2817 +#if 0 //These are LS1012A functions
2818 +/**************************** GEMAC ***************************/
2819 +
2820 +/** GEMAC block initialization.
2821 +* @param[in] base      GEMAC base address (GEMAC0, GEMAC1, GEMAC2)
2822 +* @param[in] cfg       GEMAC configuration
2823 +*/
2824 +void gemac_init(void *base, void *cfg)
2825 +{
2826 +       gemac_set_config(base, cfg);
2827 +       gemac_set_bus_width(base, 64);
2828 +}
2829 +
2830 +/** GEMAC set speed.
2831 +* @param[in] base      GEMAC base address
2832 +* @param[in] speed     GEMAC speed (10, 100 or 1000 Mbps)
2833 +*/
2834 +void gemac_set_speed(void *base, MAC_SPEED gem_speed)
2835 +{
2836 +       u32 val = readl(base + EMAC_NETWORK_CONFIG);
2837 +
2838 +       val = val & ~EMAC_SPEED_MASK;
2839 +
2840 +       switch (gem_speed)
2841 +       {
2842 +               case SPEED_10M:
2843 +                       val &= (~EMAC_PCS_ENABLE);
2844 +                       break;
2845 +
2846 +               case SPEED_100M:
2847 +                       val = val | EMAC_SPEED_100;
2848 +                       val &= (~EMAC_PCS_ENABLE);
2849 +                       break;
2850 +
2851 +               case SPEED_1000M:
2852 +                       val = val | EMAC_SPEED_1000;
2853 +                       val &= (~EMAC_PCS_ENABLE);
2854 +                       break;
2855 +
2856 +               case SPEED_1000M_PCS:
2857 +                       val = val | EMAC_SPEED_1000;
2858 +                       val |= EMAC_PCS_ENABLE;
2859 +                       break;
2860 +
2861 +               default:
2862 +                       val = val | EMAC_SPEED_100;
2863 +                       val &= (~EMAC_PCS_ENABLE);
2864 +               break;
2865 +       }
2866 +
2867 +       writel (val, base + EMAC_NETWORK_CONFIG);
2868 +}
2869 +
2870 +/** GEMAC set duplex.
2871 +* @param[in] base      GEMAC base address
2872 +* @param[in] duplex    GEMAC duplex mode (Full, Half)
2873 +*/
2874 +void gemac_set_duplex(void *base, int duplex)
2875 +{
2876 +       u32 val = readl(base + EMAC_NETWORK_CONFIG);
2877 +
2878 +       if (duplex == DUPLEX_HALF)
2879 +               val = (val & ~EMAC_DUPLEX_MASK) | EMAC_HALF_DUP;
2880 +       else
2881 +               val = (val & ~EMAC_DUPLEX_MASK) | EMAC_FULL_DUP;
2882 +
2883 +       writel (val, base + EMAC_NETWORK_CONFIG);
2884 +}
2885 +
2886 +/** GEMAC set mode.
2887 +* @param[in] base      GEMAC base address
2888 +* @param[in] mode      GEMAC operation mode (MII, RMII, RGMII, SGMII)
2889 +*/
2890 +void gemac_set_mode(void *base, int mode)
2891 +{
2892 +       switch (mode)
2893 +       {
2894 +       case GMII:
2895 +               writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_GMII_MODE_ENABLE, base + EMAC_CONTROL);
2896 +               writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
2897 +               break;
2898 +
2899 +       case RGMII:
2900 +               writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RGMII_MODE_ENABLE, base + EMAC_CONTROL);
2901 +               writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
2902 +               break;
2903 +
2904 +       case RMII:
2905 +               writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_RMII_MODE_ENABLE, base + EMAC_CONTROL);
2906 +               writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
2907 +               break;
2908 +
2909 +       case MII:
2910 +               writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE, base + EMAC_CONTROL);
2911 +               writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
2912 +               break;
2913 +
2914 +       case SGMII:
2915 +               writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | (EMAC_RMII_MODE_DISABLE | EMAC_RGMII_MODE_DISABLE), base + EMAC_CONTROL);
2916 +               writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_SGMII_MODE_ENABLE, base + EMAC_NETWORK_CONFIG);
2917 +               break;
2918 +
2919 +       default:
2920 +               writel ((readl(base + EMAC_CONTROL) & ~EMAC_MODE_MASK) | EMAC_MII_MODE_ENABLE, base + EMAC_CONTROL);
2921 +               writel (readl(base + EMAC_NETWORK_CONFIG) & (~EMAC_SGMII_MODE_ENABLE), base + EMAC_NETWORK_CONFIG);
2922 +               break;
2923 +       }
2924 +}
2925 +
2926 +/** GEMAC Enable MDIO: Activate the Management interface.  This is required to program the PHY
2927 + * @param[in] base       GEMAC base address
2928 + */
2929 +void gemac_enable_mdio(void *base)
2930 +{
2931 +        u32 data;
2932 +
2933 +        data = readl(base + EMAC_NETWORK_CONTROL);
2934 +        data |= EMAC_MDIO_EN;
2935 +        writel(data, base + EMAC_NETWORK_CONTROL);
2936 +}
2937 +
2938 +/** GEMAC Disable MDIO: Disable the Management interface.
2939 + * @param[in] base       GEMAC base address
2940 + */
2941 +void gemac_disable_mdio(void *base)
2942 +{
2943 +        u32 data;
2944 +
2945 +        data = readl(base + EMAC_NETWORK_CONTROL);
2946 +        data &= ~EMAC_MDIO_EN;
2947 +        writel(data, base + EMAC_NETWORK_CONTROL);
2948 +}
2949 +
2950 +/** GEMAC Set MDC clock division
2951 + * @param[in] base       GEMAC base address
2952 + * @param[in] base       MDC divider value
2953 + */
2954 +void gemac_set_mdc_div(void *base, MAC_MDC_DIV gem_mdcdiv)
2955 +{
2956 +        u32 data;
2957 +
2958 +        data = readl(base + EMAC_NETWORK_CONFIG);
2959 +       data &= ~(MDC_DIV_MASK << MDC_DIV_SHIFT);
2960 +        data |= (gem_mdcdiv & MDC_DIV_MASK) << MDC_DIV_SHIFT;
2961 +        writel(data, base + EMAC_NETWORK_CONFIG);
2962 +}
2963 +
2964 +/** GEMAC reset function.
2965 +* @param[in] base      GEMAC base address
2966 +*/
2967 +void gemac_reset(void *base)
2968 +{
2969 +}
2970 +
2971 +/** GEMAC enable function.
2972 +* @param[in] base      GEMAC base address
2973 +*/
2974 +void gemac_enable(void *base)
2975 +{
2976 +       writel (readl(base + EMAC_NETWORK_CONTROL) | EMAC_TX_ENABLE | EMAC_RX_ENABLE, base + EMAC_NETWORK_CONTROL);
2977 +}
2978 +
2979 +/** GEMAC disable function.
2980 +* @param[in] base      GEMAC base address
2981 +*/
2982 +void gemac_disable(void *base)
2983 +{
2984 +       writel (readl(base + EMAC_NETWORK_CONTROL) & ~(EMAC_TX_ENABLE | EMAC_RX_ENABLE), base + EMAC_NETWORK_CONTROL);
2985 +}
2986 +
2987 +/** GEMAC set mac address configuration.
2988 +* @param[in] base      GEMAC base address
2989 +* @param[in] addr      MAC address to be configured
2990 +*/
2991 +void gemac_set_address(void *base, SPEC_ADDR *addr)
2992 +{
2993 +       writel(addr->one.bottom,        base + EMAC_SPEC1_ADD_BOT);
2994 +       writel(addr->one.top,           base + EMAC_SPEC1_ADD_TOP);
2995 +       writel(addr->two.bottom,        base + EMAC_SPEC2_ADD_BOT);
2996 +       writel(addr->two.top,           base + EMAC_SPEC2_ADD_TOP);
2997 +       writel(addr->three.bottom,      base + EMAC_SPEC3_ADD_BOT);
2998 +       writel(addr->three.top,         base + EMAC_SPEC3_ADD_TOP);
2999 +       writel(addr->four.bottom,       base + EMAC_SPEC4_ADD_BOT);
3000 +       writel(addr->four.top,          base + EMAC_SPEC4_ADD_TOP);
3001 +}
3002 +
3003 +/** GEMAC get mac address configuration.
3004 +* @param[in] base      GEMAC base address
3005 +*
3006 +* @return              MAC addresses configured
3007 +*/
3008 +SPEC_ADDR gemac_get_address(void *base)
3009 +{
3010 +       SPEC_ADDR addr;
3011 +
3012 +       addr.one.bottom =       readl(base + EMAC_SPEC1_ADD_BOT);
3013 +       addr.one.top =          readl(base + EMAC_SPEC1_ADD_TOP);
3014 +       addr.two.bottom =       readl(base + EMAC_SPEC2_ADD_BOT);
3015 +       addr.two.top =          readl(base + EMAC_SPEC2_ADD_TOP);
3016 +       addr.three.bottom =     readl(base + EMAC_SPEC3_ADD_BOT);
3017 +       addr.three.top =        readl(base + EMAC_SPEC3_ADD_TOP);
3018 +       addr.four.bottom =      readl(base + EMAC_SPEC4_ADD_BOT);
3019 +       addr.four.top =         readl(base + EMAC_SPEC4_ADD_TOP);
3020 +
3021 +       return addr;
3022 +}
3023 +
3024 +/** GEMAC set specific local addresses of the MAC.
3025 +* Rather than setting up all four specific addresses, this function sets them up individually.
3026 +*
3027 +* @param[in] base      GEMAC base address
3028 +* @param[in] addr      MAC address to be configured
3029 +*/
3030 +void gemac_set_laddr1(void *base, MAC_ADDR *address)
3031 +{
3032 +       writel(address->bottom,         base + EMAC_SPEC1_ADD_BOT);
3033 +       writel(address->top,            base + EMAC_SPEC1_ADD_TOP);
3034 +}
3035 +
3036 +
3037 +void gemac_set_laddr2(void *base, MAC_ADDR *address)
3038 +{
3039 +       writel(address->bottom,         base + EMAC_SPEC2_ADD_BOT);
3040 +       writel(address->top,            base + EMAC_SPEC2_ADD_TOP);
3041 +}
3042 +
3043 +
3044 +void gemac_set_laddr3(void *base, MAC_ADDR *address)
3045 +{
3046 +       writel(address->bottom,         base + EMAC_SPEC3_ADD_BOT);
3047 +       writel(address->top,            base + EMAC_SPEC3_ADD_TOP);
3048 +}
3049 +
3050 +
3051 +void gemac_set_laddr4(void *base, MAC_ADDR *address)
3052 +{
3053 +       writel(address->bottom,         base + EMAC_SPEC4_ADD_BOT);
3054 +       writel(address->top,            base + EMAC_SPEC4_ADD_TOP);
3055 +}
3056 +
3057 +void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index)
3058 +{
3059 +       if (entry_index < 5)
3060 +       {
3061 +               writel(address->bottom,         base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
3062 +               writel(address->top,            base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP);
3063 +       }
3064 +       else
3065 +       {
3066 +               writel(address->bottom,         base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_BOT);
3067 +               writel(address->top,            base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_TOP);
3068 +       }
3069 +}
3070 +
3071 +/** Get specific local addresses of the MAC.
3072 +* This allows returning of a single specific address stored in the MAC.
3073 +* @param[in] base      GEMAC base address
3074 +*
3075 +* @return              Specific MAC address 1
3076 +*
3077 +*/
3078 +MAC_ADDR gem_get_laddr1(void *base)
3079 +{
3080 +       MAC_ADDR addr;
3081 +       addr.bottom = readl(base + EMAC_SPEC1_ADD_BOT);
3082 +       addr.top = readl(base + EMAC_SPEC1_ADD_TOP);
3083 +       return addr;
3084 +}
3085 +
3086 +
3087 +MAC_ADDR gem_get_laddr2(void *base)
3088 +{
3089 +       MAC_ADDR addr;
3090 +       addr.bottom = readl(base + EMAC_SPEC2_ADD_BOT);
3091 +       addr.top = readl(base + EMAC_SPEC2_ADD_TOP);
3092 +       return addr;
3093 +}
3094 +
3095 +
3096 +MAC_ADDR gem_get_laddr3(void *base)
3097 +{
3098 +       MAC_ADDR addr;
3099 +       addr.bottom = readl(base + EMAC_SPEC3_ADD_BOT);
3100 +       addr.top = readl(base + EMAC_SPEC3_ADD_TOP);
3101 +       return addr;
3102 +}
3103 +
3104 +
3105 +MAC_ADDR gem_get_laddr4(void *base)
3106 +{
3107 +       MAC_ADDR addr;
3108 +       addr.bottom = readl(base + EMAC_SPEC4_ADD_BOT);
3109 +       addr.top = readl(base + EMAC_SPEC4_ADD_TOP);
3110 +       return addr;
3111 +}
3112 +
3113 +
3114 +MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index)
3115 +{
3116 +       MAC_ADDR addr;
3117 +
3118 +       if (entry_index < 5)
3119 +       {
3120 +               addr.bottom = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_BOT);
3121 +               addr.top = readl(base + (entry_index * 8) + EMAC_SPEC1_ADD_TOP);
3122 +       }
3123 +       else
3124 +       {
3125 +               addr.bottom = readl(base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_BOT);
3126 +               addr.top = readl(base + ((entry_index - 5) * 8) + EMAC_SPEC5_ADD_TOP);
3127 +       }
3128 +
3129 +       return addr;
3130 +}
3131 +
3132 +/** GEMAC allow frames
3133 +* @param[in] base      GEMAC base address
3134 +*/
3135 +void gemac_enable_copy_all(void *base)
3136 +{
3137 +       writel (readl(base + EMAC_NETWORK_CONFIG) & EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG);
3138 +}
3139 +
3140 +/** GEMAC do not allow frames
3141 +* @param[in] base      GEMAC base address
3142 +*/
3143 +void gemac_disable_copy_all(void *base)
3144 +{
3145 +       writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_COPY_ALL, base + EMAC_NETWORK_CONFIG);
3146 +}
3147 +
3148 +
3149 +
3150 +/** GEMAC allow broadcast function.
3151 +* @param[in] base      GEMAC base address
3152 +*/
3153 +void gemac_allow_broadcast(void *base)
3154 +{
3155 +       writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG);
3156 +}
3157 +
3158 +/** GEMAC no broadcast function.
3159 +* @param[in] base      GEMAC base address
3160 +*/
3161 +void gemac_no_broadcast(void *base)
3162 +{
3163 +       writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_NO_BROADCAST, base + EMAC_NETWORK_CONFIG);
3164 +}
3165 +
3166 +/** GEMAC enable unicast function.
3167 +* @param[in] base      GEMAC base address
3168 +*/
3169 +void gemac_enable_unicast(void *base)
3170 +{
3171 +       writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG);
3172 +}
3173 +
3174 +/** GEMAC disable unicast function.
3175 +* @param[in] base      GEMAC base address
3176 +*/
3177 +void gemac_disable_unicast(void *base)
3178 +{
3179 +       writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_UNICAST, base + EMAC_NETWORK_CONFIG);
3180 +}
3181 +
3182 +/** GEMAC enable multicast function.
3183 +* @param[in] base      GEMAC base address
3184 +*/
3185 +void gemac_enable_multicast(void *base)
3186 +{
3187 +       writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG);
3188 +}
3189 +
3190 +/** GEMAC disable multicast function.
3191 +* @param[in]   base    GEMAC base address
3192 +*/
3193 +void gemac_disable_multicast(void *base)
3194 +{
3195 +       writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_MULTICAST, base + EMAC_NETWORK_CONFIG);
3196 +}
3197 +
3198 +/** GEMAC enable fcs rx function.
3199 +* @param[in]   base    GEMAC base address
3200 +*/
3201 +void gemac_enable_fcs_rx(void *base)
3202 +{
3203 +       writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG);
3204 +}
3205 +
3206 +/** GEMAC disable fcs rx function.
3207 +* @param[in]   base    GEMAC base address
3208 +*/
3209 +void gemac_disable_fcs_rx(void *base)
3210 +{
3211 +       writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_FCS_RX, base + EMAC_NETWORK_CONFIG);
3212 +}
3213 +
3214 +/** GEMAC enable 1536 rx function.
3215 +* @param[in]   base    GEMAC base address
3216 +*/
3217 +void gemac_enable_1536_rx(void *base)
3218 +{
3219 +       writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG);
3220 +}
3221 +
3222 +/** GEMAC disable 1536 rx function.
3223 +* @param[in]   base    GEMAC base address
3224 +*/
3225 +void gemac_disable_1536_rx(void *base)
3226 +{
3227 +       writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_1536_RX, base + EMAC_NETWORK_CONFIG);
3228 +}
3229 +
3230 +/** GEMAC enable pause rx function.
3231 +* @param[in] base      GEMAC base address
3232 +*/
3233 +void gemac_enable_pause_rx(void *base)
3234 +{
3235 +       writel (readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG);
3236 +}
3237 +
3238 +/** GEMAC disable pause rx function.
3239 +* @param[in] base      GEMAC base address
3240 +*/
3241 +void gemac_disable_pause_rx(void *base)
3242 +{
3243 +       writel (readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_PAUSE_RX, base + EMAC_NETWORK_CONFIG);
3244 +}
3245 +
3246 +/** GEMAC enable rx checksum offload function.
3247 +* @param[in] base      GEMAC base address
3248 +*/
3249 +void gemac_enable_rx_checksum_offload(void *base)
3250 +{
3251 +       writel(readl(base + EMAC_NETWORK_CONFIG) | EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG);
3252 +       writel(readl(CLASS_L4_CHKSUM_ADDR) | IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR);
3253 +}
3254 +
3255 +/** GEMAC disable rx checksum offload function.
3256 +* @param[in] base      GEMAC base address
3257 +*/
3258 +void gemac_disable_rx_checksum_offload(void *base)
3259 +{
3260 +       writel(readl(base + EMAC_NETWORK_CONFIG) & ~EMAC_ENABLE_CHKSUM_RX, base + EMAC_NETWORK_CONFIG);
3261 +       writel(readl(CLASS_L4_CHKSUM_ADDR) & ~IPV4_CHKSUM_DROP, CLASS_L4_CHKSUM_ADDR);
3262 +}
3263 +
3264 +/** Sets Gemac bus width to 64bit
3265 + * @param[in] base       GEMAC base address
3266 + * @param[in] width    gemac bus width to be set possible values are 32/64/128
3267 + * */
3268 +void gemac_set_bus_width(void *base, int width)
3269 +{
3270 +       u32 val = readl(base + EMAC_NETWORK_CONFIG);
3271 +       switch(width)
3272 +       {
3273 +       case 32:
3274 +               val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_32;
3275 +       case 128:
3276 +               val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_128;
3277 +       case 64:
3278 +       default:
3279 +               val = (val & ~EMAC_DATA_BUS_WIDTH_MASK) | EMAC_DATA_BUS_WIDTH_64;
3280 +
3281 +       }
3282 +       writel (val, base + EMAC_NETWORK_CONFIG);
3283 +}
3284 +
3285 +/** Sets Gemac configuration.
3286 +* @param[in] base      GEMAC base address
3287 +* @param[in] cfg       GEMAC configuration
3288 +*/
3289 +void gemac_set_config(void *base, GEMAC_CFG *cfg)
3290 +{
3291 +       gemac_set_mode(base, cfg->mode);
3292 +
3293 +       gemac_set_speed(base, cfg->speed);
3294 +
3295 +       gemac_set_duplex(base,cfg->duplex);
3296 +}
3297 +#endif
3298 +
3299 +/**************************** GPI ***************************/
3300 +
3301 +/** Initializes a GPI block.
3302 +* @param[in] base      GPI base address
3303 +* @param[in] cfg       GPI configuration
3304 +*/
3305 +void gpi_init(void *base, GPI_CFG *cfg)
3306 +{
3307 +       gpi_reset(base);
3308 +
3309 +       gpi_disable(base);
3310 +
3311 +       gpi_set_config(base, cfg);
3312 +}
3313 +
3314 +/** Resets a GPI block.
3315 +* @param[in] base      GPI base address
3316 +*/
3317 +void gpi_reset(void *base)
3318 +{
3319 +       writel (CORE_SW_RESET, base + GPI_CTRL);
3320 +}
3321 +
3322 +/** Enables a GPI block.
3323 +* @param[in] base      GPI base address
3324 +*/
3325 +void gpi_enable(void *base)
3326 +{
3327 +       writel (CORE_ENABLE, base + GPI_CTRL);
3328 +}
3329 +
3330 +/** Disables a GPI block.
3331 +* @param[in] base      GPI base address
3332 +*/
3333 +void gpi_disable(void *base)
3334 +{
3335 +       writel (CORE_DISABLE, base + GPI_CTRL);
3336 +}
3337 +
3338 +
3339 +/** Sets the configuration of a GPI block.
3340 +* @param[in] base      GPI base address
3341 +* @param[in] cfg       GPI configuration
3342 +*/
3343 +void gpi_set_config(void *base, GPI_CFG *cfg)
3344 +{
3345 +       writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL),      base + GPI_LMEM_ALLOC_ADDR);
3346 +       writel (CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_FREE_CTRL),       base + GPI_LMEM_FREE_ADDR);
3347 +       writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_ALLOC_CTRL),      base + GPI_DDR_ALLOC_ADDR);
3348 +       writel (CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),       base + GPI_DDR_FREE_ADDR);
3349 +       writel (CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR),                     base + GPI_CLASS_ADDR);
3350 +       writel (DDR_HDR_SIZE,                                           base + GPI_DDR_DATA_OFFSET);
3351 +       writel (LMEM_HDR_SIZE,                                          base + GPI_LMEM_DATA_OFFSET);
3352 +       writel (0,                                                      base + GPI_LMEM_SEC_BUF_DATA_OFFSET);
3353 +       writel (0,                                                      base + GPI_DDR_SEC_BUF_DATA_OFFSET);
3354 +       writel ((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE,                   base + GPI_HDR_SIZE);
3355 +       writel ((DDR_BUF_SIZE << 16) | LMEM_BUF_SIZE,                   base + GPI_BUF_SIZE);
3356 +
3357 +       writel (((cfg->lmem_rtry_cnt << 16) | (GPI_DDR_BUF_EN << 1) | GPI_LMEM_BUF_EN), base + GPI_RX_CONFIG);
3358 +       writel (cfg->tmlf_txthres,                                      base + GPI_TMLF_TX);
3359 +       writel (cfg->aseq_len,                                          base + GPI_DTX_ASEQ);
3360 +}
3361 +
3362 +/**************************** CLASSIFIER ***************************/
3363 +
3364 +/** Initializes CLASSIFIER block.
3365 +* @param[in] cfg       CLASSIFIER configuration
3366 +*/
3367 +void class_init(CLASS_CFG *cfg)
3368 +{
3369 +       class_reset();
3370 +
3371 +       class_disable();
3372 +
3373 +       class_set_config(cfg);
3374 +}
3375 +
3376 +/** Resets CLASSIFIER block.
3377 +*
3378 +*/
3379 +void class_reset(void)
3380 +{
3381 +       writel(CORE_SW_RESET, CLASS_TX_CTRL);
3382 +}
3383 +
3384 +/** Enables all CLASS-PE's cores.
3385 +*
3386 +*/
3387 +void class_enable(void)
3388 +{
3389 +       writel(CORE_ENABLE, CLASS_TX_CTRL);
3390 +}
3391 +
3392 +/** Disables all CLASS-PE's cores.
3393 +*
3394 +*/
3395 +void class_disable(void)
3396 +{
3397 +       writel(CORE_DISABLE, CLASS_TX_CTRL);
3398 +}
3399 +
3400 +/** Sets the configuration of the CLASSIFIER block.
3401 +* @param[in] cfg       CLASSIFIER configuration
3402 +*/
3403 +void class_set_config(CLASS_CFG *cfg)
3404 +{
3405 +       if (PLL_CLK_EN == 0)
3406 +               writel(0x0,     CLASS_PE_SYS_CLK_RATIO);        // Clock ratio: for 1:1 the value is 0
3407 +       else
3408 +               writel(0x1,     CLASS_PE_SYS_CLK_RATIO);        // Clock ratio: for 1:2 the value is 1
3409 +
3410 +       writel((DDR_HDR_SIZE << 16) | LMEM_HDR_SIZE,    CLASS_HDR_SIZE);
3411 +       writel(LMEM_BUF_SIZE,                           CLASS_LMEM_BUF_SIZE);
3412 +       writel(CLASS_ROUTE_ENTRY_SIZE(CLASS_ROUTE_SIZE) | CLASS_ROUTE_HASH_SIZE(cfg->route_table_hash_bits),    CLASS_ROUTE_HASH_ENTRY_SIZE);
3413 +       writel(HASH_CRC_PORT_IP | QB2BUS_LE, CLASS_ROUTE_MULTI);
3414 +
3415 +       writel(cfg->route_table_baseaddr,               CLASS_ROUTE_TABLE_BASE);
3416 +       memset((void *)DDR_PFE_TO_VIRT(cfg->route_table_baseaddr), 0, ROUTE_TABLE_SIZE);
3417 +
3418 +       writel(CLASS_PE0_RO_DM_ADDR0_VAL,               CLASS_PE0_RO_DM_ADDR0);
3419 +       writel(CLASS_PE0_RO_DM_ADDR1_VAL,               CLASS_PE0_RO_DM_ADDR1);
3420 +       writel(CLASS_PE0_QB_DM_ADDR0_VAL,               CLASS_PE0_QB_DM_ADDR0);
3421 +       writel(CLASS_PE0_QB_DM_ADDR1_VAL,               CLASS_PE0_QB_DM_ADDR1);
3422 +       writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR),    CLASS_TM_INQ_ADDR);
3423 +
3424 +       writel(23, CLASS_AFULL_THRES);
3425 +       writel(23, CLASS_TSQ_FIFO_THRES);
3426 +
3427 +       writel(24, CLASS_MAX_BUF_CNT);
3428 +       writel(24, CLASS_TSQ_MAX_CNT);
3429 +       //writel(1, CLASS_USE_TMU_INQ);
3430 +}
3431 +
3432 +/**************************** TMU ***************************/
3433 +
3434 +void tmu_reset(void)
3435 +{
3436 +       writel(SW_RESET, TMU_CTRL);
3437 +}
3438 +
3439 +/** Initializes TMU block.
3440 +* @param[in] cfg       TMU configuration
3441 +*/
3442 +void tmu_init(TMU_CFG *cfg)
3443 +{
3444 +       int q, phyno;
3445 +
3446 +       /* keep in soft reset */
3447 +       writel(SW_RESET,                     TMU_CTRL);
3448 +
3449 +       /* enable EMAC PHY ports */
3450 +       writel(0x3,                                             TMU_SYS_GENERIC_CONTROL);
3451 +
3452 +       writel(750,                                             TMU_INQ_WATERMARK);
3453 +       writel(CBUS_VIRT_TO_PFE(EGPI1_BASE_ADDR + GPI_INQ_PKTPTR),      TMU_PHY0_INQ_ADDR);
3454 +       writel(CBUS_VIRT_TO_PFE(EGPI2_BASE_ADDR + GPI_INQ_PKTPTR),      TMU_PHY1_INQ_ADDR);
3455 +#if !defined(CONFIG_LS1012A)
3456 +       writel(CBUS_VIRT_TO_PFE(EGPI3_BASE_ADDR + GPI_INQ_PKTPTR),      TMU_PHY2_INQ_ADDR);
3457 +#endif
3458 +       writel(CBUS_VIRT_TO_PFE(HGPI_BASE_ADDR + GPI_INQ_PKTPTR),       TMU_PHY3_INQ_ADDR);
3459 +       writel(CBUS_VIRT_TO_PFE(HIF_NOCPY_RX_INQ0_PKTPTR),              TMU_PHY4_INQ_ADDR);
3460 +       writel(CBUS_VIRT_TO_PFE(UTIL_INQ_PKTPTR),                       TMU_PHY5_INQ_ADDR);
3461 +       writel(CBUS_VIRT_TO_PFE(BMU2_BASE_ADDR + BMU_FREE_CTRL),        TMU_BMU_INQ_ADDR);
3462 +
3463 +       writel(0x3FF,   TMU_TDQ0_SCH_CTRL);     // enabling all 10 schedulers [9:0] of each TDQ
3464 +       writel(0x3FF,   TMU_TDQ1_SCH_CTRL);
3465 +#if !defined(CONFIG_LS1012A)
3466 +       writel(0x3FF,   TMU_TDQ2_SCH_CTRL);
3467 +#endif
3468 +       writel(0x3FF,   TMU_TDQ3_SCH_CTRL);
3469 +
3470 +
3471 +       if (PLL_CLK_EN == 0)
3472 +               writel(0x0,     TMU_PE_SYS_CLK_RATIO);  // Clock ratio: for 1:1 the value is 0
3473 +       else
3474 +               writel(0x1,     TMU_PE_SYS_CLK_RATIO);  // Clock ratio: for 1:2 the value is 1
3475 +
3476 +       //printf("TMU_LLM_BASE_ADDR %x\n", cfg->llm_base_addr);
3477 +       writel(cfg->llm_base_addr,      TMU_LLM_BASE_ADDR);     // Extra packet pointers will be stored from this address onwards
3478 +
3479 +       //printf("TMU_LLM_QUE_LEN %x\n", cfg->llm_queue_len);
3480 +       writel(cfg->llm_queue_len,      TMU_LLM_QUE_LEN);
3481 +       writel(5,                       TMU_TDQ_IIFG_CFG);
3482 +       writel(DDR_BUF_SIZE,            TMU_BMU_BUF_SIZE);
3483 +
3484 +       writel(0x0,                     TMU_CTRL);
3485 +
3486 +       /* MEM init */
3487 +       //printf("%s: mem init\n", __func__);
3488 +       writel(MEM_INIT,        TMU_CTRL);
3489 +
3490 +       while(!(readl(TMU_CTRL) & MEM_INIT_DONE))
3491 +       ;
3492 +
3493 +       /* LLM init */
3494 +       //printf("%s: lmem init\n", __func__);
3495 +       writel(LLM_INIT,        TMU_CTRL);
3496 +
3497 +       while(!(readl(TMU_CTRL) & LLM_INIT_DONE))
3498 +       ;
3499 +
3500 +       // set up each queue for tail drop
3501 +       for (phyno = 0; phyno < 4; phyno++)
3502 +       {
3503 +#if !defined(CONFIG_LS1012A)
3504 +               if(phyno = 2) continue;
3505 +#endif
3506 +               for (q = 0; q < 16; q++)
3507 +               {
3508 +                       u32 qmax;
3509 +                       writel((phyno << 8) | q, TMU_TEQ_CTRL);
3510 +                       writel(1 << 22, TMU_TEQ_QCFG);
3511 +                       qmax = ((phyno == 3) || (q < 8)) ? 255 : 127;
3512 +                       writel(qmax << 18, TMU_TEQ_HW_PROB_CFG2);
3513 +                       writel(qmax >> 14, TMU_TEQ_HW_PROB_CFG3);
3514 +               }
3515 +       }
3516 +       writel(0x05, TMU_TEQ_DISABLE_DROPCHK);
3517 +       writel(0,       TMU_CTRL);
3518 +}
3519 +
3520 +/** Enables TMU-PE cores.
3521 +* @param[in] pe_mask   TMU PE mask
3522 +*/
3523 +void tmu_enable(u32 pe_mask)
3524 +{
3525 +       writel(readl(TMU_TX_CTRL) | (pe_mask & 0xF), TMU_TX_CTRL);
3526 +}
3527 +
3528 +/** Disables TMU cores.
3529 +* @param[in] pe_mask   TMU PE mask
3530 +*/
3531 +void tmu_disable(u32 pe_mask)
3532 +{
3533 +       writel(readl(TMU_TX_CTRL) & ~(pe_mask & 0xF), TMU_TX_CTRL);
3534 +}
3535 +
3536 +/**************************** UTIL ***************************/
3537 +
3538 +/** Resets UTIL block.
3539 +*/
3540 +void util_reset(void)
3541 +{
3542 +       writel(CORE_SW_RESET, UTIL_TX_CTRL);
3543 +}
3544 +
3545 +/** Initializes UTIL block.
3546 +* @param[in] cfg       UTIL configuration
3547 +*/
3548 +void util_init(UTIL_CFG *cfg)
3549 +{
3550 +
3551 +       //writel(0x1, UTIL_MISC_REG);
3552 +
3553 +       if (PLL_CLK_EN == 0)
3554 +               writel(0x0,     UTIL_PE_SYS_CLK_RATIO);        // Clock ratio: for 1:1 the value is 0
3555 +       else
3556 +               writel(0x1,     UTIL_PE_SYS_CLK_RATIO);        // Clock ratio: for 1:2 the value is 1
3557 +}
3558 +
3559 +/** Enables UTIL-PE core.
3560 +*
3561 +*/
3562 +void util_enable(void)
3563 +{
3564 +       writel(CORE_ENABLE, UTIL_TX_CTRL);
3565 +}
3566 +
3567 +/** Disables UTIL-PE core.
3568 +*
3569 +*/
3570 +void util_disable(void)
3571 +{
3572 +       writel(CORE_DISABLE, UTIL_TX_CTRL);
3573 +}
3574 +
3575 +#if 0
3576 +/** GEMAC PHY Statistics - This function return address of the first statistics register
3577 +* @param[in]   base    GEMAC base address
3578 +*/
3579 +unsigned int * gemac_get_stats(void *base)
3580 +{
3581 +       return (unsigned int *)(base + EMAC_OCT_TX_BOT);
3582 +}
3583 +#endif
3584 +
3585 +/**************************** HIF ***************************/
3586 +
3587 +/** Initializes HIF no copy block.
3588 +*
3589 +*/
3590 +void hif_nocpy_init(void)
3591 +{
3592 +       writel(4,                                                       HIF_NOCPY_TX_PORT_NO);
3593 +       writel(CBUS_VIRT_TO_PFE(BMU1_BASE_ADDR + BMU_ALLOC_CTRL),               HIF_NOCPY_LMEM_ALLOC_ADDR);
3594 +       writel(CBUS_VIRT_TO_PFE(CLASS_INQ_PKTPTR),      HIF_NOCPY_CLASS_ADDR);
3595 +       writel(CBUS_VIRT_TO_PFE(TMU_PHY_INQ_PKTPTR),    HIF_NOCPY_TMU_PORT0_ADDR);
3596 +}
3597 +
3598 +/** Initializes HIF copy block.
3599 +*
3600 +*/
3601 +void hif_init(void)
3602 +{
3603 +       /*Initialize HIF registers*/
3604 +       writel(HIF_RX_POLL_CTRL_CYCLE<<16|HIF_TX_POLL_CTRL_CYCLE, HIF_POLL_CTRL);
3605 +}
3606 +
3607 +/** Enable hif tx DMA and interrupt
3608 +*
3609 +*/
3610 +void hif_tx_enable(void)
3611 +{
3612 +       /*TODO not sure poll_cntrl_en is required or not */
3613 +       writel( HIF_CTRL_DMA_EN, HIF_TX_CTRL);
3614 +       //writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_TXPKT_INT_EN), HIF_INT_ENABLE);
3615 +}
3616 +
3617 +/** Disable hif tx DMA and interrupt
3618 +*
3619 +*/
3620 +void hif_tx_disable(void)
3621 +{
3622 +       u32     hif_int;
3623 +
3624 +       writel(0, HIF_TX_CTRL);
3625 +
3626 +       hif_int = readl(HIF_INT_ENABLE);
3627 +       hif_int &= HIF_TXPKT_INT_EN;
3628 +       writel(hif_int, HIF_INT_ENABLE);
3629 +}
3630 +
3631 +/** Enable hif rx DMA and interrupt
3632 +*
3633 +*/
3634 +void hif_rx_enable(void)
3635 +{
3636 +       /*TODO not sure poll_cntrl_en is required or not */
3637 +       writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
3638 +       //writel((readl(HIF_INT_ENABLE) | HIF_INT_EN | HIF_RXPKT_INT_EN), HIF_INT_ENABLE);
3639 +}
3640 +
3641 +/** Disable hif rx DMA and interrupt
3642 +*
3643 +*/
3644 +void hif_rx_disable(void)
3645 +{
3646 +       u32     hif_int;
3647 +
3648 +       writel(0, HIF_RX_CTRL);
3649 +
3650 +       hif_int = readl(HIF_INT_ENABLE);
3651 +       hif_int &= HIF_RXPKT_INT_EN;
3652 +       writel(hif_int, HIF_INT_ENABLE);
3653 +
3654 +}
3655 diff --git a/drivers/net/pfe_eth/pfe/cbus.h b/drivers/net/pfe_eth/pfe/cbus.h
3656 new file mode 100644
3657 index 0000000..778fe45
3658 --- /dev/null
3659 +++ b/drivers/net/pfe_eth/pfe/cbus.h
3660 @@ -0,0 +1,74 @@
3661 +#ifndef _CBUS_H_
3662 +#define _CBUS_H_
3663 +
3664 +#define EMAC1_BASE_ADDR                (CBUS_BASE_ADDR + 0x200000)
3665 +#define EGPI1_BASE_ADDR                (CBUS_BASE_ADDR + 0x210000)
3666 +#define EMAC2_BASE_ADDR                (CBUS_BASE_ADDR + 0x220000)
3667 +#define EGPI2_BASE_ADDR                (CBUS_BASE_ADDR + 0x230000)
3668 +#define BMU1_BASE_ADDR         (CBUS_BASE_ADDR + 0x240000)
3669 +#define BMU2_BASE_ADDR         (CBUS_BASE_ADDR + 0x250000)
3670 +#define ARB_BASE_ADDR          (CBUS_BASE_ADDR + 0x260000) /* FIXME not documented */
3671 +#define DDR_CONFIG_BASE_ADDR   (CBUS_BASE_ADDR + 0x270000) /* FIXME not documented */
3672 +#define HIF_BASE_ADDR          (CBUS_BASE_ADDR + 0x280000)
3673 +#define HGPI_BASE_ADDR         (CBUS_BASE_ADDR + 0x290000)
3674 +#define LMEM_BASE_ADDR         (CBUS_BASE_ADDR + 0x300000)
3675 +#define LMEM_SIZE              0x10000
3676 +#define LMEM_END               (LMEM_BASE_ADDR + LMEM_SIZE)
3677 +#define TMU_CSR_BASE_ADDR      (CBUS_BASE_ADDR + 0x310000)
3678 +#define CLASS_CSR_BASE_ADDR    (CBUS_BASE_ADDR + 0x320000)
3679 +#if !defined(CONFIG_LS1012A)
3680 +#define EMAC3_BASE_ADDR                (CBUS_BASE_ADDR + 0x330000)
3681 +#define EGPI3_BASE_ADDR                (CBUS_BASE_ADDR + 0x340000)
3682 +#endif
3683 +#define HIF_NOCPY_BASE_ADDR    (CBUS_BASE_ADDR + 0x350000)
3684 +#define UTIL_CSR_BASE_ADDR     (CBUS_BASE_ADDR + 0x360000)
3685 +#define CBUS_GPT_BASE_ADDR     (CBUS_BASE_ADDR + 0x370000)
3686 +
3687 +#define IS_LMEM(addr, len)     (((unsigned long)(addr) >= LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= LMEM_END))
3688 +
3689 +/**
3690 +* \defgroup XXX_MEM_ACCESS_ADDR PE memory access through CSR
3691 +* XXX_MEM_ACCESS_ADDR register bit definitions.
3692 +* @{
3693 +*/
3694 +#define PE_MEM_ACCESS_WRITE            (1<<31)                 /**< Internal Memory Write. */
3695 +#define PE_MEM_ACCESS_READ             (0<<31)                 /**< Internal Memory Read. */
3696 +#define PE_MEM_ACCESS_IMEM             (1<<15)
3697 +#define PE_MEM_ACCESS_DMEM             (1<<16)
3698 +#define PE_MEM_ACCESS_BYTE_ENABLE(offset,size) (((((1 << (size)) - 1) << (4 - (offset) - (size))) & 0xf) << 24)        /**< Byte Enables of the Internal memory access. These are interpred in BE */
3699 +// @}
3700 +#include "cbus/emac.h"
3701 +#include "cbus/gpi.h"
3702 +#include "cbus/bmu.h"
3703 +#include "cbus/hif.h"
3704 +#include "cbus/tmu_csr.h"
3705 +#include "cbus/class_csr.h"
3706 +#include "cbus/hif_nocpy.h"
3707 +#include "cbus/util_csr.h"
3708 +#include "cbus/gpt.h"
3709 +
3710 +
3711 +/* PFE cores states */
3712 +#define CORE_DISABLE   0x00000000
3713 +#define CORE_ENABLE    0x00000001
3714 +#define CORE_SW_RESET  0x00000002
3715 +
3716 +/* LMEM defines */
3717 +#define LMEM_HDR_SIZE          0x0010
3718 +#define LMEM_BUF_SIZE_LN2      0x7
3719 +#define LMEM_BUF_SIZE          (1 << LMEM_BUF_SIZE_LN2)
3720 +
3721 +/* DDR defines */
3722 +#define DDR_HDR_SIZE           0x0100
3723 +#define DDR_BUF_SIZE_LN2       0xb
3724 +#define DDR_BUF_SIZE           (1 << DDR_BUF_SIZE_LN2)
3725 +
3726 +
3727 +/* Clock generation through PLL */
3728 +#if defined(CONFIG_PLATFORM_PCI)
3729 +#define PLL_CLK_EN     0
3730 +#else
3731 +#define PLL_CLK_EN     1
3732 +#endif
3733 +
3734 +#endif /* _CBUS_H_ */
3735 diff --git a/drivers/net/pfe_eth/pfe/cbus/bmu.h b/drivers/net/pfe_eth/pfe/cbus/bmu.h
3736 new file mode 100644
3737 index 0000000..f3e5e6d
3738 --- /dev/null
3739 +++ b/drivers/net/pfe_eth/pfe/cbus/bmu.h
3740 @@ -0,0 +1,37 @@
3741 +#ifndef _BMU_H_
3742 +#define _BMU_H_
3743 +
3744 +#define BMU_VERSION            0x000
3745 +#define BMU_CTRL               0x004
3746 +#define BMU_UCAST_CONFIG       0x008
3747 +#define BMU_UCAST_BASE_ADDR    0x00c
3748 +#define BMU_BUF_SIZE           0x010
3749 +#define BMU_BUF_CNT            0x014
3750 +#define BMU_THRES              0x018
3751 +#define BMU_INT_SRC            0x020
3752 +#define BMU_INT_ENABLE         0x024
3753 +#define BMU_ALLOC_CTRL         0x030
3754 +#define BMU_FREE_CTRL          0x034
3755 +#define BMU_FREE_ERR_ADDR      0x038
3756 +#define BMU_CURR_BUF_CNT       0x03c
3757 +#define BMU_MCAST_CNT          0x040
3758 +#define BMU_MCAST_ALLOC_CTRL   0x044
3759 +#define BMU_REM_BUF_CNT                0x048
3760 +#define BMU_LOW_WATERMARK      0x050
3761 +#define BMU_HIGH_WATERMARK     0x054
3762 +#define BMU_INT_MEM_ACCESS     0x100
3763 +
3764 +typedef struct {
3765 +       u32 baseaddr;
3766 +       u32 count;
3767 +       u32 size;
3768 +} BMU_CFG;
3769 +
3770 +
3771 +#define BMU1_BUF_SIZE  LMEM_BUF_SIZE_LN2
3772 +#define BMU2_BUF_SIZE  DDR_BUF_SIZE_LN2
3773 +
3774 +#define BMU2_MCAST_ALLOC_CTRL  BMU2_BASE_ADDR + BMU_MCAST_ALLOC_CTRL
3775 +
3776 +#endif /* _BMU_H_ */
3777 +
3778 diff --git a/drivers/net/pfe_eth/pfe/cbus/class_csr.h b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
3779 new file mode 100644
3780 index 0000000..f3151ec
3781 --- /dev/null
3782 +++ b/drivers/net/pfe_eth/pfe/cbus/class_csr.h
3783 @@ -0,0 +1,206 @@
3784 +#ifndef _CLASS_CSR_H_
3785 +#define _CLASS_CSR_H_
3786 +
3787 +/** @file class_csr.h.
3788 + * class_csr - block containing all the classifier control and status register. Mapped on CBUS and accessible from all PE's and ARM.
3789 + */
3790 +
3791 +
3792 +#define CLASS_VERSION                  (CLASS_CSR_BASE_ADDR + 0x000)
3793 +#define CLASS_TX_CTRL                  (CLASS_CSR_BASE_ADDR + 0x004)
3794 +#define CLASS_INQ_PKTPTR               (CLASS_CSR_BASE_ADDR + 0x010)
3795 +#define CLASS_HDR_SIZE                 (CLASS_CSR_BASE_ADDR + 0x014)   /**< (ddr_hdr_size[24:16], lmem_hdr_size[5:0]) */
3796 +#define CLASS_HDR_SIZE_LMEM(off)       ((off) & 0x3f)                  /**< LMEM header size for the Classifier block.\ Data in the LMEM is written from this offset. */
3797 +#define CLASS_HDR_SIZE_DDR(off)                (((off) & 0x1ff) << 16)         /**< DDR header size for the Classifier block.\ Data in the DDR is written from this offset. */
3798 +
3799 +#define CLASS_PE0_QB_DM_ADDR0          (CLASS_CSR_BASE_ADDR + 0x020)   /**< DMEM address of first [15:0] and second [31:16] buffers on QB side. */
3800 +#define CLASS_PE0_QB_DM_ADDR1          (CLASS_CSR_BASE_ADDR + 0x024)   /**< DMEM address of third [15:0] and fourth [31:16] buffers on QB side. */
3801 +
3802 +#define CLASS_PE0_RO_DM_ADDR0          (CLASS_CSR_BASE_ADDR + 0x060)   /**< DMEM address of first [15:0] and second [31:16] buffers on RO side. */
3803 +#define CLASS_PE0_RO_DM_ADDR1          (CLASS_CSR_BASE_ADDR + 0x064)   /**< DMEM address of third [15:0] and fourth [31:16] buffers on RO side. */
3804 +
3805 +/** @name Class PE memory access. Allows external PE's and HOST to read/write PMEM/DMEM memory ranges for each classifier PE.
3806 + */
3807 +//@{
3808 +#define CLASS_MEM_ACCESS_ADDR          (CLASS_CSR_BASE_ADDR + 0x100)   /**< {sr_pe_mem_cmd[31], csr_pe_mem_wren[27:24], csr_pe_mem_addr[23:0]}, See \ref XXX_MEM_ACCESS_ADDR for details. */
3809 +#define CLASS_MEM_ACCESS_WDATA         (CLASS_CSR_BASE_ADDR + 0x104)   /**< Internal Memory Access Write Data [31:0] */
3810 +#define CLASS_MEM_ACCESS_RDATA         (CLASS_CSR_BASE_ADDR + 0x108)   /**< Internal Memory Access Read Data [31:0] */
3811 +//@}
3812 +#define CLASS_TM_INQ_ADDR              (CLASS_CSR_BASE_ADDR + 0x114)
3813 +#define CLASS_PE_STATUS                        (CLASS_CSR_BASE_ADDR + 0x118)
3814 +
3815 +#define CLASS_PHY1_RX_PKTS             (CLASS_CSR_BASE_ADDR + 0x11c)
3816 +#define CLASS_PHY1_TX_PKTS             (CLASS_CSR_BASE_ADDR + 0x120)
3817 +#define CLASS_PHY1_LP_FAIL_PKTS                (CLASS_CSR_BASE_ADDR + 0x124)
3818 +#define CLASS_PHY1_INTF_FAIL_PKTS      (CLASS_CSR_BASE_ADDR + 0x128)
3819 +#define CLASS_PHY1_INTF_MATCH_PKTS     (CLASS_CSR_BASE_ADDR + 0x12c)
3820 +#define CLASS_PHY1_L3_FAIL_PKTS                (CLASS_CSR_BASE_ADDR + 0x130)
3821 +#define CLASS_PHY1_V4_PKTS             (CLASS_CSR_BASE_ADDR + 0x134)
3822 +#define CLASS_PHY1_V6_PKTS             (CLASS_CSR_BASE_ADDR + 0x138)
3823 +#define CLASS_PHY1_CHKSUM_ERR_PKTS     (CLASS_CSR_BASE_ADDR + 0x13c)
3824 +#define CLASS_PHY1_TTL_ERR_PKTS                (CLASS_CSR_BASE_ADDR + 0x140)
3825 +#define CLASS_PHY2_RX_PKTS             (CLASS_CSR_BASE_ADDR + 0x144)
3826 +#define CLASS_PHY2_TX_PKTS             (CLASS_CSR_BASE_ADDR + 0x148)
3827 +#define CLASS_PHY2_LP_FAIL_PKTS                (CLASS_CSR_BASE_ADDR + 0x14c)
3828 +#define CLASS_PHY2_INTF_FAIL_PKTS      (CLASS_CSR_BASE_ADDR + 0x150)
3829 +#define CLASS_PHY2_INTF_MATCH_PKTS     (CLASS_CSR_BASE_ADDR + 0x154)
3830 +#define CLASS_PHY2_L3_FAIL_PKTS                (CLASS_CSR_BASE_ADDR + 0x158)
3831 +#define CLASS_PHY2_V4_PKTS             (CLASS_CSR_BASE_ADDR + 0x15c)
3832 +#define CLASS_PHY2_V6_PKTS             (CLASS_CSR_BASE_ADDR + 0x160)
3833 +#define CLASS_PHY2_CHKSUM_ERR_PKTS     (CLASS_CSR_BASE_ADDR + 0x164)
3834 +#define CLASS_PHY2_TTL_ERR_PKTS                (CLASS_CSR_BASE_ADDR + 0x168)
3835 +#define CLASS_PHY3_RX_PKTS             (CLASS_CSR_BASE_ADDR + 0x16c)
3836 +#define CLASS_PHY3_TX_PKTS             (CLASS_CSR_BASE_ADDR + 0x170)
3837 +#define CLASS_PHY3_LP_FAIL_PKTS                (CLASS_CSR_BASE_ADDR + 0x174)
3838 +#define CLASS_PHY3_INTF_FAIL_PKTS      (CLASS_CSR_BASE_ADDR + 0x178)
3839 +#define CLASS_PHY3_INTF_MATCH_PKTS     (CLASS_CSR_BASE_ADDR + 0x17c)
3840 +#define CLASS_PHY3_L3_FAIL_PKTS                (CLASS_CSR_BASE_ADDR + 0x180)
3841 +#define CLASS_PHY3_V4_PKTS             (CLASS_CSR_BASE_ADDR + 0x184)
3842 +#define CLASS_PHY3_V6_PKTS             (CLASS_CSR_BASE_ADDR + 0x188)
3843 +#define CLASS_PHY3_CHKSUM_ERR_PKTS     (CLASS_CSR_BASE_ADDR + 0x18c)
3844 +#define CLASS_PHY3_TTL_ERR_PKTS                (CLASS_CSR_BASE_ADDR + 0x190)
3845 +#define CLASS_PHY1_ICMP_PKTS           (CLASS_CSR_BASE_ADDR + 0x194)
3846 +#define CLASS_PHY1_IGMP_PKTS           (CLASS_CSR_BASE_ADDR + 0x198)
3847 +#define CLASS_PHY1_TCP_PKTS            (CLASS_CSR_BASE_ADDR + 0x19c)
3848 +#define CLASS_PHY1_UDP_PKTS            (CLASS_CSR_BASE_ADDR + 0x1a0)
3849 +#define CLASS_PHY2_ICMP_PKTS           (CLASS_CSR_BASE_ADDR + 0x1a4)
3850 +#define CLASS_PHY2_IGMP_PKTS           (CLASS_CSR_BASE_ADDR + 0x1a8)
3851 +#define CLASS_PHY2_TCP_PKTS            (CLASS_CSR_BASE_ADDR + 0x1ac)
3852 +#define CLASS_PHY2_UDP_PKTS            (CLASS_CSR_BASE_ADDR + 0x1b0)
3853 +#define CLASS_PHY3_ICMP_PKTS           (CLASS_CSR_BASE_ADDR + 0x1b4)
3854 +#define CLASS_PHY3_IGMP_PKTS           (CLASS_CSR_BASE_ADDR + 0x1b8)
3855 +#define CLASS_PHY3_TCP_PKTS            (CLASS_CSR_BASE_ADDR + 0x1bc)
3856 +#define CLASS_PHY3_UDP_PKTS            (CLASS_CSR_BASE_ADDR + 0x1c0)
3857 +#define CLASS_PHY4_ICMP_PKTS           (CLASS_CSR_BASE_ADDR + 0x1c4)
3858 +#define CLASS_PHY4_IGMP_PKTS           (CLASS_CSR_BASE_ADDR + 0x1c8)
3859 +#define CLASS_PHY4_TCP_PKTS            (CLASS_CSR_BASE_ADDR + 0x1cc)
3860 +#define CLASS_PHY4_UDP_PKTS            (CLASS_CSR_BASE_ADDR + 0x1d0)
3861 +#define CLASS_PHY4_RX_PKTS             (CLASS_CSR_BASE_ADDR + 0x1d4)
3862 +#define CLASS_PHY4_TX_PKTS             (CLASS_CSR_BASE_ADDR + 0x1d8)
3863 +#define CLASS_PHY4_LP_FAIL_PKTS                (CLASS_CSR_BASE_ADDR + 0x1dc)
3864 +#define CLASS_PHY4_INTF_FAIL_PKTS      (CLASS_CSR_BASE_ADDR + 0x1e0)
3865 +#define CLASS_PHY4_INTF_MATCH_PKTS     (CLASS_CSR_BASE_ADDR + 0x1e4)
3866 +#define CLASS_PHY4_L3_FAIL_PKTS                (CLASS_CSR_BASE_ADDR + 0x1e8)
3867 +#define CLASS_PHY4_V4_PKTS             (CLASS_CSR_BASE_ADDR + 0x1ec)
3868 +#define CLASS_PHY4_V6_PKTS             (CLASS_CSR_BASE_ADDR + 0x1f0)
3869 +#define CLASS_PHY4_CHKSUM_ERR_PKTS     (CLASS_CSR_BASE_ADDR + 0x1f4)
3870 +#define CLASS_PHY4_TTL_ERR_PKTS                (CLASS_CSR_BASE_ADDR + 0x1f8)
3871 +
3872 +#define CLASS_PE_SYS_CLK_RATIO         (CLASS_CSR_BASE_ADDR + 0x200)
3873 +#define CLASS_AFULL_THRES              (CLASS_CSR_BASE_ADDR + 0x204)
3874 +#define CLASS_GAP_BETWEEN_READS                (CLASS_CSR_BASE_ADDR + 0x208)
3875 +#define CLASS_MAX_BUF_CNT              (CLASS_CSR_BASE_ADDR + 0x20c)
3876 +#define CLASS_TSQ_FIFO_THRES           (CLASS_CSR_BASE_ADDR + 0x210)
3877 +#define CLASS_TSQ_MAX_CNT              (CLASS_CSR_BASE_ADDR + 0x214)
3878 +#define CLASS_IRAM_DATA_0              (CLASS_CSR_BASE_ADDR + 0x218)
3879 +#define CLASS_IRAM_DATA_1              (CLASS_CSR_BASE_ADDR + 0x21c)
3880 +#define CLASS_IRAM_DATA_2              (CLASS_CSR_BASE_ADDR + 0x220)
3881 +#define CLASS_IRAM_DATA_3              (CLASS_CSR_BASE_ADDR + 0x224)
3882 +
3883 +#define CLASS_BUS_ACCESS_ADDR          (CLASS_CSR_BASE_ADDR + 0x228)
3884 +#define CLASS_BUS_ACCESS_ADDR_MASK     (0x0001FFFF)    //bit 23:0 of PE peripheral address are stored in CLASS_BUS_ACCESS_ADDR
3885 +
3886 +#define CLASS_BUS_ACCESS_WDATA         (CLASS_CSR_BASE_ADDR + 0x22c)
3887 +#define CLASS_BUS_ACCESS_RDATA         (CLASS_CSR_BASE_ADDR + 0x230)
3888 +
3889 +#define CLASS_ROUTE_HASH_ENTRY_SIZE    (CLASS_CSR_BASE_ADDR + 0x234)           /**< (route_entry_size[9:0], route_hash_size[23:16] (this is actually ln2(size))) */
3890 +#define CLASS_ROUTE_ENTRY_SIZE(size)    ((size) & 0x1ff)
3891 +#define CLASS_ROUTE_HASH_SIZE(hash_bits) (((hash_bits) & 0xff) << 16)
3892 +
3893 +#define CLASS_ROUTE_TABLE_BASE         (CLASS_CSR_BASE_ADDR + 0x238)
3894 +
3895 +#define CLASS_ROUTE_MULTI              (CLASS_CSR_BASE_ADDR + 0x23c)
3896 +#define CLASS_SMEM_OFFSET              (CLASS_CSR_BASE_ADDR + 0x240)
3897 +#define CLASS_LMEM_BUF_SIZE            (CLASS_CSR_BASE_ADDR + 0x244)
3898 +#define CLASS_VLAN_ID                  (CLASS_CSR_BASE_ADDR + 0x248)
3899 +#define CLASS_BMU1_BUF_FREE            (CLASS_CSR_BASE_ADDR + 0x24c)
3900 +#define CLASS_USE_TMU_INQ              (CLASS_CSR_BASE_ADDR + 0x250)
3901 +#define CLASS_VLAN_ID1                 (CLASS_CSR_BASE_ADDR + 0x254)
3902 +
3903 +#define CLASS_BUS_ACCESS_BASE          (CLASS_CSR_BASE_ADDR + 0x258)
3904 +#define CLASS_BUS_ACCESS_BASE_MASK     (0xFF000000)    //bit 31:24 of PE peripheral address are stored in CLASS_BUS_ACCESS_BASE
3905 +
3906 +#define CLASS_HIF_PARSE                        (CLASS_CSR_BASE_ADDR + 0x25c)
3907 +
3908 +#define CLASS_HOST_PE0_GP              (CLASS_CSR_BASE_ADDR + 0x260)
3909 +#define CLASS_PE0_GP                   (CLASS_CSR_BASE_ADDR + 0x264)
3910 +#define CLASS_HOST_PE1_GP              (CLASS_CSR_BASE_ADDR + 0x268)
3911 +#define CLASS_PE1_GP                   (CLASS_CSR_BASE_ADDR + 0x26c)
3912 +#define CLASS_HOST_PE2_GP              (CLASS_CSR_BASE_ADDR + 0x270)
3913 +#define CLASS_PE2_GP                   (CLASS_CSR_BASE_ADDR + 0x274)
3914 +#define CLASS_HOST_PE3_GP              (CLASS_CSR_BASE_ADDR + 0x278)
3915 +#define CLASS_PE3_GP                   (CLASS_CSR_BASE_ADDR + 0x27c)
3916 +#define CLASS_HOST_PE4_GP              (CLASS_CSR_BASE_ADDR + 0x280)
3917 +#define CLASS_PE4_GP                   (CLASS_CSR_BASE_ADDR + 0x284)
3918 +#define CLASS_HOST_PE5_GP              (CLASS_CSR_BASE_ADDR + 0x288)
3919 +#define CLASS_PE5_GP                   (CLASS_CSR_BASE_ADDR + 0x28c)
3920 +
3921 +#define CLASS_PE_INT_SRC               (CLASS_CSR_BASE_ADDR + 0x290)
3922 +#define CLASS_PE_INT_ENABLE            (CLASS_CSR_BASE_ADDR + 0x294)
3923 +
3924 +#define CLASS_TPID0_TPID1              (CLASS_CSR_BASE_ADDR + 0x298)
3925 +#define CLASS_TPID2                    (CLASS_CSR_BASE_ADDR + 0x29c)
3926 +
3927 +#define CLASS_L4_CHKSUM_ADDR           (CLASS_CSR_BASE_ADDR + 0x2a0)
3928 +
3929 +#define CLASS_PE0_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2a4)
3930 +#define CLASS_PE1_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2a8)
3931 +#define CLASS_PE2_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2ac)
3932 +#define CLASS_PE3_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2b0)
3933 +#define CLASS_PE4_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2b4)
3934 +#define CLASS_PE5_DEBUG                        (CLASS_CSR_BASE_ADDR + 0x2b8)
3935 +
3936 +#define CLASS_STATE                    (CLASS_CSR_BASE_ADDR + 0x2bc)
3937 +
3938 +/* CLASS defines */
3939 +#define CLASS_PBUF_SIZE                        0x100   /* Fixed by hardware */
3940 +#define CLASS_PBUF_HEADER_OFFSET       0x80    /* Can be configured */
3941 +
3942 +#define CLASS_PBUF0_BASE_ADDR          0x000                                           /* Can be configured */
3943 +#define CLASS_PBUF1_BASE_ADDR          (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_SIZE)       /* Can be configured */
3944 +#define CLASS_PBUF2_BASE_ADDR          (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_SIZE)       /* Can be configured */
3945 +#define CLASS_PBUF3_BASE_ADDR          (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_SIZE)       /* Can be configured */
3946 +
3947 +#define CLASS_PBUF0_HEADER_BASE_ADDR   (CLASS_PBUF0_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
3948 +#define CLASS_PBUF1_HEADER_BASE_ADDR   (CLASS_PBUF1_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
3949 +#define CLASS_PBUF2_HEADER_BASE_ADDR   (CLASS_PBUF2_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
3950 +#define CLASS_PBUF3_HEADER_BASE_ADDR   (CLASS_PBUF3_BASE_ADDR + CLASS_PBUF_HEADER_OFFSET)
3951 +
3952 +#define CLASS_PE0_RO_DM_ADDR0_VAL      ((CLASS_PBUF1_BASE_ADDR << 16) | CLASS_PBUF0_BASE_ADDR)
3953 +#define CLASS_PE0_RO_DM_ADDR1_VAL      ((CLASS_PBUF3_BASE_ADDR << 16) | CLASS_PBUF2_BASE_ADDR)
3954 +
3955 +#define CLASS_PE0_QB_DM_ADDR0_VAL      ((CLASS_PBUF1_HEADER_BASE_ADDR << 16) | CLASS_PBUF0_HEADER_BASE_ADDR)
3956 +#define CLASS_PE0_QB_DM_ADDR1_VAL      ((CLASS_PBUF3_HEADER_BASE_ADDR << 16) | CLASS_PBUF2_HEADER_BASE_ADDR)
3957 +
3958 +#define CLASS_ROUTE_SIZE               128
3959 +#define CLASS_ROUTE_HASH_BITS          20
3960 +#define CLASS_ROUTE_HASH_MASK          ((1 << CLASS_ROUTE_HASH_BITS) - 1)
3961 +
3962 +#define        CLASS_ROUTE0_BASE_ADDR  0x400                                           /* Can be configured */
3963 +#define CLASS_ROUTE1_BASE_ADDR (CLASS_ROUTE0_BASE_ADDR + CLASS_ROUTE_SIZE)     /* Can be configured */
3964 +#define CLASS_ROUTE2_BASE_ADDR (CLASS_ROUTE1_BASE_ADDR + CLASS_ROUTE_SIZE)     /* Can be configured */
3965 +#define CLASS_ROUTE3_BASE_ADDR (CLASS_ROUTE2_BASE_ADDR + CLASS_ROUTE_SIZE)     /* Can be configured */
3966 +
3967 +#define TWO_LEVEL_ROUTE                (1 << 0)
3968 +#define PHYNO_IN_HASH          (1 << 1)
3969 +#define HW_ROUTE_FETCH         (1 << 3)
3970 +#define HW_BRIDGE_FETCH                (1 << 5)
3971 +#define IP_ALIGNED             (1 << 6)
3972 +#define ARC_HIT_CHECK_EN       (1 << 7)
3973 +#define CLASS_TOE              (1 << 11)
3974 +#define HASH_NORMAL            (0 << 12)
3975 +#define HASH_CRC_PORT          (1 << 12)
3976 +#define HASH_CRC_IP            (2 << 12)
3977 +#define HASH_CRC_PORT_IP       (3 << 12)
3978 +#define QB2BUS_LE              (1 << 15)
3979 +
3980 +#define        TCP_CHKSUM_DROP         (1 << 0)
3981 +#define        UDP_CHKSUM_DROP         (1 << 1)
3982 +#define        IPV4_CHKSUM_DROP        (1 << 9)
3983 +
3984 +typedef struct {
3985 +       u32 route_table_baseaddr;
3986 +       u32 route_table_hash_bits;
3987 +} CLASS_CFG;
3988 +
3989 +#endif /* _CLASS_CSR_H_ */
3990 diff --git a/drivers/net/pfe_eth/pfe/cbus/emac.h b/drivers/net/pfe_eth/pfe/cbus/emac.h
3991 new file mode 100644
3992 index 0000000..1f308ce
3993 --- /dev/null
3994 +++ b/drivers/net/pfe_eth/pfe/cbus/emac.h
3995 @@ -0,0 +1,232 @@
3996 +#ifndef _EMAC_H_
3997 +#define _EMAC_H_
3998 +
3999 +#define EMAC_IEVENT_REG        0x004
4000 +#define EMAC_IMASK_REG 0x008
4001 +#define EMAC_R_DES_ACTIVE_REG  0x010
4002 +#define EMAC_X_DES_ACTIVE_REG  0x014
4003 +#define EMAC_ECNTRL_REG                0x024
4004 +#define EMAC_MII_DATA_REG      0x040
4005 +#define EMAC_MII_CTRL_REG      0x044
4006 +#define EMAC_MIB_CTRL_STS_REG  0x064
4007 +#define EMAC_RCNTRL_REG                0x084
4008 +#define EMAC_TCNTRL_REG                0x0C4
4009 +#define EMAC_PHY_ADDR_LOW      0x0E4
4010 +#define EMAC_PHY_ADDR_HIGH     0x0E8
4011 +#define EMAC_TFWR_STR_FWD      0x144
4012 +#define EMAC_RX_SECTIOM_FULL   0x190
4013 +#define EMAC_TX_SECTION_EMPTY  0x1A0
4014 +#define EMAC_TRUNC_FL          0x1B0
4015 +
4016 +#define RMON_T_DROP            0x200 /* Count of frames not cntd correctly */
4017 +#define RMON_T_PACKETS         0x204 /* RMON TX packet count */
4018 +#define RMON_T_BC_PKT          0x208 /* RMON TX broadcast pkts */
4019 +#define RMON_T_MC_PKT          0x20c /* RMON TX multicast pkts */
4020 +#define RMON_T_CRC_ALIGN       0x210 /* RMON TX pkts with CRC align err */
4021 +#define RMON_T_UNDERSIZE       0x214 /* RMON TX pkts < 64 bytes, good CRC */
4022 +#define RMON_T_OVERSIZE                0x218 /* RMON TX pkts > MAX_FL bytes good CRC */
4023 +#define RMON_T_FRAG            0x21c /* RMON TX pkts < 64 bytes, bad CRC */
4024 +#define RMON_T_JAB             0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */
4025 +#define RMON_T_COL             0x224 /* RMON TX collision count */
4026 +#define RMON_T_P64             0x228 /* RMON TX 64 byte pkts */
4027 +#define RMON_T_P65TO127                0x22c /* RMON TX 65 to 127 byte pkts */
4028 +#define RMON_T_P128TO255       0x230 /* RMON TX 128 to 255 byte pkts */
4029 +#define RMON_T_P256TO511       0x234 /* RMON TX 256 to 511 byte pkts */
4030 +#define RMON_T_P512TO1023      0x238 /* RMON TX 512 to 1023 byte pkts */
4031 +#define RMON_T_P1024TO2047     0x23c /* RMON TX 1024 to 2047 byte pkts */
4032 +#define RMON_T_P_GTE2048       0x240 /* RMON TX pkts > 2048 bytes */
4033 +#define RMON_T_OCTETS          0x244 /* RMON TX octets */
4034 +#define IEEE_T_DROP            0x248 /* Count of frames not counted crtly */
4035 +#define IEEE_T_FRAME_OK                0x24c /* Frames tx'd OK */
4036 +#define IEEE_T_1COL            0x250 /* Frames tx'd with single collision */
4037 +#define IEEE_T_MCOL            0x254 /* Frames tx'd with multiple collision */
4038 +#define IEEE_T_DEF             0x258 /* Frames tx'd after deferral delay */
4039 +#define IEEE_T_LCOL            0x25c /* Frames tx'd with late collision */
4040 +#define IEEE_T_EXCOL           0x260 /* Frames tx'd with excesv collisions */
4041 +#define IEEE_T_MACERR          0x264 /* Frames tx'd with TX FIFO underrun */
4042 +#define IEEE_T_CSERR           0x268 /* Frames tx'd with carrier sense err */
4043 +#define IEEE_T_SQE             0x26c /* Frames tx'd with SQE err */
4044 +#define IEEE_T_FDXFC           0x270 /* Flow control pause frames tx'd */
4045 +#define IEEE_T_OCTETS_OK       0x274 /* Octet count for frames tx'd w/o err */
4046 +#define RMON_R_PACKETS         0x284 /* RMON RX packet count */
4047 +#define RMON_R_BC_PKT          0x288 /* RMON RX broadcast pkts */
4048 +#define RMON_R_MC_PKT          0x28c /* RMON RX multicast pkts */
4049 +#define RMON_R_CRC_ALIGN       0x290 /* RMON RX pkts with CRC alignment err */
4050 +#define RMON_R_UNDERSIZE       0x294 /* RMON RX pkts < 64 bytes, good CRC */
4051 +#define RMON_R_OVERSIZE                0x298 /* RMON RX pkts > MAX_FL bytes good CRC */
4052 +#define RMON_R_FRAG            0x29c /* RMON RX pkts < 64 bytes, bad CRC */
4053 +#define RMON_R_JAB             0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */
4054 +#define RMON_R_RESVD_O         0x2a4 /* Reserved */
4055 +#define RMON_R_P64             0x2a8 /* RMON RX 64 byte pkts */
4056 +#define RMON_R_P65TO127                0x2ac /* RMON RX 65 to 127 byte pkts */
4057 +#define RMON_R_P128TO255       0x2b0 /* RMON RX 128 to 255 byte pkts */
4058 +#define RMON_R_P256TO511       0x2b4 /* RMON RX 256 to 511 byte pkts */
4059 +#define RMON_R_P512TO1023      0x2b8 /* RMON RX 512 to 1023 byte pkts */
4060 +#define RMON_R_P1024TO2047     0x2bc /* RMON RX 1024 to 2047 byte pkts */
4061 +#define RMON_R_P_GTE2048       0x2c0 /* RMON RX pkts > 2048 bytes */
4062 +#define RMON_R_OCTETS          0x2c4 /* RMON RX octets */
4063 +#define IEEE_R_DROP            0x2c8 /* Count frames not counted correctly */
4064 +#define IEEE_R_FRAME_OK                0x2cc /* Frames rx'd OK */
4065 +#define IEEE_R_CRC             0x2d0 /* Frames rx'd with CRC err */
4066 +#define IEEE_R_ALIGN           0x2d4 /* Frames rx'd with alignment err */
4067 +#define IEEE_R_MACERR          0x2d8 /* Receive FIFO overflow count */
4068 +#define IEEE_R_FDXFC           0x2dc /* Flow control pause frames rx'd */
4069 +#define IEEE_R_OCTETS_OK       0x2e0 /* Octet cnt for frames rx'd w/o err */
4070 +
4071 +
4072 +/* GEMAC definitions and settings */
4073 +
4074 +#define EMAC_PORT_0                    0
4075 +#define EMAC_PORT_1                    1
4076 +
4077 +/* GEMAC Bit definitions */
4078 +#define EMAC_IEVENT_HBERR                0x80000000
4079 +#define EMAC_IEVENT_BABR                 0x40000000
4080 +#define EMAC_IEVENT_BABT                 0x20000000
4081 +#define EMAC_IEVENT_GRA                  0x10000000
4082 +#define EMAC_IEVENT_TXF                  0x08000000
4083 +#define EMAC_IEVENT_TXB                  0x04000000
4084 +#define EMAC_IEVENT_RXF                  0x02000000
4085 +#define EMAC_IEVENT_RXB                  0x01000000
4086 +#define EMAC_IEVENT_MII                  0x00800000
4087 +#define EMAC_IEVENT_EBERR                0x00400000
4088 +#define EMAC_IEVENT_LC                   0x00200000
4089 +#define EMAC_IEVENT_RL                   0x00100000
4090 +#define EMAC_IEVENT_UN                   0x00080000
4091 +
4092 +#define EMAC_IMASK_HBERR                 0x80000000
4093 +#define EMAC_IMASK_BABR                  0x40000000
4094 +#define EMAC_IMASKT_BABT                 0x20000000
4095 +#define EMAC_IMASK_GRA                   0x10000000
4096 +#define EMAC_IMASKT_TXF                  0x08000000
4097 +#define EMAC_IMASK_TXB                   0x04000000
4098 +#define EMAC_IMASKT_RXF                  0x02000000
4099 +#define EMAC_IMASK_RXB                   0x01000000
4100 +#define EMAC_IMASK_MII                   0x00800000
4101 +#define EMAC_IMASK_EBERR                 0x00400000
4102 +#define EMAC_IMASK_LC                    0x00200000
4103 +#define EMAC_IMASKT_RL                   0x00100000
4104 +#define EMAC_IMASK_UN                    0x00080000
4105 +
4106 +#define EMAC_RCNTRL_MAX_FL_SHIFT         16
4107 +#define EMAC_RCNTRL_LOOP                 0x00000001
4108 +#define EMAC_RCNTRL_DRT                  0x00000002
4109 +#define EMAC_RCNTRL_MII_MODE             0x00000004
4110 +#define EMAC_RCNTRL_PROM                 0x00000008
4111 +#define EMAC_RCNTRL_BC_REJ               0x00000010
4112 +#define EMAC_RCNTRL_FCE                  0x00000020
4113 +#define EMAC_RCNTRL_RGMII                0x00000040
4114 +#define EMAC_RCNTRL_SGMII                0x00000080
4115 +#define EMAC_RCNTRL_RMII                 0x00000100
4116 +#define EMAC_RCNTRL_RMII_10T             0x00000200
4117 +#define EMAC_RCNTRL_CRC_FWD             0x00004000
4118 +
4119 +#define EMAC_TCNTRL_GTS                  0x00000001
4120 +#define EMAC_TCNTRL_HBC                  0x00000002
4121 +#define EMAC_TCNTRL_FDEN                 0x00000004
4122 +#define EMAC_TCNTRL_TFC_PAUSE            0x00000008
4123 +#define EMAC_TCNTRL_RFC_PAUSE            0x00000010
4124 +
4125 +#define EMAC_ECNTRL_RESET                0x00000001      /* reset the EMAC */
4126 +#define EMAC_ECNTRL_ETHER_EN             0x00000002      /* enable the EMAC */
4127 +#define EMAC_ECNTRL_SPEED                0x00000020
4128 +#define EMAC_ECNTRL_DBSWAP               0x00000100
4129 +
4130 +#define EMAC_X_WMRK_STRFWD               0x00000100
4131 +
4132 +#define EMAC_X_DES_ACTIVE_TDAR           0x01000000
4133 +#define EMAC_R_DES_ACTIVE_RDAR           0x01000000
4134 +
4135 +
4136 +
4137 +/* The possible operating speeds of the MAC, currently supporting 10, 100 and
4138 + * 1000Mb modes.
4139 + */
4140 +typedef enum {SPEED_10M, SPEED_100M, SPEED_1000M, SPEED_1000M_PCS} MAC_SPEED;
4141 +
4142 +#define GMII   1
4143 +#define MII    2
4144 +#define RMII   3
4145 +#define RGMII  4
4146 +#define SGMII  5
4147 +
4148 +#define DUPLEX_HALF    0x00
4149 +#define DUPLEX_FULL    0x01
4150 +
4151 +
4152 +/* Default configuration */
4153 +#define EMAC0_DEFAULT_DUPLEX_MODE      FULLDUPLEX
4154 +#define EMAC0_DEFAULT_EMAC_MODE                RGMII
4155 +#define EMAC0_DEFAULT_EMAC_SPEED       SPEED_1000M
4156 +
4157 +#define EMAC1_DEFAULT_DUPLEX_MODE      FULLDUPLEX
4158 +#define EMAC1_DEFAULT_EMAC_MODE                SGMII
4159 +#define EMAC1_DEFAULT_EMAC_SPEED       SPEED_1000M
4160 +
4161 +/* MII-related definitios */
4162 +#define EMAC_MII_DATA_ST         0x40000000      /* Start of frame delimiter */
4163 +#define EMAC_MII_DATA_OP_RD      0x20000000      /* Perform a read operation */
4164 +#define EMAC_MII_DATA_OP_WR      0x10000000      /* Perform a write operation */
4165 +#define EMAC_MII_DATA_PA_MSK     0x0f800000      /* PHY Address field mask */
4166 +#define EMAC_MII_DATA_RA_MSK     0x007c0000      /* PHY Register field mask */
4167 +#define EMAC_MII_DATA_TA         0x00020000      /* Turnaround */
4168 +#define EMAC_MII_DATA_DATAMSK    0x0000ffff      /* PHY data field */
4169 +
4170 +#define EMAC_MII_DATA_RA_SHIFT   18      /* MII Register address bits */
4171 +#define EMAC_MII_DATA_RA_MASK   0x1F      /* MII Register address mask */
4172 +#define EMAC_MII_DATA_PA_SHIFT   23      /* MII PHY address bits */
4173 +#define EMAC_MII_DATA_PA_MASK    0x1F      /* MII PHY address mask */
4174 +
4175 +#define EMAC_MII_DATA_RA(v) ((v & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT)
4176 +#define EMAC_MII_DATA_PA(v) ((v & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_PA_SHIFT)
4177 +#define EMAC_MII_DATA(v)    (v & 0xffff)
4178 +
4179 +#define EMAC_MII_SPEED_SHIFT   1
4180 +#define EMAC_HOLDTIME_SHIFT    8
4181 +#define EMAC_HOLDTIME_MASK     0x7
4182 +#define EMAC_HOLDTIME(v)       ((v & EMAC_HOLDTIME_MASK) << EMAC_HOLDTIME_SHIFT)
4183 +
4184 +/* The Address organisation for the MAC device.  All addresses are split into
4185 + * two 32-bit register fields.  The first one (bottom) is the lower 32-bits of
4186 + * the address and the other field are the high order bits - this may be 16-bits
4187 + * in the case of MAC addresses, or 32-bits for the hash address.
4188 + * In terms of memory storage, the first item (bottom) is assumed to be at a
4189 + * lower address location than 'top'. i.e. top should be at address location of
4190 + * 'bottom' + 4 bytes.
4191 + */
4192 +typedef struct {
4193 +       u32 bottom;     /* Lower 32-bits of address. */
4194 +       u32 top;        /* Upper 32-bits of address. */
4195 +} MAC_ADDR;
4196 +
4197 +
4198 +/* The following is the organisation of the address filters section of the MAC
4199 + * registers.  The Cadence MAC contains four possible specific address match
4200 + * addresses, if an incoming frame corresponds to any one of these four
4201 + * addresses then the frame will be copied to memory.
4202 + * It is not necessary for all four of the address match registers to be
4203 + * programmed, this is application dependant.
4204 + */
4205 +typedef struct {
4206 +       MAC_ADDR one;        /* Specific address register 1. */
4207 +       MAC_ADDR two;        /* Specific address register 2. */
4208 +       MAC_ADDR three;      /* Specific address register 3. */
4209 +       MAC_ADDR four;       /* Specific address register 4. */
4210 +} SPEC_ADDR;
4211 +
4212 +typedef struct {
4213 +       u32 mode;
4214 +       u32 speed;
4215 +       u32 duplex;
4216 +} GEMAC_CFG;
4217 +
4218 +/* Internal PHY Registers - SGMII */
4219 +#define PHY_SGMII_CR_PHY_RESET      0x8000
4220 +#define PHY_SGMII_CR_RESET_AN       0x0200
4221 +#define PHY_SGMII_CR_DEF_VAL        0x1140
4222 +#define PHY_SGMII_DEV_ABILITY_SGMII 0x4001
4223 +#define PHY_SGMII_IF_MODE_AN        0x0002
4224 +#define PHY_SGMII_IF_MODE_SGMII     0x0001
4225 +
4226 +
4227 +#endif /* _EMAC_H_ */
4228 diff --git a/drivers/net/pfe_eth/pfe/cbus/gpi.h b/drivers/net/pfe_eth/pfe/cbus/gpi.h
4229 new file mode 100644
4230 index 0000000..d2d165f
4231 --- /dev/null
4232 +++ b/drivers/net/pfe_eth/pfe/cbus/gpi.h
4233 @@ -0,0 +1,60 @@
4234 +#ifndef _GPI_H_
4235 +#define _GPI_H_
4236 +
4237 +#define GPI_VERSION                    0x00
4238 +#define GPI_CTRL                       0x04
4239 +#define GPI_RX_CONFIG                  0x08
4240 +#define GPI_HDR_SIZE                   0x0c
4241 +#define GPI_BUF_SIZE                   0x10
4242 +#define GPI_LMEM_ALLOC_ADDR            0x14
4243 +#define GPI_LMEM_FREE_ADDR             0x18
4244 +#define GPI_DDR_ALLOC_ADDR             0x1c
4245 +#define GPI_DDR_FREE_ADDR              0x20
4246 +#define GPI_CLASS_ADDR                 0x24
4247 +#define GPI_DRX_FIFO                   0x28
4248 +#define GPI_TRX_FIFO                   0x2c
4249 +#define GPI_INQ_PKTPTR                 0x30
4250 +#define GPI_DDR_DATA_OFFSET            0x34
4251 +#define GPI_LMEM_DATA_OFFSET           0x38
4252 +#define GPI_TMLF_TX                    0x4c
4253 +#define GPI_DTX_ASEQ                   0x50
4254 +#define GPI_FIFO_STATUS                        0x54
4255 +#define GPI_FIFO_DEBUG                 0x58
4256 +#define GPI_TX_PAUSE_TIME              0x5c
4257 +#define GPI_LMEM_SEC_BUF_DATA_OFFSET   0x60
4258 +#define GPI_DDR_SEC_BUF_DATA_OFFSET    0x64
4259 +#define GPI_TOE_CHKSUM_EN              0x68
4260 +#define GPI_OVERRUN_DROPCNT            0x6c
4261 +
4262 +typedef struct {
4263 +       u32 lmem_rtry_cnt;
4264 +       u32 tmlf_txthres;
4265 +       u32 aseq_len;
4266 +} GPI_CFG;
4267 +
4268 +
4269 +/* GPI commons defines */
4270 +#define GPI_LMEM_BUF_EN                0x1
4271 +#define GPI_DDR_BUF_EN         0x1
4272 +
4273 +/* EGPI 1 defines */
4274 +#define EGPI1_LMEM_RTRY_CNT    0x40
4275 +#define EGPI1_TMLF_TXTHRES     0xBC
4276 +#define EGPI1_ASEQ_LEN         0x50
4277 +
4278 +/* EGPI 2 defines */
4279 +#define EGPI2_LMEM_RTRY_CNT    0x40
4280 +#define EGPI2_TMLF_TXTHRES     0xBC
4281 +#define EGPI2_ASEQ_LEN         0x40
4282 +
4283 +/* EGPI 3 defines */
4284 +#define EGPI3_LMEM_RTRY_CNT    0x40
4285 +#define EGPI3_TMLF_TXTHRES     0xBC
4286 +#define EGPI3_ASEQ_LEN         0x40
4287 +
4288 +/* HGPI defines */
4289 +#define HGPI_LMEM_RTRY_CNT     0x40
4290 +#define HGPI_TMLF_TXTHRES      0xBC
4291 +#define HGPI_ASEQ_LEN          0x40
4292 +
4293 +#endif /* _GPI_H_ */
4294 diff --git a/drivers/net/pfe_eth/pfe/cbus/gpt.h b/drivers/net/pfe_eth/pfe/cbus/gpt.h
4295 new file mode 100644
4296 index 0000000..f8c114b
4297 --- /dev/null
4298 +++ b/drivers/net/pfe_eth/pfe/cbus/gpt.h
4299 @@ -0,0 +1,11 @@
4300 +#ifndef _CBUS_GPT_H_
4301 +#define _CBUS_GPT_H_
4302 +
4303 +#define CBUS_GPT_VERSION        (CBUS_GPT_BASE_ADDR + 0x00)
4304 +#define CBUS_GPT_STATUS                 (CBUS_GPT_BASE_ADDR + 0x04)
4305 +#define CBUS_GPT_CONFIG                 (CBUS_GPT_BASE_ADDR + 0x08)
4306 +#define CBUS_GPT_COUNTER        (CBUS_GPT_BASE_ADDR + 0x0c)
4307 +#define CBUS_GPT_PERIOD                 (CBUS_GPT_BASE_ADDR + 0x10)
4308 +#define CBUS_GPT_WIDTH          (CBUS_GPT_BASE_ADDR + 0x14)
4309 +
4310 +#endif /* _CBUS_GPT_H_ */
4311 diff --git a/drivers/net/pfe_eth/pfe/cbus/hif.h b/drivers/net/pfe_eth/pfe/cbus/hif.h
4312 new file mode 100644
4313 index 0000000..a4dd7c2
4314 --- /dev/null
4315 +++ b/drivers/net/pfe_eth/pfe/cbus/hif.h
4316 @@ -0,0 +1,62 @@
4317 +#ifndef _HIF_H_
4318 +#define _HIF_H_
4319 +
4320 +/** @file hif.h.
4321 + * hif - PFE hif block control and status register. Mapped on CBUS and accessible from all PE's and ARM.
4322 + */
4323 +#define HIF_VERSION            (HIF_BASE_ADDR + 0x00)
4324 +#define HIF_TX_CTRL            (HIF_BASE_ADDR + 0x04)
4325 +#define HIF_TX_CURR_BD_ADDR    (HIF_BASE_ADDR + 0x08)
4326 +#define HIF_TX_ALLOC           (HIF_BASE_ADDR + 0x0c)
4327 +#define HIF_TX_BDP_ADDR                (HIF_BASE_ADDR + 0x10)
4328 +#define HIF_TX_STATUS          (HIF_BASE_ADDR + 0x14)
4329 +#define HIF_RX_CTRL            (HIF_BASE_ADDR + 0x20)
4330 +#define HIF_RX_BDP_ADDR                (HIF_BASE_ADDR + 0x24)
4331 +#define HIF_RX_STATUS          (HIF_BASE_ADDR + 0x30)
4332 +#define HIF_INT_SRC            (HIF_BASE_ADDR + 0x34)
4333 +#define HIF_INT_ENABLE         (HIF_BASE_ADDR + 0x38)
4334 +#define HIF_POLL_CTRL          (HIF_BASE_ADDR + 0x3c)
4335 +#define HIF_RX_CURR_BD_ADDR    (HIF_BASE_ADDR + 0x40)
4336 +#define HIF_RX_ALLOC           (HIF_BASE_ADDR + 0x44)
4337 +#define HIF_TX_DMA_STATUS      (HIF_BASE_ADDR + 0x48)
4338 +#define HIF_RX_DMA_STATUS      (HIF_BASE_ADDR + 0x4c)
4339 +#define HIF_INT_COAL           (HIF_BASE_ADDR + 0x50)
4340 +
4341 +/*HIF_INT_SRC/ HIF_INT_ENABLE control bits */
4342 +#define HIF_INT                        (1 << 0)
4343 +#define HIF_RXBD_INT                   (1 << 1)
4344 +#define HIF_RXPKT_INT                  (1 << 2)
4345 +#define HIF_TXBD_INT                   (1 << 3)
4346 +#define HIF_TXPKT_INT                  (1 << 4)
4347 +
4348 +/*HIF_TX_CTRL bits */
4349 +#define HIF_CTRL_DMA_EN                        (1<<0)
4350 +#define HIF_CTRL_BDP_POLL_CTRL_EN      (1<<1)
4351 +#define HIF_CTRL_BDP_CH_START_WSTB     (1<<2)
4352 +
4353 +/*HIF_INT_ENABLE bits */
4354 +#define HIF_INT_EN             (1 << 0)
4355 +#define HIF_RXBD_INT_EN                (1 << 1)
4356 +#define HIF_RXPKT_INT_EN       (1 << 2)
4357 +#define HIF_TXBD_INT_EN                (1 << 3)
4358 +#define HIF_TXPKT_INT_EN       (1 << 4)
4359 +
4360 +/*HIF_POLL_CTRL bits*/
4361 +#define HIF_RX_POLL_CTRL_CYCLE 0x0400
4362 +#define HIF_TX_POLL_CTRL_CYCLE 0x0400
4363 +
4364 +/*Buffer descriptor control bits */
4365 +#define BD_CTRL_BUFLEN_MASK    (0xffff)
4366 +#define BD_BUF_LEN(x)          (x & BD_CTRL_BUFLEN_MASK)
4367 +#define BD_CTRL_CBD_INT_EN     (1 << 16)
4368 +#define BD_CTRL_PKT_INT_EN     (1 << 17)
4369 +#define BD_CTRL_LIFM           (1 << 18)
4370 +#define BD_CTRL_LAST_BD                (1 << 19)
4371 +#define BD_CTRL_DIR            (1 << 20)
4372 +#define BD_CTRL_PKT_XFER       (1 << 24)
4373 +#define BD_CTRL_DESC_EN                (1 << 31)
4374 +#define BD_CTRL_PARSE_DISABLE  (1 << 25)
4375 +#define BD_CTRL_BRFETCH_DISABLE        (1 << 26)
4376 +#define BD_CTRL_RTFETCH_DISABLE        (1 << 27)
4377 +
4378 +#endif /* _HIF_H_ */
4379 diff --git a/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
4380 new file mode 100644
4381 index 0000000..93cb946
4382 --- /dev/null
4383 +++ b/drivers/net/pfe_eth/pfe/cbus/hif_nocpy.h
4384 @@ -0,0 +1,33 @@
4385 +#ifndef _HIF_NOCPY_H_
4386 +#define _HIF_NOCPY_H_
4387 +
4388 +#define HIF_NOCPY_VERSION              (HIF_NOCPY_BASE_ADDR + 0x00)
4389 +#define HIF_NOCPY_TX_CTRL              (HIF_NOCPY_BASE_ADDR + 0x04)
4390 +#define HIF_NOCPY_TX_CURR_BD_ADDR      (HIF_NOCPY_BASE_ADDR + 0x08)
4391 +#define HIF_NOCPY_TX_ALLOC             (HIF_NOCPY_BASE_ADDR + 0x0c)
4392 +#define HIF_NOCPY_TX_BDP_ADDR          (HIF_NOCPY_BASE_ADDR + 0x10)
4393 +#define HIF_NOCPY_TX_STATUS            (HIF_NOCPY_BASE_ADDR + 0x14)
4394 +#define HIF_NOCPY_RX_CTRL              (HIF_NOCPY_BASE_ADDR + 0x20)
4395 +#define HIF_NOCPY_RX_BDP_ADDR          (HIF_NOCPY_BASE_ADDR + 0x24)
4396 +#define HIF_NOCPY_RX_STATUS            (HIF_NOCPY_BASE_ADDR + 0x30)
4397 +#define HIF_NOCPY_INT_SRC              (HIF_NOCPY_BASE_ADDR + 0x34)
4398 +#define HIF_NOCPY_INT_ENABLE           (HIF_NOCPY_BASE_ADDR + 0x38)
4399 +#define HIF_NOCPY_POLL_CTRL            (HIF_NOCPY_BASE_ADDR + 0x3c)
4400 +#define HIF_NOCPY_RX_CURR_BD_ADDR      (HIF_NOCPY_BASE_ADDR + 0x40)
4401 +#define HIF_NOCPY_RX_ALLOC             (HIF_NOCPY_BASE_ADDR + 0x44)
4402 +#define HIF_NOCPY_TX_DMA_STATUS                (HIF_NOCPY_BASE_ADDR + 0x48)
4403 +#define HIF_NOCPY_RX_DMA_STATUS                (HIF_NOCPY_BASE_ADDR + 0x4c)
4404 +#define HIF_NOCPY_RX_INQ0_PKTPTR       (HIF_NOCPY_BASE_ADDR + 0x50)
4405 +#define HIF_NOCPY_RX_INQ1_PKTPTR       (HIF_NOCPY_BASE_ADDR + 0x54)
4406 +#define HIF_NOCPY_TX_PORT_NO           (HIF_NOCPY_BASE_ADDR + 0x60)
4407 +#define HIF_NOCPY_LMEM_ALLOC_ADDR      (HIF_NOCPY_BASE_ADDR + 0x64)
4408 +#define HIF_NOCPY_CLASS_ADDR           (HIF_NOCPY_BASE_ADDR + 0x68)
4409 +#define HIF_NOCPY_TMU_PORT0_ADDR       (HIF_NOCPY_BASE_ADDR + 0x70)
4410 +#define HIF_NOCPY_TMU_PORT1_ADDR       (HIF_NOCPY_BASE_ADDR + 0x74)
4411 +#define HIF_NOCPY_TMU_PORT2_ADDR       (HIF_NOCPY_BASE_ADDR + 0x7c)
4412 +#define HIF_NOCPY_TMU_PORT3_ADDR       (HIF_NOCPY_BASE_ADDR + 0x80)
4413 +#define HIF_NOCPY_TMU_PORT4_ADDR       (HIF_NOCPY_BASE_ADDR + 0x84)
4414 +#define HIF_NOCPY_INT_COAL             (HIF_NOCPY_BASE_ADDR + 0x90)
4415 +
4416 +
4417 +#endif /* _HIF_NOCPY_H_ */
4418 diff --git a/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
4419 new file mode 100644
4420 index 0000000..cbcbb1f
4421 --- /dev/null
4422 +++ b/drivers/net/pfe_eth/pfe/cbus/tmu_csr.h
4423 @@ -0,0 +1,102 @@
4424 +#ifndef _TMU_CSR_H_
4425 +#define _TMU_CSR_H_
4426 +
4427 +#define TMU_VERSION                    (TMU_CSR_BASE_ADDR + 0x000)
4428 +#define TMU_INQ_WATERMARK              (TMU_CSR_BASE_ADDR + 0x004)
4429 +#define TMU_PHY_INQ_PKTPTR             (TMU_CSR_BASE_ADDR + 0x008)
4430 +#define TMU_PHY_INQ_PKTINFO            (TMU_CSR_BASE_ADDR + 0x00c)
4431 +#define TMU_PHY_INQ_FIFO_CNT           (TMU_CSR_BASE_ADDR + 0x010)
4432 +#define TMU_SYS_GENERIC_CONTROL                (TMU_CSR_BASE_ADDR + 0x014)
4433 +#define TMU_SYS_GENERIC_STATUS         (TMU_CSR_BASE_ADDR + 0x018)
4434 +#define TMU_SYS_GEN_CON0               (TMU_CSR_BASE_ADDR + 0x01c)
4435 +#define TMU_SYS_GEN_CON1               (TMU_CSR_BASE_ADDR + 0x020)
4436 +#define TMU_SYS_GEN_CON2               (TMU_CSR_BASE_ADDR + 0x024)
4437 +#define TMU_SYS_GEN_CON3               (TMU_CSR_BASE_ADDR + 0x028)
4438 +#define TMU_SYS_GEN_CON4               (TMU_CSR_BASE_ADDR + 0x02c)
4439 +#define TMU_TEQ_DISABLE_DROPCHK                (TMU_CSR_BASE_ADDR + 0x030)
4440 +#define TMU_TEQ_CTRL                   (TMU_CSR_BASE_ADDR + 0x034)
4441 +#define TMU_TEQ_QCFG                   (TMU_CSR_BASE_ADDR + 0x038)
4442 +#define TMU_TEQ_DROP_STAT              (TMU_CSR_BASE_ADDR + 0x03c)
4443 +#define TMU_TEQ_QAVG                   (TMU_CSR_BASE_ADDR + 0x040)
4444 +#define TMU_TEQ_WREG_PROB              (TMU_CSR_BASE_ADDR + 0x044)
4445 +#define TMU_TEQ_TRANS_STAT             (TMU_CSR_BASE_ADDR + 0x048)
4446 +#define TMU_TEQ_HW_PROB_CFG0           (TMU_CSR_BASE_ADDR + 0x04c)
4447 +#define TMU_TEQ_HW_PROB_CFG1           (TMU_CSR_BASE_ADDR + 0x050)
4448 +#define TMU_TEQ_HW_PROB_CFG2           (TMU_CSR_BASE_ADDR + 0x054)
4449 +#define TMU_TEQ_HW_PROB_CFG3           (TMU_CSR_BASE_ADDR + 0x058)
4450 +#define TMU_TEQ_HW_PROB_CFG4           (TMU_CSR_BASE_ADDR + 0x05c)
4451 +#define TMU_TEQ_HW_PROB_CFG5           (TMU_CSR_BASE_ADDR + 0x060)
4452 +#define TMU_TEQ_HW_PROB_CFG6           (TMU_CSR_BASE_ADDR + 0x064)
4453 +#define TMU_TEQ_HW_PROB_CFG7           (TMU_CSR_BASE_ADDR + 0x068)
4454 +#define TMU_TEQ_HW_PROB_CFG8           (TMU_CSR_BASE_ADDR + 0x06c)
4455 +#define TMU_TEQ_HW_PROB_CFG9           (TMU_CSR_BASE_ADDR + 0x070)
4456 +#define TMU_TEQ_HW_PROB_CFG10          (TMU_CSR_BASE_ADDR + 0x074)
4457 +#define TMU_TEQ_HW_PROB_CFG11          (TMU_CSR_BASE_ADDR + 0x078)
4458 +#define TMU_TEQ_HW_PROB_CFG12          (TMU_CSR_BASE_ADDR + 0x07c)
4459 +#define TMU_TEQ_HW_PROB_CFG13          (TMU_CSR_BASE_ADDR + 0x080)
4460 +#define TMU_TEQ_HW_PROB_CFG14          (TMU_CSR_BASE_ADDR + 0x084)
4461 +#define TMU_TEQ_HW_PROB_CFG15          (TMU_CSR_BASE_ADDR + 0x088)
4462 +#define TMU_TEQ_HW_PROB_CFG16          (TMU_CSR_BASE_ADDR + 0x08c)
4463 +#define TMU_TEQ_HW_PROB_CFG17          (TMU_CSR_BASE_ADDR + 0x090)
4464 +#define TMU_TEQ_HW_PROB_CFG18          (TMU_CSR_BASE_ADDR + 0x094)
4465 +#define TMU_TEQ_HW_PROB_CFG19          (TMU_CSR_BASE_ADDR + 0x098)
4466 +#define TMU_TEQ_HW_PROB_CFG20          (TMU_CSR_BASE_ADDR + 0x09c)
4467 +#define TMU_TEQ_HW_PROB_CFG21          (TMU_CSR_BASE_ADDR + 0x0a0)
4468 +#define TMU_TEQ_HW_PROB_CFG22          (TMU_CSR_BASE_ADDR + 0x0a4)
4469 +#define TMU_TEQ_HW_PROB_CFG23          (TMU_CSR_BASE_ADDR + 0x0a8)
4470 +#define TMU_TEQ_HW_PROB_CFG24          (TMU_CSR_BASE_ADDR + 0x0ac)
4471 +#define TMU_TEQ_HW_PROB_CFG25          (TMU_CSR_BASE_ADDR + 0x0b0)
4472 +#define TMU_TDQ_IIFG_CFG               (TMU_CSR_BASE_ADDR + 0x0b4)
4473 +#define TMU_TDQ0_SCH_CTRL              (TMU_CSR_BASE_ADDR + 0x0b8)     /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY0 */
4474 +#define TMU_LLM_CTRL                   (TMU_CSR_BASE_ADDR + 0x0bc)
4475 +#define TMU_LLM_BASE_ADDR              (TMU_CSR_BASE_ADDR + 0x0c0)
4476 +#define TMU_LLM_QUE_LEN                        (TMU_CSR_BASE_ADDR + 0x0c4)
4477 +#define TMU_LLM_QUE_HEADPTR            (TMU_CSR_BASE_ADDR + 0x0c8)
4478 +#define TMU_LLM_QUE_TAILPTR            (TMU_CSR_BASE_ADDR + 0x0cc)
4479 +#define TMU_LLM_QUE_DROPCNT            (TMU_CSR_BASE_ADDR + 0x0d0)
4480 +#define TMU_INT_EN                     (TMU_CSR_BASE_ADDR + 0x0d4)
4481 +#define TMU_INT_SRC                    (TMU_CSR_BASE_ADDR + 0x0d8)
4482 +#define TMU_INQ_STAT                   (TMU_CSR_BASE_ADDR + 0x0dc)
4483 +#define TMU_CTRL                       (TMU_CSR_BASE_ADDR + 0x0e0)
4484 +
4485 +#define TMU_MEM_ACCESS_ADDR            (TMU_CSR_BASE_ADDR + 0x0e4)     /**< [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal memory Write [27:24] Byte Enables of the Internal memory access [23:0] Address of the internal memory. This address is used to access both the PM and DM of all the PE's */
4486 +#define TMU_MEM_ACCESS_WDATA           (TMU_CSR_BASE_ADDR + 0x0e8)     /**< Internal Memory Access Write Data */
4487 +#define TMU_MEM_ACCESS_RDATA           (TMU_CSR_BASE_ADDR + 0x0ec)     /**< Internal Memory Access Read Data. The commands are blocked at the mem_access only */
4488 +
4489 +#define TMU_PHY0_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x0f0)     /**< [31:0] PHY0 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
4490 +#define TMU_PHY1_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x0f4)     /**< [31:0] PHY1 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
4491 +#define TMU_PHY2_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x0f8)     /**< [31:0] PHY2 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
4492 +#define TMU_PHY3_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x0fc)     /**< [31:0] PHY3 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
4493 +#define TMU_BMU_INQ_ADDR               (TMU_CSR_BASE_ADDR + 0x100)
4494 +#define TMU_TX_CTRL                    (TMU_CSR_BASE_ADDR + 0x104)
4495 +
4496 +#define TMU_BUS_ACCESS_WDATA           (TMU_CSR_BASE_ADDR + 0x108)
4497 +#define TMU_BUS_ACCESS                 (TMU_CSR_BASE_ADDR + 0x10c)
4498 +#define TMU_BUS_ACCESS_RDATA           (TMU_CSR_BASE_ADDR + 0x110)
4499 +
4500 +#define TMU_PE_SYS_CLK_RATIO           (TMU_CSR_BASE_ADDR + 0x114)
4501 +#define TMU_PE_STATUS                  (TMU_CSR_BASE_ADDR + 0x118)
4502 +#define TMU_TEQ_MAX_THRESHOLD          (TMU_CSR_BASE_ADDR + 0x11c)
4503 +#define TMU_PHY4_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x134)     /**< [31:0] PHY4 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
4504 +#define TMU_TDQ1_SCH_CTRL              (TMU_CSR_BASE_ADDR + 0x138)     /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY1 */
4505 +#define TMU_TDQ2_SCH_CTRL              (TMU_CSR_BASE_ADDR + 0x13c)     /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY2 */
4506 +#define TMU_TDQ3_SCH_CTRL              (TMU_CSR_BASE_ADDR + 0x140)     /**< [9:0] Scheduler Enable for each of the scheduler in the TDQ. This is a global Enable for all schedulers in PHY3 */
4507 +#define TMU_BMU_BUF_SIZE               (TMU_CSR_BASE_ADDR + 0x144)
4508 +#define TMU_PHY5_INQ_ADDR              (TMU_CSR_BASE_ADDR + 0x148)     /**< [31:0] PHY5 in queue address (must be initialized with one of the xxx_INQ_PKTPTR cbus addresses) */
4509 +
4510 +#define SW_RESET       (1 << 0)        /**< Global software reset */
4511 +#define INQ_RESET      (1 << 2)
4512 +#define TEQ_RESET      (1 << 3)
4513 +#define TDQ_RESET      (1 << 4)
4514 +#define PE_RESET       (1 << 5)
4515 +#define MEM_INIT       (1 << 6)
4516 +#define MEM_INIT_DONE  (1 << 7)
4517 +#define LLM_INIT       (1 << 8)
4518 +#define LLM_INIT_DONE  (1 << 9)
4519 +
4520 +typedef struct {
4521 +       u32 llm_base_addr;
4522 +       u32 llm_queue_len;
4523 +} TMU_CFG;
4524 +
4525 +#endif /* _TMU_CSR_H_ */
4526 diff --git a/drivers/net/pfe_eth/pfe/cbus/util_csr.h b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
4527 new file mode 100644
4528 index 0000000..d67e849
4529 --- /dev/null
4530 +++ b/drivers/net/pfe_eth/pfe/cbus/util_csr.h
4531 @@ -0,0 +1,43 @@
4532 +#ifndef _UTIL_CSR_H_
4533 +#define _UTIL_CSR_H_
4534 +
4535 +#define UTIL_VERSION                   (UTIL_CSR_BASE_ADDR + 0x000)
4536 +#define UTIL_TX_CTRL                   (UTIL_CSR_BASE_ADDR + 0x004)
4537 +#define UTIL_INQ_PKTPTR                        (UTIL_CSR_BASE_ADDR + 0x010)
4538 +
4539 +#define UTIL_HDR_SIZE                  (UTIL_CSR_BASE_ADDR + 0x014)
4540 +
4541 +#define UTIL_PE0_QB_DM_ADDR0           (UTIL_CSR_BASE_ADDR + 0x020)
4542 +#define UTIL_PE0_QB_DM_ADDR1           (UTIL_CSR_BASE_ADDR + 0x024)
4543 +#define UTIL_PE0_RO_DM_ADDR0           (UTIL_CSR_BASE_ADDR + 0x060)
4544 +#define UTIL_PE0_RO_DM_ADDR1           (UTIL_CSR_BASE_ADDR + 0x064)
4545 +
4546 +#define UTIL_MEM_ACCESS_ADDR           (UTIL_CSR_BASE_ADDR + 0x100)
4547 +#define UTIL_MEM_ACCESS_WDATA          (UTIL_CSR_BASE_ADDR + 0x104)
4548 +#define UTIL_MEM_ACCESS_RDATA          (UTIL_CSR_BASE_ADDR + 0x108)
4549 +
4550 +#define UTIL_TM_INQ_ADDR               (UTIL_CSR_BASE_ADDR + 0x114)
4551 +#define UTIL_PE_STATUS                 (UTIL_CSR_BASE_ADDR + 0x118)
4552 +
4553 +#define UTIL_PE_SYS_CLK_RATIO          (UTIL_CSR_BASE_ADDR + 0x200)
4554 +#define UTIL_AFULL_THRES               (UTIL_CSR_BASE_ADDR + 0x204)
4555 +#define UTIL_GAP_BETWEEN_READS         (UTIL_CSR_BASE_ADDR + 0x208)
4556 +#define UTIL_MAX_BUF_CNT               (UTIL_CSR_BASE_ADDR + 0x20c)
4557 +#define UTIL_TSQ_FIFO_THRES            (UTIL_CSR_BASE_ADDR + 0x210)
4558 +#define UTIL_TSQ_MAX_CNT               (UTIL_CSR_BASE_ADDR + 0x214)
4559 +#define UTIL_IRAM_DATA_0               (UTIL_CSR_BASE_ADDR + 0x218)
4560 +#define UTIL_IRAM_DATA_1               (UTIL_CSR_BASE_ADDR + 0x21c)
4561 +#define UTIL_IRAM_DATA_2               (UTIL_CSR_BASE_ADDR + 0x220)
4562 +#define UTIL_IRAM_DATA_3               (UTIL_CSR_BASE_ADDR + 0x224)
4563 +
4564 +#define UTIL_BUS_ACCESS_ADDR           (UTIL_CSR_BASE_ADDR + 0x228)
4565 +#define UTIL_BUS_ACCESS_WDATA          (UTIL_CSR_BASE_ADDR + 0x22c)
4566 +#define UTIL_BUS_ACCESS_RDATA          (UTIL_CSR_BASE_ADDR + 0x230)
4567 +
4568 +#define UTIL_INQ_AFULL_THRES           (UTIL_CSR_BASE_ADDR + 0x234)
4569 +#define UTIL_MISC_REG                  (UTIL_CSR_BASE_ADDR + 0x240)
4570 +
4571 +typedef struct {
4572 +} UTIL_CFG;
4573 +
4574 +#endif /* _UTIL_CSR_H_ */
4575 diff --git a/drivers/net/pfe_eth/pfe/class.h b/drivers/net/pfe_eth/pfe/class.h
4576 new file mode 100644
4577 index 0000000..33ad826
4578 --- /dev/null
4579 +++ b/drivers/net/pfe_eth/pfe/class.h
4580 @@ -0,0 +1,142 @@
4581 +#ifndef _CLASS_H_
4582 +#define _CLASS_H_
4583 +
4584 +#define CLASS_DMEM_BASE_ADDR   0x00000000
4585 +#define CLASS_DMEM_SIZE                0x2000
4586 +#define CLASS_DMEM_END         (CLASS_DMEM_BASE_ADDR + CLASS_DMEM_SIZE)
4587 +#define CLASS_PMEM_BASE_ADDR   0x00010000
4588 +
4589 +#define CBUS_BASE_ADDR         0xc0000000
4590 +#define CLASS_APB_BASE_ADDR    0xc1000000
4591 +#define CLASS_AHB1_BASE_ADDR   0xc2000000
4592 +#define CLASS_AHB2_BASE_ADDR   0xc3000000
4593 +
4594 +#include "cbus.h"
4595 +
4596 +#define GPT_BASE_ADDR          (CLASS_APB_BASE_ADDR + 0x00000)
4597 +#define UART_BASE_ADDR         (CLASS_APB_BASE_ADDR + 0x10000)
4598 +#define PERG_BASE_ADDR         (CLASS_APB_BASE_ADDR + 0x20000)
4599 +#define EFET_BASE_ADDR         (CLASS_APB_BASE_ADDR + 0x40000)
4600 +
4601 +#define MAC_HASH_BASE_ADDR     (CLASS_AHB1_BASE_ADDR + 0x30000)
4602 +#define VLAN_HASH_BASE_ADDR    (CLASS_AHB1_BASE_ADDR + 0x50000)
4603 +
4604 +#define PE_LMEM_BASE_ADDR      (CLASS_AHB2_BASE_ADDR + 0x10000)
4605 +#define PE_LMEM_SIZE           0x8000
4606 +#define PE_LMEM_END            (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
4607 +#define CCU_BASE_ADDR          (CLASS_AHB2_BASE_ADDR + 0x20000)
4608 +
4609 +#define IS_DMEM(addr, len)     (((unsigned long)(addr) >= CLASS_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= CLASS_DMEM_END))
4610 +#define IS_PE_LMEM(addr, len)  (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END))
4611 +
4612 +
4613 +#include "gpt.h"
4614 +#include "uart.h"
4615 +#include "class/perg.h"
4616 +#include "class/efet.h"
4617 +#include "class/mac_hash.h"
4618 +#include "class/vlan_hash.h"
4619 +#include "class/ccu.h"
4620 +
4621 +
4622 +#define CLASS_MAX_PBUFFERS     4
4623 +
4624 +#define PBUF_HWPARSE_OFFSET    0x10    /* Fixed by hardware */
4625 +
4626 +#define PAYLOAD_DMEM_MAX_SIZE  (CLASS_PBUF_SIZE - CLASS_PBUF_HEADER_OFFSET - sizeof(class_rx_hdr_t))
4627 +
4628 +#define PHYPORT_0               0x0
4629 +#define PHYPORT_1               0x1
4630 +#define HOST_PORT_NO           0x3
4631 +
4632 +#define   ACT_SRC_MAC_REPLACE  (1 << (4+0))
4633 +#define   ACT_VLAN_REPLACE             (1 << (4+3))
4634 +#define   ACT_TCPCHKSUM_REPLACE        (1 << (4+2))
4635 +#define   ACT_VLAN_ADD                 (1 << (4+1))
4636 +
4637 +#define MIN_PKT_SIZE           56
4638 +
4639 +#define PARSE_ETH_TYPE         (1 << 0)
4640 +#define PARSE_VLAN_TYPE                (1 << 1)
4641 +#define PARSE_PPPOE_TYPE       (1 << 2)
4642 +#define PARSE_ARP_TYPE         (1 << 3)
4643 +#define PARSE_MCAST_TYPE       (1 << 4)
4644 +#define PARSE_IP_TYPE          (1 << 5)
4645 +#define PARSE_IPV6_TYPE                (1 << 6)
4646 +#define PARSE_IPV4_TYPE                (1 << 7)
4647 +
4648 +#define PARSE_IPX_TYPE         (1 << 9)
4649 +
4650 +#define PARSE_UDP_FLOW         (1 << 11)
4651 +#define PARSE_TCP_FLOW         (1 << 12)
4652 +#define PARSE_ICMP_FLOW                (1 << 13)
4653 +#define PARSE_IGMP_FLOW                (1 << 14)
4654 +#define PARSE_FRAG_FLOW                (1 << 15)
4655 +
4656 +#define PARSE_HIF_PKT          (1 << 23)
4657 +#define PARSE_ARC_HIT          (1 << 24)
4658 +#define PARSE_PKT_OVERFLOW     (1 << 25)
4659 +
4660 +#define PARSE_PROTO_MISMATCH   (1 << 28)
4661 +#define PARSE_L3_MISMATCH      (1 << 29)
4662 +#define PARSE_L2_MISMATCH      (1 << 30)
4663 +#define PARSE_INCOMPLETE       (1 << 31)
4664 +
4665 +
4666 +typedef struct _hwparse_t {
4667 +       u16     sid;
4668 +       u16     connid;
4669 +       u8      toevec;
4670 +       u8      pLayer2Hdr;
4671 +       u8      pLayer3Hdr;
4672 +       u8      pLayer4Hdr;
4673 +       u16     vlanid;
4674 +       u16     ifParseFlags;
4675 +       u32     parseFlags;
4676 +       u16     srcport;
4677 +       u16     dstport;
4678 +       u32     proto:8;
4679 +       u32     port:4;
4680 +       u32     hash:20;
4681 +       u64     rte_res_valid:1;
4682 +       u64     vlan_res_valid:1;
4683 +       u64     dst_res_valid:1;
4684 +       u64     src_res_valid:1;
4685 +       u64     vlan_lookup:20;
4686 +       u64     dst_lookup:20;
4687 +       u64     src_lookup:20;
4688 +} hwparse_t;
4689 +
4690 +
4691 +typedef struct {
4692 +       u32     next_ptr;       /* ptr to the start of the first DDR buffer */
4693 +       u16     length;         /* total packet length */
4694 +       u16     phyno;          /* input physical port number */
4695 +       u32     status;         /* gemac status bits */
4696 +       u32     res;            /* reserved for software usage */
4697 +} class_rx_hdr_t;
4698 +
4699 +
4700 +typedef struct {
4701 +       u8      num_cpy;        /* no of copies to send out from RO block, for each there must be a corresponding tx pre-header */
4702 +       u8      dma_len;        /* len to be DMAed to DDR mem, including all tx pre-headers */
4703 +       u16     src_addr;       /* class dmem source address, pointing to first tx pre-header */
4704 +       u32     dst_addr;       /* DDR memory destination address of first tx pre-header, must be so packet data is continuous in DDR */
4705 +       u32     res1;           /* reserved for software usage - queue number? */
4706 +       u16     res2;           /* reserved for software usage */
4707 +       u16     tsv;            /* time stamp val */
4708 +} class_tx_desc_t;
4709 +
4710 +
4711 +typedef struct {
4712 +       u8      start_data_off;         /* packet data start offset, relative to start of this tx pre-header */
4713 +       u8      start_buf_off;          /* this tx pre-header start offset, relative to start of DDR buffer */
4714 +       u16     pkt_length;             /* total packet lenght */
4715 +       u8      act_phyno;              /* action phy number */
4716 +       u8      queueno;                /* queueno */
4717 +       u16     src_mac_msb;            /* indicates src_mac 47:32 */
4718 +       u32     src_mac_lsb;            /* indicates src_mac 31:0 */
4719 +       u32     vlanid;                 /* vlanid */
4720 +} class_tx_hdr_t;
4721 +
4722 +#endif /* _CLASS_H_ */
4723 diff --git a/drivers/net/pfe_eth/pfe/class/ccu.h b/drivers/net/pfe_eth/pfe/class/ccu.h
4724 new file mode 100644
4725 index 0000000..2c43d97
4726 --- /dev/null
4727 +++ b/drivers/net/pfe_eth/pfe/class/ccu.h
4728 @@ -0,0 +1,10 @@
4729 +#ifndef _CCU_H_
4730 +#define _CCU_H_
4731 +
4732 +#define CCU_ADDR       (CCU_BASE_ADDR + 0x00)
4733 +#define CCU_CNT                (CCU_BASE_ADDR + 0x04)
4734 +#define CCU_STATUS     (CCU_BASE_ADDR + 0x08)
4735 +#define CCU_VAL                (CCU_BASE_ADDR + 0x0c)
4736 +
4737 +#endif /* _CCU_H_ */
4738 +
4739 diff --git a/drivers/net/pfe_eth/pfe/class/efet.h b/drivers/net/pfe_eth/pfe/class/efet.h
4740 new file mode 100644
4741 index 0000000..4f3cc25
4742 --- /dev/null
4743 +++ b/drivers/net/pfe_eth/pfe/class/efet.h
4744 @@ -0,0 +1,21 @@
4745 +#ifndef _CLASS_EFET_H_
4746 +#define _CLASS_EFET_H_
4747 +
4748 +#define CLASS_EFET_ENTRY_ADDR          (EFET_BASE_ADDR + 0x00)
4749 +#define CLASS_EFET_ENTRY_SIZE          (EFET_BASE_ADDR + 0x04)
4750 +#define CLASS_EFET_ENTRY_DMEM_ADDR     (EFET_BASE_ADDR + 0x08)
4751 +#define CLASS_EFET_ENTRY_STATUS                (EFET_BASE_ADDR + 0x0c)
4752 +#define CLASS_EFET_ENTRY_ENDIAN                (EFET_BASE_ADDR + 0x10)
4753 +
4754 +#define CBUS2DMEM      0
4755 +#define DMEM2CBUS      1
4756 +
4757 +#define EFET2BUS_LE     (1 << 0)
4758 +#define PE2BUS_LE      (1 << 1)
4759 +
4760 +void class_efet(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir);
4761 +void class_efet_wait(void);
4762 +void class_efet_sync(u32 cbus_addr, u32 dmem_addr, u32 len, u32 dir);
4763 +
4764 +#endif /* _CLASS_EFET_H_ */
4765 +
4766 diff --git a/drivers/net/pfe_eth/pfe/class/mac_hash.h b/drivers/net/pfe_eth/pfe/class/mac_hash.h
4767 new file mode 100644
4768 index 0000000..68023b4
4769 --- /dev/null
4770 +++ b/drivers/net/pfe_eth/pfe/class/mac_hash.h
4771 @@ -0,0 +1,28 @@
4772 +#ifndef _MAC_HASH_H_
4773 +#define _MAC_HASH_H_
4774 +
4775 +#define MAC_HASH_REQ1_BASE_ADDR                (MAC_HASH_BASE_ADDR + 0x000)
4776 +#define MAC_HASH_REQ2_BASE_ADDR                (MAC_HASH_BASE_ADDR + 0x020)
4777 +#define MAC_HASH_REQ3_BASE_ADDR                (MAC_HASH_BASE_ADDR + 0x040)
4778 +#define MAC_HASH_REQ4_BASE_ADDR                (MAC_HASH_BASE_ADDR + 0x060)
4779 +#define MAC_HASH_REQ5_BASE_ADDR                (MAC_HASH_BASE_ADDR + 0x080)
4780 +#define MAC_HASH_REQ6_BASE_ADDR                (MAC_HASH_BASE_ADDR + 0x0a0)
4781 +#define MAC_HASH_REQ7_BASE_ADDR                (MAC_HASH_BASE_ADDR + 0x0c0)
4782 +#define MAC_HASH_REQ8_BASE_ADDR                (MAC_HASH_BASE_ADDR + 0x0e0)
4783 +
4784 +#define MAC_HASH_REQ_CMD(i)            (MAC_HASH_REQ##i##_BASE_ADDR + 0x000)
4785 +#define MAC_HASH_REQ_MAC1_ADDR(i)      (MAC_HASH_REQ##i##_BASE_ADDR + 0x004)
4786 +#define MAC_HASH_REQ_MAC2_ADDR(i)      (MAC_HASH_REQ##i##_BASE_ADDR + 0x008)
4787 +#define MAC_HASH_REQ_MASK1_ADDR(i)     (MAC_HASH_REQ##i##_BASE_ADDR + 0x00c)
4788 +#define MAC_HASH_REQ_MASK2_ADDR(i)     (MAC_HASH_REQ##i##_BASE_ADDR + 0x010)
4789 +#define MAC_HASH_REQ_ENTRY(i)          (MAC_HASH_REQ##i##_BASE_ADDR + 0x014)
4790 +#define MAC_HASH_REQ_STATUS(i)         (MAC_HASH_REQ##i##_BASE_ADDR + 0x018)
4791 +#define MAC_HASH_REQ_ENTRY_MAYCH(i)    (MAC_HASH_REQ##i##_BASE_ADDR + 0x01c)
4792 +
4793 +
4794 +#define MAC_HASH_FREELIST_PTR_HEAD     (MAC_HASH_BASE_ADDR + 0x100)
4795 +#define MAC_HASH_FREELIST_PTR_TAIL     (MAC_HASH_BASE_ADDR + 0x104)
4796 +#define MAC_HASH_FREELIST_ENTRIES_ADDR (MAC_HASH_BASE_ADDR + 0x108)
4797 +
4798 +#endif /* _MAC_HASH_H_ */
4799 +
4800 diff --git a/drivers/net/pfe_eth/pfe/class/perg.h b/drivers/net/pfe_eth/pfe/class/perg.h
4801 new file mode 100644
4802 index 0000000..7297171
4803 --- /dev/null
4804 +++ b/drivers/net/pfe_eth/pfe/class/perg.h
4805 @@ -0,0 +1,21 @@
4806 +#ifndef _PERG_H_
4807 +#define _PERG_H_
4808 +
4809 +#define PERG_QB_BUF_STATUS             (PERG_BASE_ADDR + 0x00)
4810 +#define PERG_RO_BUF_STATUS             (PERG_BASE_ADDR + 0x04)
4811 +#define PERG_CLR_QB_BUF_STATUS         (PERG_BASE_ADDR + 0x08)
4812 +#define PERG_SET_RO_BUF_STATUS         (PERG_BASE_ADDR + 0x0c)
4813 +#define PERG_CLR_RO_ERR_PKT            (PERG_BASE_ADDR + 0x10)
4814 +#define PERG_CLR_BMU2_ERR_PKT          (PERG_BASE_ADDR + 0x14)
4815 +
4816 +#define PERG_ID                                (PERG_BASE_ADDR + 0x18)
4817 +#define PERG_TIMER1                    (PERG_BASE_ADDR + 0x1c)
4818 +#define PERG_TIMER2                    (PERG_BASE_ADDR + 0x20)
4819 +#define PERG_BUF1                      (PERG_BASE_ADDR + 0x24)
4820 +#define PERG_BUF2                      (PERG_BASE_ADDR + 0x28)
4821 +#define PERG_HOST_GP                   (PERG_BASE_ADDR + 0x2c)
4822 +#define PERG_PE_GP                     (PERG_BASE_ADDR + 0x30)
4823 +#define PERG_INT_ENABLE                        (PERG_BASE_ADDR + 0x34)
4824 +#define PERG_INT_SRC                   (PERG_BASE_ADDR + 0x38)
4825 +
4826 +#endif /* _PERG_H_ */
4827 diff --git a/drivers/net/pfe_eth/pfe/class/vlan_hash.h b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
4828 new file mode 100644
4829 index 0000000..a54ac19
4830 --- /dev/null
4831 +++ b/drivers/net/pfe_eth/pfe/class/vlan_hash.h
4832 @@ -0,0 +1,28 @@
4833 +#ifndef _VLAN_HASH_H_
4834 +#define _VLAN_HASH_H_
4835 +
4836 +#define VLAN_HASH_REQ1_BASE_ADDR       (VLAN_HASH_BASE_ADDR + 0x000)
4837 +#define VLAN_HASH_REQ2_BASE_ADDR       (VLAN_HASH_BASE_ADDR + 0x020)
4838 +#define VLAN_HASH_REQ3_BASE_ADDR       (VLAN_HASH_BASE_ADDR + 0x040)
4839 +#define VLAN_HASH_REQ4_BASE_ADDR       (VLAN_HASH_BASE_ADDR + 0x060)
4840 +#define VLAN_HASH_REQ5_BASE_ADDR       (VLAN_HASH_BASE_ADDR + 0x080)
4841 +#define VLAN_HASH_REQ6_BASE_ADDR       (VLAN_HASH_BASE_ADDR + 0x0a0)
4842 +#define VLAN_HASH_REQ7_BASE_ADDR       (VLAN_HASH_BASE_ADDR + 0x0c0)
4843 +#define VLAN_HASH_REQ8_BASE_ADDR       (VLAN_HASH_BASE_ADDR + 0x0e0)
4844 +
4845 +#define VLAN_HASH_REQ_CMD(i)           (VLAN_HASH_REQ##i##_BASE_ADDR + 0x000)
4846 +#define VLAN_HASH_REQ_MAC1_ADDR(i)     (VLAN_HASH_REQ##i##_BASE_ADDR + 0x004)
4847 +#define VLAN_HASH_REQ_MAC2_ADDR(i)     (VLAN_HASH_REQ##i##_BASE_ADDR + 0x008)
4848 +#define VLAN_HASH_REQ_MASK1_ADDR(i)    (VLAN_HASH_REQ##i##_BASE_ADDR + 0x00c)
4849 +#define VLAN_HASH_REQ_MASK2_ADDR(i)    (VLAN_HASH_REQ##i##_BASE_ADDR + 0x010)
4850 +#define VLAN_HASH_REQ_ENTRY(i)         (VLAN_HASH_REQ##i##_BASE_ADDR + 0x014)
4851 +#define VLAN_HASH_REQ_STATUS(i)                (VLAN_HASH_REQ##i##_BASE_ADDR + 0x018)
4852 +#define VLAN_HASH_REQ_ENTRY_MAYCH(i)   (VLAN_HASH_REQ##i##_BASE_ADDR + 0x01c)
4853 +
4854 +
4855 +#define VLAN_HASH_FREELIST_PTR_HEAD    (VLAN_HASH_BASE_ADDR + 0x100)
4856 +#define VLAN_HASH_FREELIST_PTR_TAIL    (VLAN_HASH_BASE_ADDR + 0x104)
4857 +#define VLAN_HASH_FREELIST_ENTRIES_ADDR        (VLAN_HASH_BASE_ADDR + 0x108)
4858 +
4859 +#endif /* _VLAN_HASH_H_ */
4860 +
4861 diff --git a/drivers/net/pfe_eth/pfe/gpt.h b/drivers/net/pfe_eth/pfe/gpt.h
4862 new file mode 100644
4863 index 0000000..d820277
4864 --- /dev/null
4865 +++ b/drivers/net/pfe_eth/pfe/gpt.h
4866 @@ -0,0 +1,11 @@
4867 +#ifndef _GPT_H_
4868 +#define _GPT_H_
4869 +
4870 +#define GPT_VERSION             (GPT_BASE_ADDR + 0x00)
4871 +#define GPT_STATUS              (GPT_BASE_ADDR + 0x04)
4872 +#define GPT_CONFIG              (GPT_BASE_ADDR + 0x08)
4873 +#define GPT_COUNTER             (GPT_BASE_ADDR + 0x0c)
4874 +#define GPT_PERIOD              (GPT_BASE_ADDR + 0x10)
4875 +#define GPT_WIDTH               (GPT_BASE_ADDR + 0x14)
4876 +
4877 +#endif /* _GPT_H_ */
4878 diff --git a/drivers/net/pfe_eth/pfe/pe.h b/drivers/net/pfe_eth/pfe/pe.h
4879 new file mode 100644
4880 index 0000000..a3838f5
4881 --- /dev/null
4882 +++ b/drivers/net/pfe_eth/pfe/pe.h
4883 @@ -0,0 +1,147 @@
4884 +#ifndef _PE_H_
4885 +#define _PE_H_
4886 +
4887 +#include "hal.h"
4888 +
4889 +#define DDR_BASE_ADDR          0x00020000
4890 +#define DDR_END                        0x86000000 /* This includes ACP and IRAM areas */
4891 +#define IRAM_BASE_ADDR         0x83000000
4892 +
4893 +#define IS_DDR(addr, len)      (((unsigned long)(addr) >= DDR_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DDR_END))
4894 +
4895 +typedef struct {
4896 +
4897 +} ddr_rx_hdr_t;
4898 +
4899 +typedef struct {
4900 +
4901 +} lmem_rx_hdr_t;
4902 +
4903 +
4904 +typedef struct {
4905 +
4906 +} tmu_rx_hdr_t;
4907 +
4908 +typedef struct {
4909 +
4910 +} tmu_tx_hdr_t;
4911 +
4912 +typedef struct {
4913 +
4914 +} util_rx_hdr_t;
4915 +
4916 +
4917 +struct pe_sync_mailbox
4918 +{
4919 +       u32 stop;
4920 +       u32 stopped;
4921 +};
4922 +
4923 +struct pe_msg_mailbox
4924 +{
4925 +       u32 dst;
4926 +       u32 src;
4927 +       u32 len;
4928 +       u32 request;
4929 +};
4930 +
4931 +/** Basic busy loop delay function
4932 +*
4933 +* @param cycles                Number of cycles to delay (actual cpu cycles should be close to 3 x cycles)
4934 +*
4935 +*/
4936 +static inline void delay(u32 cycles)
4937 +{
4938 +       volatile int i;
4939 +
4940 +       for (i = 0; i < cycles; i++);
4941 +}
4942 +
4943 +
4944 +/** Read PE id
4945 +*
4946 +* @return      PE id (0 - 5 for CLASS-PE's, 6 - 9 for TMU-PE's, 10 for UTIL-PE)
4947 +*
4948 +*/
4949 +static inline u32 esi_get_mpid(void)
4950 +{
4951 +       u32 mpid;
4952 +
4953 +       asm ("rcsr %0, Configuration, MPID" : "=d" (mpid));
4954 +
4955 +       return mpid;
4956 +}
4957 +
4958 +/** 64bit aligned memory copy using efet.
4959 +* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
4960 +* Source, destination addresses and len must all be 64bit aligned.
4961 +* Uses efet synchronous interface to copy the data.
4962 +*
4963 +* @param dst   Destination address to write to (must be 64bit aligned)
4964 +* @param src   Source address to read from (must be 64bit aligned)
4965 +* @param len   Number of bytes to copy (must be 64bit aligned)
4966 +*
4967 +*/
4968 +void efet_memcpy64(void *dst, void *src, unsigned int len);
4969 +
4970 +
4971 +/** Aligned memory copy using efet.
4972 +* Either the source or destination address must be in DMEM, the other address can be in LMEM or DDR.
4973 +* Both the source and destination must have the same 64bit alignment, there is no restriction on length.
4974 +*
4975 +* @param dst   Destination address to write to (must have the same 64bit alignment as src)
4976 +* @param src   Source address to read from (must have the same 64bit alignment as dst)
4977 +* @param len   Number of bytes to copy
4978 +*
4979 +*/
4980 +void efet_memcpy(void *dst, void *src, unsigned int len);
4981 +
4982 +
4983 +/** 32bit aligned memory copy.
4984 +* Source and destination addresses must be 32bit aligned, there is no restriction on the length.
4985 +*
4986 +* @param dst           Destination address (must be 32bit aligned)
4987 +* @param src           Source address (must be 32bit aligned)
4988 +* @param len           Number of bytes to copy
4989 +*
4990 +*/
4991 +void memcpy_aligned32(void *dst, void *src, unsigned int len);
4992 +
4993 +/** Aligned memory copy.
4994 +* Source and destination addresses must have the same alignment
4995 +* relative to 32bit boundaries (but otherwsie may have any alignment),
4996 +* there is no restriction on the length.
4997 +*
4998 +* @param dst           Destination address
4999 +* @param src           Source address (must have same 32bit alignment as dst)
5000 +* @param len           Number of bytes to copy
5001 +*
5002 +*/
5003 +void memcpy_aligned(void *dst, void *src, unsigned int len);
5004 +
5005 +
5006 +/** Generic memory set.
5007 +* Implements a generic memory set. Not very optimal (uses byte writes for the entire range)
5008 +*
5009 +*
5010 +* @param dst           Destination address
5011 +* @param val           Value to set memory to
5012 +* @param len           Number of bytes to set
5013 +*
5014 +*/
5015 +void memset(void *dst, u8 val, unsigned int len);
5016 +
5017 +/** Generic memory copy.
5018 +* Implements generic memory copy. If source and destination have the same
5019 +* alignment memcpy_aligned() is used, otherwise, we first align the destination
5020 +* to a 32bit boundary (using byte copies) then the src, and finally use a loop
5021 +* of read, shift, write
5022 +*
5023 +* @param dst           Destination address
5024 +* @param src           Source address
5025 +* @param len           Number of bytes to copy
5026 +*
5027 +*/
5028 +void memcpy(void *dst, void *src, unsigned int len);
5029 +
5030 +#endif /* _PE_H_ */
5031 diff --git a/drivers/net/pfe_eth/pfe/pfe.h b/drivers/net/pfe_eth/pfe/pfe.h
5032 new file mode 100644
5033 index 0000000..e8e2221
5034 --- /dev/null
5035 +++ b/drivers/net/pfe_eth/pfe/pfe.h
5036 @@ -0,0 +1,250 @@
5037 +#ifndef _PFE_H_
5038 +#define _PFE_H_
5039 +
5040 +#define CLASS_DMEM_BASE_ADDR(i)        (0x00000000 | ((i) << 20))
5041 +#define CLASS_IMEM_BASE_ADDR(i)        (0x00000000 | ((i) << 20)) /* Only valid for mem access register interface */
5042 +#define CLASS_DMEM_SIZE                0x00002000
5043 +#define CLASS_IMEM_SIZE                0x00008000
5044 +
5045 +#define TMU_DMEM_BASE_ADDR(i)  (0x00000000 + ((i) << 20))
5046 +#define TMU_IMEM_BASE_ADDR(i)  (0x00000000 + ((i) << 20)) /* Only valid for mem access register interface */
5047 +#define TMU_DMEM_SIZE          0x00000800
5048 +#define TMU_IMEM_SIZE          0x00002000
5049 +
5050 +#define UTIL_DMEM_BASE_ADDR    0x00000000
5051 +#define UTIL_DMEM_SIZE         0x00002000
5052 +
5053 +#define PE_LMEM_BASE_ADDR      0xc3010000
5054 +#define PE_LMEM_SIZE           0x8000
5055 +#define PE_LMEM_END            (PE_LMEM_BASE_ADDR + PE_LMEM_SIZE)
5056 +
5057 +#define DMEM_BASE_ADDR         0x00000000
5058 +#define DMEM_SIZE              0x2000          /**< TMU has less... */
5059 +#define DMEM_END               (DMEM_BASE_ADDR + DMEM_SIZE)
5060 +
5061 +#define PMEM_BASE_ADDR         0x00010000
5062 +#define PMEM_SIZE              0x8000          /**< TMU has less... */
5063 +#define PMEM_END               (PMEM_BASE_ADDR + PMEM_SIZE)
5064 +
5065 +
5066 +/* Memory ranges check from PE point of view/memory map */
5067 +#define IS_DMEM(addr, len)     (((unsigned long)(addr) >= DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= DMEM_END))
5068 +#define IS_PMEM(addr, len)     (((unsigned long)(addr) >= PMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PMEM_END))
5069 +#define IS_PE_LMEM(addr, len)  (((unsigned long)(addr) >= PE_LMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PE_LMEM_END))
5070 +
5071 +#define IS_PFE_LMEM(addr, len) (((unsigned long)(addr) >= CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR)) && (((unsigned long)(addr) + (len)) <= CBUS_VIRT_TO_PFE(LMEM_END)))
5072 +#define IS_PHYS_DDR(addr, len) (((unsigned long)(addr) >= PFE_DDR_PHYS_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= PFE_DDR_PHYS_END))
5073 +
5074 +/* Host View Address */
5075 +extern void *cbus_base_addr;
5076 +extern void *ddr_base_addr;
5077 +#define CBUS_BASE_ADDR         cbus_base_addr
5078 +#define DDR_BASE_ADDR          ddr_base_addr
5079 +
5080 +/* PFE View Address */
5081 +#define PFE_DDR_PHYS_BASE_ADDR 0x03800000      /**< DDR physical base address as seen by PE's. */
5082 +#define PFE_DDR_PHYS_SIZE      0xC000000
5083 +#define PFE_DDR_PHYS_END       (PFE_DDR_PHYS_BASE_ADDR + PFE_DDR_PHYS_SIZE)
5084 +#define PFE_CBUS_PHYS_BASE_ADDR        0xc0000000      /**< CBUS physical base address as seen by PE's. */
5085 +
5086 +/* Host<->PFE Mapping */
5087 +#define DDR_PFE_TO_VIRT(p)     ((p ) + 0x80000000)
5088 +#define CBUS_VIRT_TO_PFE(v)    (((v) - CBUS_BASE_ADDR) + PFE_CBUS_PHYS_BASE_ADDR)
5089 +#define CBUS_PFE_TO_VIRT(p)    (((p) - PFE_CBUS_PHYS_BASE_ADDR) + CBUS_BASE_ADDR)
5090 +
5091 +#include "cbus.h"
5092 +
5093 +enum {
5094 +       CLASS0_ID = 0,
5095 +       CLASS1_ID,
5096 +       CLASS2_ID,
5097 +       CLASS3_ID,
5098 +#if !defined(CONFIG_PLATFORM_PCI)
5099 +       CLASS4_ID,
5100 +       CLASS5_ID,
5101 +#endif
5102 +#if !defined(CONFIG_TMU_DUMMY)
5103 +       TMU0_ID,
5104 +       TMU1_ID,
5105 +       TMU2_ID,
5106 +       TMU3_ID,
5107 +#else
5108 +       TMU0_ID,
5109 +#endif
5110 +#if !defined(CONFIG_UTIL_PE_DISABLED)
5111 +       UTIL_ID,
5112 +#endif
5113 +       MAX_PE
5114 +};
5115 +
5116 +#if !defined(CONFIG_PLATFORM_PCI)
5117 +#define CLASS_MASK     ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID) | (1 << CLASS4_ID) | (1 << CLASS5_ID))
5118 +#define CLASS_MAX_ID   CLASS5_ID
5119 +#else
5120 +#define CLASS_MASK      ((1 << CLASS0_ID) | (1 << CLASS1_ID) | (1 << CLASS2_ID) | (1 << CLASS3_ID))
5121 +#define CLASS_MAX_ID   CLASS3_ID
5122 +#endif
5123 +
5124 +#if !defined(CONFIG_TMU_DUMMY)
5125 +#if defined(CONFIG_LS1012A)
5126 +#define TMU_MASK       ((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU3_ID))
5127 +#else
5128 +#define TMU_MASK       ((1 << TMU0_ID) | (1 << TMU1_ID) | (1 << TMU2_ID) | (1 << TMU3_ID))
5129 +#endif
5130 +#define TMU_MAX_ID     TMU3_ID
5131 +#else
5132 +#define TMU_MASK       (1 << TMU0_ID)
5133 +#define TMU_MAX_ID     TMU0_ID
5134 +#endif
5135 +
5136 +#if !defined(CONFIG_UTIL_PE_DISABLED)
5137 +#define UTIL_MASK      (1 << UTIL_ID)
5138 +#endif
5139 +
5140 +struct pe_sync_mailbox
5141 +{
5142 +       u32 stop;
5143 +       u32 stopped;
5144 +};
5145 +
5146 +struct pe_msg_mailbox
5147 +{
5148 +       u32 dst;
5149 +       u32 src;
5150 +       u32 len;
5151 +       u32 request;
5152 +};
5153 +
5154 +/** PE information.
5155 + * Structure containing PE's specific information. It is used to create
5156 + * generic C functions common to all PE's.
5157 + * Before using the library functions this structure needs to be initialized with the different registers virtual addresses
5158 + * (according to the ARM MMU mmaping). The default initialization supports a virtual == physical mapping.
5159 + *
5160 + */
5161 +struct pe_info
5162 +{
5163 +       u32 dmem_base_addr;             /**< PE's dmem base address */
5164 +       u32 pmem_base_addr;             /**< PE's pmem base address */
5165 +       u32 pmem_size;                  /**< PE's pmem size */
5166 +
5167 +       void *mem_access_wdata;         /**< PE's _MEM_ACCESS_WDATA register address */
5168 +       void *mem_access_addr;          /**< PE's _MEM_ACCESS_ADDR register address */
5169 +       void *mem_access_rdata;         /**< PE's _MEM_ACCESS_RDATA register address */
5170 +};
5171 +
5172 +
5173 +void pe_lmem_read(u32 *dst, u32 len, u32 offset);
5174 +void pe_lmem_write(u32 *src, u32 len, u32 offset);
5175 +
5176 +void pe_dmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
5177 +void pe_pmem_memcpy_to32(int id, u32 dst, const void *src, unsigned int len);
5178 +
5179 +u32 pe_pmem_read(int id, u32 addr, u8 size);
5180 +
5181 +void pe_dmem_write(int id, u32 val, u32 addr, u8 size);
5182 +u32 pe_dmem_read(int id, u32 addr, u8 size);
5183 +void class_bus_write(u32 val, u32 addr, u8 size);
5184 +u32 class_bus_read(u32 addr, u8 size);
5185 +void util_bus_write(u32 val, u32 addr, u8 size);
5186 +u32 util_bus_read(u32 addr, u8 size);
5187 +
5188 +#define class_bus_readl(addr)                  class_bus_read(addr, 4)
5189 +#define class_bus_readw(addr)                  class_bus_read(addr, 2)
5190 +#define class_bus_readb(addr)                  class_bus_read(addr, 1)
5191 +
5192 +#define class_bus_writel(val, addr)            class_bus_write(val, addr, 4)
5193 +#define class_bus_writew(val, addr)            class_bus_write(val, addr, 2)
5194 +#define class_bus_writeb(val, addr)            class_bus_write(val, addr, 1)
5195 +
5196 +#define pe_mem_readl(id, addr)                 pe_mem_read(id, addr, 4)
5197 +#define pe_mem_readw(id, addr)                 pe_mem_read(id, addr, 2)
5198 +#define pe_mem_readb(id, addr)                 pe_mem_read(id, addr, 1)
5199 +
5200 +#define pe_mem_writel(id, val, addr)           pe_mem_write(id, val, addr, 4)
5201 +#define pe_mem_writew(id, val, addr)           pe_mem_write(id, val, addr, 2)
5202 +#define pe_mem_writeb(id, val, addr)           pe_mem_write(id, val, addr, 1)
5203 +
5204 +int pe_load_elf_section(int id, const void *data, Elf32_Shdr *shdr);
5205 +
5206 +void pfe_lib_init(void *cbus_base, void *ddr_base, unsigned long ddr_phys_base);
5207 +void bmu_init(void *base, BMU_CFG *cfg);
5208 +void bmu_reset(void *base);
5209 +void bmu_enable(void *base);
5210 +void bmu_disable(void *base);
5211 +void bmu_set_config(void *base, BMU_CFG *cfg);
5212 +
5213 +#if 0
5214 +void gemac_init(void *base, void *config);
5215 +void gemac_set_speed(void *base, MAC_SPEED gem_speed);
5216 +void gemac_set_duplex(void *base, int duplex);
5217 +void gemac_set_mode(void *base, int mode);
5218 +void gemac_enable_mdio(void *base);
5219 +void gemac_disable_mdio(void *base);
5220 +void gemac_set_mdc_div(void *base, MAC_MDC_DIV gem_mdcdiv);
5221 +void gemac_enable(void *base);
5222 +void gemac_disable(void *base);
5223 +void gemac_enable_mdio(void *base);
5224 +void gemac_disable_mdio(void *base);
5225 +void gemac_reset(void *base);
5226 +void gemac_set_address(void *base, SPEC_ADDR *addr);
5227 +SPEC_ADDR gemac_get_address(void *base);
5228 +void gemac_set_laddr1(void *base, MAC_ADDR *address);
5229 +void gemac_set_laddr2(void *base, MAC_ADDR *address);
5230 +void gemac_set_laddr3(void *base, MAC_ADDR *address);
5231 +void gemac_set_laddr4(void *base, MAC_ADDR *address);
5232 +void gemac_set_laddrN(void *base, MAC_ADDR *address, unsigned int entry_index);
5233 +MAC_ADDR gem_get_laddr1(void *base);
5234 +MAC_ADDR gem_get_laddr2(void *base);
5235 +MAC_ADDR gem_get_laddr3(void *base);
5236 +MAC_ADDR gem_get_laddr4(void *base);
5237 +MAC_ADDR gem_get_laddrN(void *base, unsigned int entry_index);
5238 +void gemac_set_config(void *base, GEMAC_CFG *cfg);
5239 +void gemac_enable_copy_all(void *base);
5240 +void gemac_disable_copy_all(void *base);
5241 +void gemac_allow_broadcast(void *base);
5242 +void gemac_no_broadcast(void *base);
5243 +void gemac_enable_unicast(void *base);
5244 +void gemac_disable_unicast(void *base);
5245 +void gemac_enable_multicast(void *base);
5246 +void gemac_disable_multicast(void *base);
5247 +void gemac_enable_fcs_rx(void *base);
5248 +void gemac_disable_fcs_rx(void *base);
5249 +void gemac_enable_1536_rx(void *base);
5250 +void gemac_disable_1536_rx(void *base);
5251 +void gemac_enable_pause_rx(void *base);
5252 +void gemac_disable_pause_rx(void *base);
5253 +void gemac_enable_rx_checksum_offload(void *base);
5254 +void gemac_disable_rx_checksum_offload(void *base);
5255 +unsigned int * gemac_get_stats(void *base);
5256 +void gemac_set_bus_width(void *base, int width);
5257 +#endif
5258 +
5259 +void gpi_init(void *base, GPI_CFG *cfg);
5260 +void gpi_reset(void *base);
5261 +void gpi_enable(void *base);
5262 +void gpi_disable(void *base);
5263 +void gpi_set_config(void *base, GPI_CFG *cfg);
5264 +
5265 +void class_init(CLASS_CFG *cfg);
5266 +void class_reset(void);
5267 +void class_enable(void);
5268 +void class_disable(void);
5269 +void class_set_config(CLASS_CFG *cfg);
5270 +
5271 +void tmu_init(TMU_CFG *cfg);
5272 +void tmu_enable(u32 pe_mask);
5273 +void tmu_disable(u32 pe_mask);
5274 +
5275 +void util_init(UTIL_CFG *cfg);
5276 +void util_reset(void);
5277 +void util_enable(void);
5278 +void util_disable(void);
5279 +
5280 +void hif_init(void);
5281 +void hif_tx_enable(void);
5282 +void hif_tx_disable(void);
5283 +void hif_rx_enable(void);
5284 +void hif_rx_disable(void);
5285 +
5286 +#endif /* _PFE_H_ */
5287 diff --git a/drivers/net/pfe_eth/pfe/tmu.h b/drivers/net/pfe_eth/pfe/tmu.h
5288 new file mode 100644
5289 index 0000000..12eaf12
5290 --- /dev/null
5291 +++ b/drivers/net/pfe_eth/pfe/tmu.h
5292 @@ -0,0 +1,48 @@
5293 +#ifndef _TMU_H_
5294 +#define _TMU_H_
5295 +
5296 +#define TMU_DMEM_BASE_ADDR     0x00000000
5297 +#define TMU_PMEM_BASE_ADDR     0x00010000
5298 +
5299 +
5300 +#define CBUS_BASE_ADDR         0xc0000000
5301 +#define TMU_APB_BASE_ADDR      0xc1000000
5302 +
5303 +#include "cbus.h"
5304 +
5305 +#define GPT_BASE_ADDR          (TMU_APB_BASE_ADDR + 0x00000)
5306 +#define UART_BASE_ADDR         (TMU_APB_BASE_ADDR + 0x10000)
5307 +
5308 +
5309 +#define SHAPER0_BASE_ADDR      (TMU_APB_BASE_ADDR + 0x020000)
5310 +#define SHAPER1_BASE_ADDR      (TMU_APB_BASE_ADDR + 0x030000)
5311 +#define SHAPER2_BASE_ADDR      (TMU_APB_BASE_ADDR + 0x040000)
5312 +#define SHAPER3_BASE_ADDR      (TMU_APB_BASE_ADDR + 0x050000)
5313 +#define SHAPER4_BASE_ADDR      (TMU_APB_BASE_ADDR + 0x060000)
5314 +#define SHAPER5_BASE_ADDR      (TMU_APB_BASE_ADDR + 0x070000)
5315 +#define SHAPER6_BASE_ADDR      (TMU_APB_BASE_ADDR + 0x080000)
5316 +#define SHAPER7_BASE_ADDR      (TMU_APB_BASE_ADDR + 0x090000)
5317 +#define SHAPER8_BASE_ADDR      (TMU_APB_BASE_ADDR + 0x0a0000)
5318 +#define SHAPER9_BASE_ADDR      (TMU_APB_BASE_ADDR + 0x0b0000)
5319 +
5320 +#define SCHED0_BASE_ADDR       (TMU_APB_BASE_ADDR + 0x1c0000)
5321 +#define SCHED1_BASE_ADDR       (TMU_APB_BASE_ADDR + 0x1d0000)
5322 +#define SCHED2_BASE_ADDR       (TMU_APB_BASE_ADDR + 0x1e0000)
5323 +#define SCHED3_BASE_ADDR       (TMU_APB_BASE_ADDR + 0x1f0000)
5324 +#define SCHED4_BASE_ADDR       (TMU_APB_BASE_ADDR + 0x200000)
5325 +#define SCHED5_BASE_ADDR       (TMU_APB_BASE_ADDR + 0x210000)
5326 +#define SCHED6_BASE_ADDR       (TMU_APB_BASE_ADDR + 0x220000)
5327 +#define SCHED7_BASE_ADDR       (TMU_APB_BASE_ADDR + 0x230000)
5328 +
5329 +
5330 +#define PHY_QUEUE_BASE_ADDR    (TMU_APB_BASE_ADDR + 0x260000)
5331 +#define SHAPER_STATUS          (TMU_APB_BASE_ADDR + 0x270000) /**< [9:0] bitmask of shapers that have positive credit */
5332 +
5333 +
5334 +#include "gpt.h"
5335 +#include "uart.h"
5336 +#include "tmu/shaper.h"
5337 +#include "tmu/sched.h"
5338 +#include "tmu/phy_queue.h"
5339 +
5340 +#endif /* _TMU_H_ */
5341 diff --git a/drivers/net/pfe_eth/pfe/tmu/phy_queue.h b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
5342 new file mode 100644
5343 index 0000000..9eef9a9
5344 --- /dev/null
5345 +++ b/drivers/net/pfe_eth/pfe/tmu/phy_queue.h
5346 @@ -0,0 +1,31 @@
5347 +#ifndef _PHY_QUEUE_H_
5348 +#define _PHY_QUEUE_H_
5349 +
5350 +#define PHY_QUEUE_SHAPER_STATUS        (PHY_QUEUE_BASE_ADDR + 0x00)    /**< [28:19] same as SHAPER_STATUS, [18:3] same as QUEUE_STATUS, [2:0] must be zero before a new packet may be dequeued */
5351 +#define QUEUE_STATUS           (PHY_QUEUE_BASE_ADDR + 0x04)    /**< [15:0] bit mask of input queues with pending packets */
5352 +
5353 +#define QUEUE0_PKT_LEN         (PHY_QUEUE_BASE_ADDR + 0x08)
5354 +#define QUEUE1_PKT_LEN         (PHY_QUEUE_BASE_ADDR + 0x0c)
5355 +#define QUEUE2_PKT_LEN         (PHY_QUEUE_BASE_ADDR + 0x10)
5356 +#define QUEUE3_PKT_LEN         (PHY_QUEUE_BASE_ADDR + 0x14)
5357 +#define QUEUE4_PKT_LEN         (PHY_QUEUE_BASE_ADDR + 0x18)
5358 +#define QUEUE5_PKT_LEN         (PHY_QUEUE_BASE_ADDR + 0x1c)
5359 +#define QUEUE6_PKT_LEN         (PHY_QUEUE_BASE_ADDR + 0x20)
5360 +#define QUEUE7_PKT_LEN         (PHY_QUEUE_BASE_ADDR + 0x24)
5361 +#define QUEUE8_PKT_LEN         (PHY_QUEUE_BASE_ADDR + 0x28)
5362 +#define QUEUE9_PKT_LEN         (PHY_QUEUE_BASE_ADDR + 0x2c)
5363 +#define QUEUE10_PKT_LEN                (PHY_QUEUE_BASE_ADDR + 0x30)
5364 +#define QUEUE11_PKT_LEN                (PHY_QUEUE_BASE_ADDR + 0x34)
5365 +#define QUEUE12_PKT_LEN                (PHY_QUEUE_BASE_ADDR + 0x38)
5366 +#define QUEUE13_PKT_LEN                (PHY_QUEUE_BASE_ADDR + 0x3c)
5367 +#define QUEUE14_PKT_LEN                (PHY_QUEUE_BASE_ADDR + 0x40)
5368 +#define QUEUE15_PKT_LEN                (PHY_QUEUE_BASE_ADDR + 0x44)
5369 +#define QUEUE_RESULT0          (PHY_QUEUE_BASE_ADDR + 0x48)    /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY3), [6:0] winner input queue number */
5370 +#define QUEUE_RESULT1          (PHY_QUEUE_BASE_ADDR + 0x4c)    /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY4), [6:0] winner input queue number */
5371 +#define QUEUE_RESULT2          (PHY_QUEUE_BASE_ADDR + 0x50)    /**< [7] set to one to indicate output PHY (TMU0->PHY0, TMU1->PHY1, TMU2->PHY2, TMU3->PHY5), [6:0] winner input queue number */
5372 +#define QUEUE_GBL_PKTLEN       (PHY_QUEUE_BASE_ADDR + 0x5c)
5373 +#define QUEUE_GBL_PKTLEN_MASK  (PHY_QUEUE_BASE_ADDR + 0x60)
5374 +
5375 +
5376 +
5377 +#endif /* _PHY_QUEUE_H_ */
5378 diff --git a/drivers/net/pfe_eth/pfe/tmu/sched.h b/drivers/net/pfe_eth/pfe/tmu/sched.h
5379 new file mode 100644
5380 index 0000000..0c741cc
5381 --- /dev/null
5382 +++ b/drivers/net/pfe_eth/pfe/tmu/sched.h
5383 @@ -0,0 +1,47 @@
5384 +#ifndef _SCHED_H_
5385 +#define _SCHED_H_
5386 +
5387 +/* Offsets from SCHEDx_BASE_ADDR */
5388 +#define SCHED_CTRL                     0x00
5389 +#define SCHED_SLOT_TIME                        0x04
5390 +#define SCHED_RES                      0x08
5391 +#define SCHED_QUEUE_ALLOC0             0x0c
5392 +#define SCHED_QUEUE_ALLOC1             0x10
5393 +#define SCHED_BW                       0x14
5394 +#define SCHED_GUR_DEF_CTR              0x18
5395 +#define SCHED_AVL_CTR                  0x1c
5396 +#define SCHED_QU0_WGHT                 0x20
5397 +#define SCHED_QU1_WGHT                 0x24
5398 +#define SCHED_QU2_WGHT                 0x28
5399 +#define SCHED_QU3_WGHT                 0x2c
5400 +#define SCHED_QU4_WGHT                 0x30
5401 +#define SCHED_QU5_WGHT                 0x34
5402 +#define SCHED_QU6_WGHT                 0x38
5403 +#define SCHED_QU7_WGHT                 0x3c
5404 +#define SCHED_QUE0_DEFICIT_CNT         0x40
5405 +#define SCHED_QUE1_DEFICIT_CNT         0x44
5406 +#define SCHED_QUE2_DEFICIT_CNT         0x48
5407 +#define SCHED_QUE3_DEFICIT_CNT         0x4c
5408 +#define SCHED_QUE4_DEFICIT_CNT         0x50
5409 +#define SCHED_QUE5_DEFICIT_CNT         0x54
5410 +#define SCHED_QUE6_DEFICIT_CNT         0x58
5411 +#define SCHED_QUE7_DEFICIT_CNT         0x5c
5412 +#define SCHED_PKT_LEN                  0x60
5413 +
5414 +#define SCHED_CTRL_ALGOTYPE(x)                 (((x) & 0xf) << 0)
5415 +#define SCHED_CTRL_CALQUOTA(x)                 (((x) & 0x1) << 4)
5416 +#define SCHED_CTRL_ACTIVE_Q(x)                 (((x) & 0xff) << 8)
5417 +#define SCHED_CTRL_SHARE_BW(x)                 (((x) & 0xff) << 16)
5418 +#define SCHED_CTRL_BARROW_BW(x)        (((x) & 0xff) << 24)
5419 +
5420 +#define SCHED_QUEUE_ALLOC0_QUEUEA(x)   (((x) & 0x1f) << 0)
5421 +#define SCHED_QUEUE_ALLOC0_QUEUEB(x)   (((x) & 0x1f) << 8)
5422 +#define SCHED_QUEUE_ALLOC0_QUEUEC(x)   (((x) & 0x1f) << 16)
5423 +#define SCHED_QUEUE_ALLOC0_QUEUED(x)   (((x) & 0x1f) << 24)
5424 +
5425 +#define SCHED_QUEUE_ALLOC0_RES0(x)     (((x) & 0x7) << 5)
5426 +#define SCHED_QUEUE_ALLOC0_RES1(x)     (((x) & 0x7) << 13)
5427 +#define SCHED_QUEUE_ALLOC0_RES2(x)     (((x) & 0x7) << 21)
5428 +#define SCHED_QUEUE_ALLOC0_RES3(x)     (((x) & 0x7) << 29)
5429 +
5430 +#endif /* _SCHED_H_ */
5431 diff --git a/drivers/net/pfe_eth/pfe/tmu/shaper.h b/drivers/net/pfe_eth/pfe/tmu/shaper.h
5432 new file mode 100644
5433 index 0000000..76315f3
5434 --- /dev/null
5435 +++ b/drivers/net/pfe_eth/pfe/tmu/shaper.h
5436 @@ -0,0 +1,19 @@
5437 +#ifndef _SHAPER_H_
5438 +#define _SHAPER_H_
5439 +
5440 +/* Offsets from SHAPPERx_BASE_ADDR */
5441 +#define SHAPER_CTRL            0x00
5442 +#define SHAPER_WEIGHT          0x04
5443 +#define SHAPER_PKT_LEN         0x08
5444 +
5445 +#define SHAPER_CTRL_ENABLE(x)  (((x) & 0x1) << 0)
5446 +#define SHAPER_CTRL_QNO(x)     (((x) & 0x3f) << 1)
5447 +#define SHAPER_CTRL_CLKDIV(x)  (((x) & 0xffff) << 16)
5448 +
5449 +#define SHAPER_WEIGHT_FRACWT(x)        (((x) & 0xff) << 0)
5450 +#define SHAPER_WEIGHT_INTWT(x)                 (((x) & 0x3) << 8)
5451 +#define SHAPER_WEIGHT_MAXCREDIT(x)     (((x) & 0x3fffff) << 10)
5452 +
5453 +#define PORT_SHAPER_MASK (1 << 0)
5454 +
5455 +#endif /* _SHAPER_H_ */
5456 diff --git a/drivers/net/pfe_eth/pfe/uart.h b/drivers/net/pfe_eth/pfe/uart.h
5457 new file mode 100644
5458 index 0000000..483d446
5459 --- /dev/null
5460 +++ b/drivers/net/pfe_eth/pfe/uart.h
5461 @@ -0,0 +1,13 @@
5462 +#ifndef _UART_H_
5463 +#define _UART_H_
5464 +
5465 +#define UART_THR       (UART_BASE_ADDR + 0x00)
5466 +#define UART_IER       (UART_BASE_ADDR + 0x04)
5467 +#define UART_IIR       (UART_BASE_ADDR + 0x08)
5468 +#define UART_LCR       (UART_BASE_ADDR + 0x0c)
5469 +#define UART_MCR       (UART_BASE_ADDR + 0x10)
5470 +#define UART_LSR       (UART_BASE_ADDR + 0x14)
5471 +#define UART_MDR       (UART_BASE_ADDR + 0x18)
5472 +#define UART_SCRATCH   (UART_BASE_ADDR + 0x1c)
5473 +
5474 +#endif /* _UART_H_ */
5475 diff --git a/drivers/net/pfe_eth/pfe/util.h b/drivers/net/pfe_eth/pfe/util.h
5476 new file mode 100644
5477 index 0000000..fb2417c
5478 --- /dev/null
5479 +++ b/drivers/net/pfe_eth/pfe/util.h
5480 @@ -0,0 +1,30 @@
5481 +#ifndef _UTIL_H_
5482 +#define _UTIL_H_
5483 +
5484 +#define UTIL_DMEM_BASE_ADDR    0x00000000
5485 +#define UTIL_DMEM_SIZE         0x00002000
5486 +#define UTIL_DMEM_END          (UTIL_DMEM_BASE_ADDR + UTIL_DMEM_SIZE)
5487 +
5488 +#define IS_DMEM(addr, len)     (((unsigned long)(addr) >= UTIL_DMEM_BASE_ADDR) && (((unsigned long)(addr) + (len)) <= UTIL_DMEM_END))
5489 +
5490 +#define CBUS_BASE_ADDR         0xc0000000
5491 +#define UTIL_APB_BASE_ADDR     0xc1000000
5492 +
5493 +#include "cbus.h"
5494 +
5495 +#define GPT_BASE_ADDR          (UTIL_APB_BASE_ADDR + 0x00000)
5496 +#define UART_BASE_ADDR         (UTIL_APB_BASE_ADDR + 0x10000)
5497 +#define EAPE_BASE_ADDR         (UTIL_APB_BASE_ADDR + 0x20000)
5498 +#define INQ_BASE_ADDR          (UTIL_APB_BASE_ADDR + 0x30000)
5499 +#define EFET1_BASE_ADDR                (UTIL_APB_BASE_ADDR + 0x40000)
5500 +#define EFET2_BASE_ADDR                (UTIL_APB_BASE_ADDR + 0x50000)
5501 +#define EFET3_BASE_ADDR                (UTIL_APB_BASE_ADDR + 0x60000)
5502 +
5503 +
5504 +#include "gpt.h"
5505 +#include "uart.h"
5506 +#include "util/eape.h"
5507 +#include "util/inq.h"
5508 +#include "util/efet.h"
5509 +
5510 +#endif /* _UTIL_H_ */
5511 diff --git a/drivers/net/pfe_eth/pfe/util/eape.h b/drivers/net/pfe_eth/pfe/util/eape.h
5512 new file mode 100644
5513 index 0000000..07344dc
5514 --- /dev/null
5515 +++ b/drivers/net/pfe_eth/pfe/util/eape.h
5516 @@ -0,0 +1,10 @@
5517 +#ifndef _EAPE_H_
5518 +#define _EAPE_H_
5519 +
5520 +#define EAPE_STATUS            (EAPE_BASE_ADDR + 0x0)
5521 +#define EAPE_INT_ENABLE                (EAPE_BASE_ADDR + 0x4)
5522 +#define EAPE_INT_SRC           (EAPE_BASE_ADDR + 0x8)
5523 +#define EAPE_HOST_INT_ENABLE   (EAPE_BASE_ADDR + 0xc)
5524 +
5525 +
5526 +#endif /* _EAPE_H_ */
5527 diff --git a/drivers/net/pfe_eth/pfe/util/efet.h b/drivers/net/pfe_eth/pfe/util/efet.h
5528 new file mode 100644
5529 index 0000000..12d0310
5530 --- /dev/null
5531 +++ b/drivers/net/pfe_eth/pfe/util/efet.h
5532 @@ -0,0 +1,20 @@
5533 +#ifndef _UTIL_EFET_H_
5534 +#define _UTIL_EFET_H_
5535 +
5536 +#define EFET_ENTRY_ADDR                0x00
5537 +#define EFET_ENTRY_SIZE                0x04
5538 +#define EFET_ENTRY_DMEM_ADDR   0x08
5539 +#define EFET_ENTRY_STATUS      0x0c
5540 +#define EFET_ENTRY_ENDIAN      0x10
5541 +
5542 +#define CBUS2DMEM      0
5543 +#define DMEM2CBUS      1
5544 +
5545 +#define EFET2BUS_LE     (1 << 0)
5546 +
5547 +void util_efet(int i, u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir);
5548 +void util_efet_wait(int i);
5549 +void util_efet_sync(int i, u32 cbus_addr, u32 dmem_addr, u32 len, u8 dir);
5550 +
5551 +#endif /* _UTIL_EFET_H_ */
5552 +
5553 diff --git a/drivers/net/pfe_eth/pfe/util/inq.h b/drivers/net/pfe_eth/pfe/util/inq.h
5554 new file mode 100644
5555 index 0000000..73d1acb
5556 --- /dev/null
5557 +++ b/drivers/net/pfe_eth/pfe/util/inq.h
5558 @@ -0,0 +1,10 @@
5559 +#ifndef _INQ_H_
5560 +#define _INQ_H_
5561 +
5562 +#define INQ_HOST_GP    (INQ_BASE_ADDR + 0x00) /* FIXME what are these for ? */
5563 +#define INQ_UPE_GP     (INQ_BASE_ADDR + 0x04) /* FIXME what are these for ? */
5564 +
5565 +#define INQ_QB_PKTPTR  (INQ_BASE_ADDR + 0x08)
5566 +#define INQ_FIFO_CNT   (INQ_BASE_ADDR + 0x0c)
5567 +
5568 +#endif /* _INQ_H_ */
5569 diff --git a/drivers/net/pfe_eth/pfe_driver.c b/drivers/net/pfe_eth/pfe_driver.c
5570 new file mode 100644
5571 index 0000000..ca00e98
5572 --- /dev/null
5573 +++ b/drivers/net/pfe_eth/pfe_driver.c
5574 @@ -0,0 +1,710 @@
5575 +/*
5576 + *  (C) Copyright 2011
5577 + *  Author : Mindspeed Technologes
5578 + *
5579 + *  See file CREDITS for list of people who contributed to this
5580 + *  project.
5581 + *
5582 + *  This program is free software; you can redistribute it and/or
5583 + *  modify it under the terms of the GNU General Public License as
5584 + *  published by the Free Software Foundation; either version 2 of
5585 + *  the License, or (at your option) any later version.
5586 + *
5587 + *  This program is distributed in the hope that it will be useful,
5588 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
5589 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
5590 + *  GNU General Public License for more details.
5591 + *
5592 + *  You should have received a copy of the GNU General Public License
5593 + *  along with this program; if not, write to the Free Software
5594 + *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
5595 + *  MA 02111-1307 USA
5596 + * */
5597 +
5598 +
5599 +#include "hal.h"
5600 +#include "pfe/pfe.h"
5601 +#include "pfe_driver.h"
5602 +#include "pfe_firmware.h"
5603 +
5604 +
5605 +static struct tx_desc_s *g_tx_desc = NULL;
5606 +static struct rx_desc_s *g_rx_desc = NULL;
5607 +
5608 +#define wmb()  asm volatile("dsb st" : : : "memory")
5609 +
5610 +/** HIF Rx interface function
5611 + * Reads the rx descriptor from the current location (rxToRead).
5612 + * - If the descriptor has a valid data/pkt, then get the data pointer
5613 + * - check for the input rx phy number
5614 + * - increments the rx data pointer by pkt_head_room_size
5615 + * - decrements the data length by pkt_head_room_size
5616 + * - handover the packet to caller.
5617 + *
5618 + * @param[out] pkt_ptr Pointer to store rx packet pointer
5619 + * @param[out] phy_port Pointer to store recv phy port
5620 + *
5621 + * @return     -1 if no packet, else returns length of packet.
5622 + */
5623 +int pfe_recv(unsigned int *pkt_ptr, int *phy_port)
5624 +{
5625 +       struct rx_desc_s *rx_desc = g_rx_desc;
5626 +       struct bufDesc *bd;
5627 +       int len = -1;
5628 +       //volatile u32 ctrl;
5629 +       struct hif_header_s *hif_header;
5630 +
5631 +       bd = rx_desc->rxBase + rx_desc->rxToRead;
5632 +
5633 +       if (bd->ctrl & BD_CTRL_DESC_EN)
5634 +               return len; //No pending Rx packet
5635 +
5636 +       /* this len include hif_header(8bytes) */
5637 +       len = bd->ctrl & 0xFFFF;
5638 +
5639 +       hif_header = (struct hif_header_s *)DDR_PFE_TO_VIRT(bd->data);
5640 +
5641 +
5642 +       /* Get the recive port info from the packet */
5643 +       dprint("Pkt recv'd: Pkt ptr(%p), len(%d), gemac_port(%d) status(%08x)\n",
5644 +                               hif_header, len, hif_header->port_no, bd->status);
5645 +
5646 +#if 0
5647 +       {
5648 +               int i;
5649 +               unsigned char *p = (unsigned char *)hif_header;
5650 +               for(i=0; i < len; i++) {
5651 +                       if(!(i % 16))
5652 +                               printf("\n");
5653 +                       printf(" %02x", p[i]);
5654 +               }
5655 +               printf("\n");
5656 +       }
5657 +#endif
5658 +
5659 +       *pkt_ptr = (unsigned int )(hif_header + 1);
5660 +       *phy_port = hif_header->port_no;
5661 +       len -= sizeof(struct hif_header_s);
5662 +#if 0
5663 +       /* reset bd control field */
5664 +       ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR);
5665 +       bd->ctrl = ctrl;
5666 +       bd->status = 0;
5667 +
5668 +       rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
5669 +
5670 +       /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
5671 +        * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
5672 +        * In idle state (ie., no rx pkt), BDP will not fetch
5673 +        * the descriptor even if strobe is given(I think) */
5674 +       writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
5675 +#endif
5676 +       return len;
5677 +}
5678 +
5679 +void pfe_recv_ack(void)
5680 +{
5681 +       struct rx_desc_s *rx_desc = g_rx_desc;
5682 +       struct bufDesc *bd;
5683 +       volatile u32 ctrl;
5684 +
5685 +       bd = rx_desc->rxBase + rx_desc->rxToRead;
5686 +
5687 +       /* reset bd control field */
5688 +       ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR);
5689 +       bd->ctrl = ctrl;
5690 +       bd->status = 0;
5691 +
5692 +       rx_desc->rxToRead = (rx_desc->rxToRead + 1) & (rx_desc->rxRingSize - 1);
5693 +
5694 +       /* Give START_STROBE to BDP to fetch the descriptor __NOW__,
5695 +        * BDP need not to wait for rx_poll_cycle time to fetch the descriptor,
5696 +        * In idle state (ie., no rx pkt), BDP will not fetch
5697 +        * the descriptor even if strobe is given(I think) */
5698 +       writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
5699 +       return;
5700 +}
5701 +
5702 +
5703 +/** HIF Tx interface function
5704 + * This function sends a single packet to PFE from HIF interface.
5705 + * - No interrupt indication on tx completion.
5706 + * - After tx descriptor is updated and TX DMA is enabled.
5707 + * - To support both chipit and read c2k environment, data is copied to
5708 + *   tx buffers. After verification this copied can be avoided.
5709 + *
5710 + * @param[in] phy_port Phy port number to send out this packet
5711 + * @param[in] data     Pointer to the data
5712 + * @param[in] length   Length of the ethernet packet to be transfered.
5713 + *
5714 + * @return -1 if tx Q is full, else returns the tx location where the pkt is placed.
5715 + */
5716 +int pfe_send(int phy_port, void *data, int length)
5717 +{
5718 +       struct tx_desc_s *tx_desc = g_tx_desc;
5719 +       struct bufDesc *bd;
5720 +       struct hif_header_s hif_header;
5721 +       u8 *tx_buf_va;
5722 +       volatile u32 ctrl_word;
5723 +
5724 +       dprint("%s:pkt: %p, len: %d, txBase: %p, txToSend: %d\n", __func__,
5725 +                       data, length, tx_desc->txBase, tx_desc->txToSend);
5726 +
5727 +       bd = tx_desc->txBase + tx_desc->txToSend;
5728 +
5729 +       /* check queue-full condition */
5730 +       if (bd->ctrl & BD_CTRL_DESC_EN) {
5731 +               printf("Tx queue full\n");
5732 +               return -1;
5733 +       }
5734 +
5735 +       /* PFE checks for min pkt size */
5736 +       if (length < MIN_PKT_SIZE) {
5737 +               length = MIN_PKT_SIZE;
5738 +       }
5739 +
5740 +       tx_buf_va = (u8 *)DDR_PFE_TO_VIRT(bd->data);
5741 +       dprint("%s: tx_buf_va: %p, tx_buf_pa: %08x\n", __func__, tx_buf_va, bd->data);
5742 +
5743 +       /* Fill the gemac/phy port number to send this packet out */
5744 +       memset(&hif_header, 0 ,  sizeof(struct hif_header_s));
5745 +       hif_header.port_no = phy_port;
5746 +
5747 +       memcpy(tx_buf_va, (u8 *)&hif_header, sizeof(struct hif_header_s));
5748 +       memcpy(tx_buf_va + sizeof(struct hif_header_s), data, length);
5749 +       length += sizeof(struct hif_header_s);
5750 +
5751 +#if 0
5752 +       {
5753 +               int i;
5754 +               unsigned char *p = (unsigned char *)tx_buf_va;
5755 +               for(i=0; i < length; i++) {
5756 +                       if (!(i % 16)) printf("\n");
5757 +                       printf("%02x ", p[i]);
5758 +               }
5759 +       }
5760 +#endif
5761 +
5762 +       dprint("before0: Tx Done, status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
5763 +
5764 +       /* fill the tx desc */
5765 +       ctrl_word = (u32)(BD_CTRL_DESC_EN | BD_CTRL_LIFM | (length & 0xFFFF));
5766 +       bd->ctrl = ctrl_word;
5767 +       bd->status = 0;
5768 +
5769 +       /* NOTE: This code can be removed after verification */
5770 +#if 1 //SRAM_RETENTION_BUG
5771 +       ctrl_word = 0;
5772 +       bd->status = 0xF0;
5773 +       ctrl_word = bd->ctrl;
5774 +       //printf("0: contrl word: %08x\n", ctrl_word);
5775 +#endif
5776 +       wmb();
5777 +
5778 +       /* Indicate Tx DMA to start fetching the Tx Descriptor,
5779 +        * set START_STOBE */
5780 +       //writel((readl(HIF_TX_CTRL) | HIF_TX_BDP_CH_START_WSTB), HIF_TX_CTRL);
5781 +       //writel((readl(HIF_TX_CTRL) | (HIF_TX_DMA_EN | HIF_TX_BDP_CH_START_WSTB)), HIF_TX_CTRL);
5782 +       writel((HIF_CTRL_DMA_EN | HIF_CTRL_BDP_CH_START_WSTB), HIF_TX_CTRL);
5783 +
5784 +       udelay(100);
5785 +
5786 +       return tx_desc->txToSend;
5787 +}
5788 +
5789 +/** HIF to check the Tx done
5790 + *  This function will chceck the tx done indication of the current txToSend locations
5791 + *  if success, moves the txToSend to next location.
5792 + *
5793 + * @return -1 if TX ownership bit is not cleared by hw.
5794 +                         else on success (tx done copletion) returns zero.
5795 + */
5796 +int pfe_tx_done(void)
5797 +{
5798 +       struct tx_desc_s *tx_desc = g_tx_desc;
5799 +       struct bufDesc *bd;
5800 +       volatile u32 ctrl_word;
5801 +
5802 +       dprint("%s:txBase: %p, txToSend: %d\n", __func__, tx_desc->txBase, tx_desc->txToSend);
5803 +
5804 +       bd = tx_desc->txBase + tx_desc->txToSend;
5805 +
5806 +       /* check queue-full condition */
5807 +       ctrl_word = bd->ctrl;
5808 +       if (ctrl_word & BD_CTRL_DESC_EN)
5809 +               return -1;
5810 +
5811 +       /* reset the control field */
5812 +       bd->ctrl = 0;
5813 +       //bd->data = (u32)NULL;
5814 +       bd->status = 0;
5815 +
5816 +       dprint("Tx Done : status: %08x, ctrl: %08x\n", bd->status, bd->ctrl);
5817 +
5818 +       /* increment the txtosend index to next location */
5819 +       tx_desc->txToSend = (tx_desc->txToSend + 1) & (tx_desc->txRingSize - 1);
5820 +
5821 +       dprint("Tx next pkt location: %d\n", tx_desc->txToSend);
5822 +
5823 +       return 0;
5824 +}
5825 +#if defined CONFIG_LS1024A
5826 +/** GEMAC initialization
5827 + * Initializes the GEMAC registers.
5828 + *
5829 + * @param[in] gemac_base   Pointer to GEMAC reg base
5830 + * @param[in] mode GEMAC mode to configure (MII config)
5831 + * @param[in] speed GEMAC speed
5832 + * @param[in] duplex
5833 + */
5834 +void pfe_gemac_init(void *gemac_base, u32 mode, u32 speed, u32 duplex)
5835 +{
5836 +       GEMAC_CFG gemac_cfg  = {
5837 +               .mode = mode,
5838 +               .speed = speed,
5839 +               .duplex = duplex,
5840 +       };
5841 +
5842 +       dprint("%s: gemac_base=%p\n", __func__, gemac_base);
5843 +
5844 +       gemac_init(gemac_base, &gemac_cfg);
5845 +
5846 +       //gemac_set_loop(gemac_base, LB_NONE);
5847 +       //gemac_disable_copy_all(gemac_base);
5848 +       //gemac_disable_rx_checksum_offload(gemac_base);
5849 +
5850 +       gemac_allow_broadcast(gemac_base);
5851 +       gemac_disable_unicast(gemac_base); /* unicast hash disabled  */
5852 +       gemac_disable_multicast(gemac_base); /* multicast hash disabled */
5853 +       gemac_disable_fcs_rx(gemac_base);
5854 +       gemac_disable_1536_rx(gemac_base);
5855 +       gemac_enable_pause_rx(gemac_base);
5856 +       gemac_enable_rx_checksum_offload(gemac_base);
5857 +}
5858 +#endif
5859 +/** Helper function to dump Rx descriptors.
5860 + */
5861 +void hif_rx_desc_dump(void)
5862 +{
5863 +       struct bufDesc *bd_va;
5864 +       int i;
5865 +       struct rx_desc_s *rx_desc;
5866 +
5867 +       if (g_rx_desc == NULL) {
5868 +               printf("%s: HIF Rx desc no init \n", __func__);
5869 +               return;
5870 +       }
5871 +
5872 +       rx_desc = g_rx_desc;
5873 +       bd_va = rx_desc->rxBase;
5874 +
5875 +       printf("HIF rx desc: base_va: %p, base_pa: %08x\n", rx_desc->rxBase, rx_desc->rxBase_pa);
5876 +       for (i=0; i < rx_desc->rxRingSize; i++) {
5877 +//             printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
5878 +//                     bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
5879 +               bd_va++;
5880 +       }
5881 +}
5882 +
5883 +/** HIF Rx Desc initialization function.
5884 + */
5885 +static int hif_rx_desc_init(struct pfe *pfe)
5886 +{
5887 +       u32 ctrl;
5888 +       struct bufDesc *bd_va;
5889 +       struct bufDesc *bd_pa;
5890 +       struct rx_desc_s *rx_desc;
5891 +       u32 rx_buf_pa;
5892 +       int i;
5893 +
5894 +       /* sanity check */
5895 +       if (g_rx_desc) {
5896 +               printf("%s: HIF Rx desc re-init request\n", __func__);
5897 +               return 0;
5898 +       }
5899 +
5900 +       rx_desc = (struct rx_desc_s *)malloc(sizeof(struct rx_desc_s));
5901 +       if (rx_desc == NULL) {
5902 +               printf("%s:%d:Memory allocation failure\n", __func__, __LINE__);
5903 +               return -1;
5904 +       }
5905 +       memset(rx_desc, 0 , sizeof(struct rx_desc_s));
5906 +
5907 +       /* init: Rx ring buffer */
5908 +       rx_desc->rxRingSize = HIF_RX_DESC_NT;
5909 +
5910 +       /* NOTE: must be 64bit aligned  */
5911 +       bd_va = (struct bufDesc *)(pfe->ddr_baseaddr + RX_BD_BASEADDR);
5912 +       bd_pa = (struct bufDesc *)(pfe->ddr_phys_baseaddr + RX_BD_BASEADDR);
5913 +
5914 +       rx_desc->rxBase = bd_va;
5915 +       rx_desc->rxBase_pa = (unsigned long)bd_pa;
5916 +
5917 +       rx_buf_pa = pfe->ddr_phys_baseaddr + HIF_RX_PKT_DDR_BASEADDR;
5918 +
5919 +
5920 +       printf("%s: Rx desc base: %p, base_pa: %08x, desc_count: %d\n",
5921 +               __func__, rx_desc->rxBase, rx_desc->rxBase_pa, rx_desc->rxRingSize);
5922 +
5923 +       memset(bd_va, 0, sizeof(struct bufDesc) * rx_desc->rxRingSize);
5924 +
5925 +       ctrl = (MAX_FRAME_SIZE | BD_CTRL_DESC_EN | BD_CTRL_DIR | BD_CTRL_LIFM);
5926 +       for (i=0; i < rx_desc->rxRingSize; i++) {
5927 +               bd_va->next = (u32 )(bd_pa + 1);
5928 +               bd_va->ctrl = ctrl;
5929 +               bd_va->data = rx_buf_pa + (i * MAX_FRAME_SIZE);
5930 +//             printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
5931 +//                     bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
5932 +               bd_va++;
5933 +               bd_pa++;
5934 +       }
5935 +       --bd_va;
5936 +       bd_va->next = (u32 )rx_desc->rxBase_pa;
5937 +
5938 +       /* !!! This is a redundent information for h/w as we are also
5939 +               maintaining next address in the buffer descriptor
5940 +               Posedge: reference code does not using this bit to go back to base address */
5941 +       //bd->ctrl |= BD_CTRL_LAST_BD;
5942 +
5943 +       writel(rx_desc->rxBase_pa, HIF_RX_BDP_ADDR);
5944 +       writel((readl(HIF_RX_CTRL) | HIF_CTRL_BDP_CH_START_WSTB), HIF_RX_CTRL);
5945 +
5946 +       g_rx_desc = rx_desc;
5947 +
5948 +       return 0;
5949 +}
5950 +
5951 +/** Helper function to dump Tx Descriptors.
5952 + */
5953 +void hif_tx_desc_dump(void)
5954 +{
5955 +       struct tx_desc_s *tx_desc;
5956 +       int i;
5957 +       struct bufDesc *bd_va;
5958 +
5959 +       if (g_tx_desc == NULL) {
5960 +               printf("%s: HIF Tx desc no init \n", __func__);
5961 +               return;
5962 +       }
5963 +
5964 +       tx_desc = g_tx_desc;
5965 +       bd_va = tx_desc->txBase;
5966 +
5967 +       printf("HIF tx desc: base_va: %p, base_pa: %08x\n", tx_desc->txBase, tx_desc->txBase_pa);
5968 +       for (i=0; i < tx_desc->txRingSize; i++) {
5969 +//             printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
5970 +//                     bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
5971 +               bd_va++;
5972 +       }
5973 +}
5974 +
5975 +/** HIF Tx descriptor initialization function.
5976 + */
5977 +static int hif_tx_desc_init(struct pfe *pfe)
5978 +{
5979 +       struct bufDesc *bd_va;
5980 +       struct bufDesc *bd_pa;
5981 +       int i;
5982 +       struct tx_desc_s *tx_desc;
5983 +       u32 tx_buf_pa;
5984 +
5985 +       /* sanity check */
5986 +       if (g_tx_desc) {
5987 +               printf("%s: HIF Tx desc re-init request\n", __func__);
5988 +               return 0;
5989 +       }
5990 +
5991 +       tx_desc = (struct tx_desc_s *)malloc(sizeof(struct tx_desc_s));
5992 +       if (tx_desc == NULL) {
5993 +               printf("%s:%d:Memory allocation failure\n", __func__, __LINE__);
5994 +               return -1;
5995 +       }
5996 +       memset(tx_desc, 0 , sizeof(struct tx_desc_s));
5997 +
5998 +       /* init: Tx ring buffer */
5999 +       tx_desc->txRingSize = HIF_TX_DESC_NT;
6000 +       /* NOTE: must be 64bit aligned  */
6001 +       bd_va = (struct bufDesc *)(pfe->ddr_baseaddr + TX_BD_BASEADDR);
6002 +       bd_pa = (struct bufDesc *)(pfe->ddr_phys_baseaddr + TX_BD_BASEADDR);
6003 +
6004 +       tx_desc->txBase_pa = (unsigned long)bd_pa;
6005 +       tx_desc->txBase = bd_va;
6006 +
6007 +       printf("%s: Tx desc_base: %p, base_pa: %08x, desc_count: %d\n",
6008 +                       __func__, tx_desc->txBase, tx_desc->txBase_pa, tx_desc->txRingSize);
6009 +
6010 +       memset(bd_va, 0, sizeof(struct bufDesc) * tx_desc->txRingSize);
6011 +
6012 +       tx_buf_pa = pfe->ddr_phys_baseaddr + HIF_TX_PKT_DDR_BASEADDR;
6013 +
6014 +       for (i=0; i < tx_desc->txRingSize; i++) {
6015 +               bd_va->next = (u32 )(bd_pa + 1);
6016 +               bd_va->data = tx_buf_pa + (i * MAX_FRAME_SIZE);
6017 +//             printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
6018 +//                     bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
6019 +               bd_va++;
6020 +               bd_pa++;
6021 +       }
6022 +       --bd_va;
6023 +       bd_va->next = (u32 )tx_desc->txBase_pa;
6024 +//     printf("status: %08x, ctrl: %08x, data: %08x, next: %p\n",
6025 +//             bd_va->status, bd_va->ctrl, bd_va->data, bd_va->next);
6026 +
6027 +       /* !!! This is a redundent information for h/w as we are also
6028 +               maintaining next address in the buffer descriptor,
6029 +               Posedge: reference code does not using LAST_BD for moving back to base address */
6030 +       //bd->ctrl |= BD_CTRL_LAST_BD;
6031 +
6032 +       writel(tx_desc->txBase_pa, HIF_TX_BDP_ADDR);
6033 +
6034 +       g_tx_desc = tx_desc;
6035 +
6036 +       return 0;
6037 +}
6038 +
6039 +/** PFE/Class initialization.
6040 + */
6041 +static void pfe_class_init(struct pfe *pfe)
6042 +{
6043 +       CLASS_CFG class_cfg = {
6044 +               .route_table_baseaddr = pfe->ddr_phys_baseaddr + ROUTE_TABLE_BASEADDR,
6045 +               .route_table_hash_bits = ROUTE_TABLE_HASH_BITS,
6046 +       };
6047 +
6048 +       class_init(&class_cfg);
6049 +       printf("class init complete\n");
6050 +}
6051 +
6052 +/** PFE/TMU initialization.
6053 + */
6054 +static void pfe_tmu_init(struct pfe *pfe)
6055 +{
6056 +       TMU_CFG tmu_cfg = {
6057 +               .llm_base_addr = pfe->ddr_phys_baseaddr + TMU_LLM_BASEADDR,
6058 +               .llm_queue_len = TMU_LLM_QUEUE_LEN,
6059 +       };
6060 +
6061 +       tmu_init(&tmu_cfg);
6062 +       printf("tmu init complete\n");
6063 +}
6064 +
6065 +/** PFE/BMU (both BMU1 & BMU2) initialization.
6066 + */
6067 +static void pfe_bmu_init(struct pfe *pfe)
6068 +{
6069 +       BMU_CFG bmu1_cfg = {
6070 +               .baseaddr = CBUS_VIRT_TO_PFE(LMEM_BASE_ADDR + BMU1_LMEM_BASEADDR),
6071 +               .count = BMU1_BUF_COUNT,
6072 +               .size = BMU1_BUF_SIZE,
6073 +       };
6074 +
6075 +       BMU_CFG bmu2_cfg = {
6076 +               .baseaddr = pfe->ddr_phys_baseaddr + BMU2_DDR_BASEADDR,
6077 +               .count = BMU2_BUF_COUNT,
6078 +               .size = BMU2_BUF_SIZE,
6079 +       };
6080 +
6081 +       bmu_init(BMU1_BASE_ADDR, &bmu1_cfg);
6082 +       printf("bmu1 init: done\n");
6083 +
6084 +       bmu_init(BMU2_BASE_ADDR, &bmu2_cfg);
6085 +       printf("bmu2 init: done\n");
6086 +}
6087 +
6088 +#if !defined(CONFIG_UTIL_PE_DISABLED)
6089 +/** PFE/Util initialization function.
6090 + */
6091 +static void pfe_util_init(struct pfe *pfe)
6092 +{
6093 +       UTIL_CFG util_cfg = { };
6094 +
6095 +       util_init(&util_cfg);
6096 +       printf("util init complete\n");
6097 +}
6098 +#endif
6099 +
6100 +/** PFE/GPI initialization function.
6101 + *  - egpi1, egpi2, egpi3, hgpi
6102 + */
6103 +static void pfe_gpi_init(struct pfe *pfe)
6104 +{
6105 +       GPI_CFG egpi1_cfg = {
6106 +               .lmem_rtry_cnt = EGPI1_LMEM_RTRY_CNT,
6107 +               .tmlf_txthres = EGPI1_TMLF_TXTHRES,
6108 +               .aseq_len = EGPI1_ASEQ_LEN,
6109 +       };
6110 +
6111 +       GPI_CFG egpi2_cfg = {
6112 +               .lmem_rtry_cnt = EGPI2_LMEM_RTRY_CNT,
6113 +               .tmlf_txthres = EGPI2_TMLF_TXTHRES,
6114 +               .aseq_len = EGPI2_ASEQ_LEN,
6115 +       };
6116 +
6117 +#if 0
6118 +       GPI_CFG egpi3_cfg = {
6119 +               .lmem_rtry_cnt = EGPI3_LMEM_RTRY_CNT,
6120 +               .tmlf_txthres = EGPI3_TMLF_TXTHRES,
6121 +               .aseq_len = EGPI3_ASEQ_LEN,
6122 +       };
6123 +#endif
6124 +
6125 +       GPI_CFG hgpi_cfg = {
6126 +               .lmem_rtry_cnt = HGPI_LMEM_RTRY_CNT,
6127 +               .tmlf_txthres = HGPI_TMLF_TXTHRES,
6128 +               .aseq_len = HGPI_ASEQ_LEN,
6129 +       };
6130 +
6131 +       gpi_init(EGPI1_BASE_ADDR, &egpi1_cfg);
6132 +       printf("GPI1 init complete\n");
6133 +
6134 +   gpi_init(EGPI2_BASE_ADDR, &egpi2_cfg);
6135 +       printf("GPI2 init complete\n");
6136 +
6137 +#if 0
6138 +   gpi_init(EGPI3_BASE_ADDR, &egpi3_cfg);
6139 +#endif
6140 +
6141 +   gpi_init(HGPI_BASE_ADDR, &hgpi_cfg);
6142 +       printf("HGPI init complete\n");
6143 +}
6144 +
6145 +
6146 +/** PFE/HIF initialization function.
6147 + */
6148 +static void pfe_hif_init(struct pfe *pfe)
6149 +{
6150 +       hif_tx_disable();
6151 +       hif_rx_disable();
6152 +
6153 +       hif_tx_desc_init(pfe);
6154 +       hif_rx_desc_init(pfe);
6155 +
6156 +       hif_init();
6157 +
6158 +       hif_tx_enable();
6159 +       hif_rx_enable();
6160 +
6161 +       hif_rx_desc_dump();
6162 +       hif_tx_desc_dump();
6163 +
6164 +       printf("HIF init complete\n");
6165 +}
6166 +
6167 +/** PFE initialization
6168 + * - Firmware loading (CLASS-PE and TMU-PE)
6169 + * - BMU1 and BMU2 init
6170 + * - GEMAC init
6171 + * - GPI init
6172 + * - CLASS-PE init
6173 + * - TMU-PE init
6174 + * - HIF tx and rx descriptors init
6175 + *
6176 + * @param[in]  edev    Pointer to eth device structure.
6177 + *
6178 + * @return 0, on success.
6179 + */
6180 +static int pfe_hw_init(struct pfe *pfe)
6181 +{
6182 +
6183 +       dprint("%s: start \n", __func__);
6184 +#if defined (CONFIG_LS1012A)
6185 +       /*This clock workaround needed for LS1012 */
6186 +       writel(0x3,     CLASS_PE_SYS_CLK_RATIO);
6187 +       writel(0x3,     TMU_PE_SYS_CLK_RATIO);
6188 +       writel(0x3,     UTIL_PE_SYS_CLK_RATIO);
6189 +       udelay(10);
6190 +#endif
6191 +
6192 +       pfe_class_init(pfe);
6193 +
6194 +       pfe_tmu_init(pfe);
6195 +
6196 +       pfe_bmu_init(pfe);
6197 +
6198 +#if !defined(CONFIG_UTIL_PE_DISABLED)
6199 +       pfe_util_init(pfe);
6200 +#endif
6201 +
6202 +       pfe_gpi_init(pfe);
6203 +
6204 +       pfe_hif_init(pfe);
6205 +
6206 +       bmu_enable(BMU1_BASE_ADDR);
6207 +       printf("bmu1 enabled\n");
6208 +
6209 +       bmu_enable(BMU2_BASE_ADDR);
6210 +       printf("bmu2 enabled\n");
6211 +
6212 +       printf("%s: done\n", __func__);
6213 +
6214 +       /* NOTE: Load PE specific data (if any) */
6215 +
6216 +       return 0;
6217 +}
6218 +
6219 +
6220 +/** PFE probe function.
6221 + * - Initializes pfe_lib
6222 + * - pfe hw init
6223 + * - fw loading and enables PEs
6224 + * - should be executed once.
6225 + *
6226 + * @param[in] pfe  Pointer the pfe control block
6227 + */
6228 +int pfe_probe(struct pfe *pfe)
6229 +{
6230 +       static int init_done = 0;
6231 +
6232 +       if (init_done)
6233 +               return 0;
6234 +
6235 +       printf("cbus_baseaddr: %p, ddr_baseaddr: %p, ddr_phys_baseaddr: %08x\n",
6236 +                    pfe->cbus_baseaddr, pfe->ddr_baseaddr, (u32)pfe->ddr_phys_baseaddr);
6237 +
6238 +       pfe_lib_init(pfe->cbus_baseaddr, pfe->ddr_baseaddr, pfe->ddr_phys_baseaddr);
6239 +
6240 +
6241 +       pfe_hw_init(pfe);
6242 +
6243 +       /* Load the class,TM, Util fw
6244 +    * by now pfe is,
6245 +    * - out of reset + disabled + configured,
6246 +    * Fw loading should be done after pfe_hw_init() */
6247 +#ifdef CONFIG_CMD_PFE_START
6248 +       /* It loads firmware from DDR locations Class@0x100000 TMU@0x180000  UTIL@200000*/
6249 +       //For this firmware should be preloaded in DDR
6250 +       //pfe_firmware_init((u8 *)0x80100000, (u8 *)0x80180000, 0x80200000);
6251 +       pfe_firmware_init(NULL, NULL, NULL);
6252 +#else
6253 +       /*It loads default inbuilt sbl firmware */
6254 +       pfe_firmware_init(NULL, NULL, NULL);
6255 +#endif
6256 +
6257 +       init_done = 1;
6258 +
6259 +       return 0;
6260 +}
6261 +
6262 +
6263 +/** PFE remove function
6264 + *  - stopes PEs
6265 + *  - frees tx/rx descriptor resources
6266 + *  - should be called once.
6267 + *
6268 + * @param[in] pfe Pointer to pfe control block.
6269 + */
6270 +int pfe_remove(struct pfe *pfe)
6271 +{
6272 +       if (g_tx_desc) {
6273 +               free(g_tx_desc);
6274 +       }
6275 +
6276 +       if (g_rx_desc) {
6277 +               free(g_rx_desc);
6278 +       }
6279 +
6280 +       pfe_firmware_exit();
6281 +
6282 +       return 0;
6283 +}
6284 +
6285 diff --git a/drivers/net/pfe_eth/pfe_driver.h b/drivers/net/pfe_eth/pfe_driver.h
6286 new file mode 100644
6287 index 0000000..4d2e8b6
6288 --- /dev/null
6289 +++ b/drivers/net/pfe_eth/pfe_driver.h
6290 @@ -0,0 +1,141 @@
6291 +/*
6292 + *  (C) Copyright 2011
6293 + *  Author : Mindspeed Technologes
6294 + *
6295 + *  See file CREDITS for list of people who contributed to this
6296 + *  project.
6297 + *
6298 + *  This program is free software; you can redistribute it and/or
6299 + *  modify it under the terms of the GNU General Public License as
6300 + *  published by the Free Software Foundation; either version 2 of
6301 + *  the License, or (at your option) any later version.
6302 + *
6303 + *  This program is distributed in the hope that it will be useful,
6304 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
6305 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6306 + *  GNU General Public License for more details.
6307 + *
6308 + *  You should have received a copy of the GNU General Public License
6309 + *  along with this program; if not, write to the Free Software
6310 + *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
6311 + *  MA 02111-1307 USA
6312 + * */
6313 +
6314 +#ifndef __PFE_DRIVER_H__
6315 +#define __PFE_DRIVER_H__
6316 +
6317 +#include "hal.h"
6318 +
6319 +#include "pfe/pfe.h"
6320 +#include "pfe/cbus.h"
6321 +#include "pfe/cbus/bmu.h"
6322 +
6323 +
6324 +
6325 +typedef struct bufDesc {
6326 +       volatile u32 ctrl;
6327 +       volatile u32 status;
6328 +       volatile u32 data;
6329 +       volatile u32 next;
6330 +                // struct bufDesc *next;
6331 +}__attribute__((packed)) bufDesc_t;
6332 +
6333 +#if defined(CONFIG_PLATFORM_PCI)
6334 +#define HIF_RX_DESC_NT         4
6335 +#define        HIF_TX_DESC_NT          4
6336 +#else
6337 +#define HIF_RX_DESC_NT         64
6338 +#define        HIF_TX_DESC_NT          64
6339 +#endif
6340 +#define RX_BD_BASEADDR         (HIF_DESC_BASEADDR)
6341 +#define TX_BD_BASEADDR         (HIF_DESC_BASEADDR + HIF_TX_DESC_SIZE)
6342 +
6343 +#define MIN_PKT_SIZE                   56
6344 +#define MAX_FRAME_SIZE     2048
6345 +
6346 +
6347 +typedef struct hif_header_s {
6348 +       u8      port_no; //Carries input port no for host rx packets and output port no for tx pkts
6349 +       u8 reserved0;
6350 +       u32 reserved2;
6351 +} __attribute__((packed)) hif_header_t;
6352 +
6353 +
6354 +typedef struct rx_desc_s {
6355 +       struct bufDesc *rxBase;
6356 +       unsigned int rxBase_pa;
6357 +       int rxToRead;
6358 +       int rxRingSize;
6359 +}rx_desc_t;
6360 +
6361 +typedef struct tx_desc_s {
6362 +       struct bufDesc *txBase;
6363 +       unsigned int txBase_pa;
6364 +       int txToSend;
6365 +       int txRingSize;
6366 +}tx_desc_t;
6367 +
6368 +
6369 +/* The set of statistics registers implemented in the Cadence MAC.
6370 + * The statistics registers implemented are a subset of all the statistics
6371 + * available, but contains all the compulsory ones.
6372 + */
6373 +typedef struct gem_stats{
6374 +    u32 octets_tx_bot;      /* Lower 32-bits for number of octets tx'd */
6375 +    u32 octets_tx_top;      /* Upper 16-bits for number of octets tx'd */
6376 +    u32 frames_tx;          /* Number of frames transmitted OK */
6377 +    u32 broadcast_tx;       /* Number of broadcast frames transmitted */
6378 +    u32 multicast_tx;       /* Number of multicast frames transmitted */
6379 +    u32 pause_tx;           /* Number of pause frames transmitted. */
6380 +    u32 frame64_tx;         /* Number of 64byte frames transmitted */
6381 +    u32 frame65_127_tx;     /* Number of 65-127 byte frames transmitted */
6382 +    u32 frame128_255_tx;    /* Number of 128-255 byte frames transmitted */
6383 +    u32 frame256_511_tx;    /* Number of 256-511 byte frames transmitted */
6384 +    u32 frame512_1023_tx;   /* Number of 512-1023 byte frames transmitted */
6385 +    u32 frame1024_1518_tx;  /* Number of 1024-1518 byte frames transmitted*/
6386 +    u32 frame1519_tx;       /* Number of frames greater than 1518 bytes tx*/
6387 +    u32 tx_urun;            /* Transmit underrun errors due to DMA */
6388 +    u32 single_col;         /* Number of single collision frames */
6389 +    u32 multi_col;          /* Number of multi collision frames */
6390 +    u32 excess_col;         /* Number of excessive collision frames. */
6391 +    u32 late_col;           /* Collisions occuring after slot time */
6392 +    u32 def_tx;             /* Frames deferred due to crs */
6393 +    u32 crs_errors;         /* Errors caused by crs not being asserted. */
6394 +    u32 octets_rx_bot;      /* Lower 32-bits for number of octets rx'd */
6395 +    u32 octets_rx_top;      /* Upper 16-bits for number of octets rx'd */
6396 +    u32 frames_rx;          /* Number of frames received OK */
6397 +    u32 broadcast_rx;       /* Number of broadcast frames received */
6398 +    u32 multicast_rx;       /* Number of multicast frames received */
6399 +    u32 pause_rx;           /* Number of pause frames received. */
6400 +    u32 frame64_rx;         /* Number of 64byte frames received */
6401 +    u32 frame65_127_rx;     /* Number of 65-127 byte frames received */
6402 +    u32 frame128_255_rx;    /* Number of 128-255 byte frames received */
6403 +    u32 frame256_511_rx;    /* Number of 256-511 byte frames received */
6404 +    u32 frame512_1023_rx;   /* Number of 512-1023 byte frames received */
6405 +    u32 frame1024_1518_rx;  /* Number of 1024-1518 byte frames received*/
6406 +    u32 frame1519_rx;       /* Number of frames greater than 1518 bytes rx*/
6407 +    u32 usize_frames;       /* Frames received less than min of 64 bytes */
6408 +    u32 excess_length;      /* Number of excessive length frames rx */
6409 +    u32 jabbers;            /* Excessive length + crc or align errors. */
6410 +    u32 fcs_errors;         /* Number of frames received with crc errors */
6411 +    u32 length_check_errors;/* Number of frames with incorrect length */
6412 +    u32 rx_symbol_errors;   /* Number of times rx_er asserted during rx */
6413 +    u32 align_errors;       /* Frames received without integer no. bytes */
6414 +    u32 rx_res_errors;      /* Number of times buffers ran out during rx */
6415 +    u32 rx_orun;            /* Receive overrun errors due to DMA */
6416 +    u32 ip_cksum;           /* IP header checksum errors */
6417 +    u32 tcp_cksum;           /* TCP checksum errors */
6418 +    u32 udp_cksum;           /* UDP checksum errors */
6419 +} volatile GEM_STATS;
6420 +
6421 +
6422 +int pfe_send(int phy_port, void *data, int length);
6423 +int pfe_recv(unsigned int *pkt_ptr, int *phy_port);
6424 +void pfe_recv_ack(void);
6425 +int pfe_tx_done(void);
6426 +void pfe_gem_enable_all(void);
6427 +void pfe_gemac_init(void *gemac_base, u32 mode, u32 speed, u32 duplex);
6428 +
6429 +
6430 +#endif
6431 +
6432 diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c
6433 new file mode 100644
6434 index 0000000..40ac095
6435 --- /dev/null
6436 +++ b/drivers/net/pfe_eth/pfe_eth.c
6437 @@ -0,0 +1,521 @@
6438 +#include <common.h>
6439 +#include <config.h>
6440 +//#include <asm/arch/hardware.h>
6441 +#include <asm/byteorder.h>
6442 +#include <net.h>
6443 +#include <command.h>
6444 +#include <miiphy.h>
6445 +#include "pfe_eth.h"
6446 +
6447 +struct gemac_s gem_info[] = {
6448 +        /* PORT_0 configuration */
6449 +        {
6450 +                /* GEMAC config */
6451 +                .gemac_mode = GMII,
6452 +                .gemac_speed = SPEED_1000M,
6453 +                .gemac_duplex = DUPLEX_FULL,
6454 +
6455 +                /* phy iface */
6456 +                .phy_address = EMAC1_PHY_ADDR,
6457 +               .phy_mode = PHY_INTERFACE_MODE_SGMII,
6458 +        },
6459 +        /* PORT_1 configuration */
6460 +        {
6461 +                /* GEMAC config */
6462 +                .gemac_mode = GMII,
6463 +                .gemac_speed = SPEED_1000M,
6464 +                .gemac_duplex = DUPLEX_FULL,
6465 +
6466 +                /* phy iface */
6467 +                .phy_address = EMAC2_PHY_ADDR,
6468 +               .phy_mode = PHY_INTERFACE_MODE_RGMII,
6469 +        },
6470 +};
6471 +
6472 +#define MAX_GEMACS      2
6473 +
6474 +static struct ls1012a_eth_dev *gemac_list[MAX_GEMACS];
6475 +
6476 +/* Max MII register/address (we support) */
6477 +#define MII_REGISTER_MAX  31
6478 +#define MII_ADDRESS_MAX   31
6479 +
6480 +#define MDIO_TIMEOUT    5000
6481 +
6482 +
6483 +static void ls1012a_gemac_enable(void *gemac_base)
6484 +{
6485 +        writel(readl(gemac_base + EMAC_ECNTRL_REG) | EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
6486 +}
6487 +
6488 +static void ls1012a_gemac_dsable(void *gemac_base)
6489 +{
6490 +        writel(readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_ETHER_EN, gemac_base + EMAC_ECNTRL_REG);
6491 +}
6492 +
6493 +static void ls1012a_gemac_set_mode(void *gemac_base, u32 mode)
6494 +{
6495 +}
6496 +
6497 +static void ls1012a_gemac_set_speed(void *gemac_base, u32 speed)
6498 +{
6499 +       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
6500 +       u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED;
6501 +       u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T;
6502 +       u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) & ~(SCFG_RGMIIPCR_SETSP_1000M|SCFG_RGMIIPCR_SETSP_10M);
6503 +
6504 +       if (speed == _1000BASET) {
6505 +               ecr |= EMAC_ECNTRL_SPEED;
6506 +               rgmii_pcr |= SCFG_RGMIIPCR_SETSP_1000M;
6507 +       }
6508 +       else if (speed != _100BASET){
6509 +               rcr |= EMAC_RCNTRL_RMII_10T;
6510 +               rgmii_pcr |= SCFG_RGMIIPCR_SETSP_10M;
6511 +       }
6512 +
6513 +       writel(ecr, gemac_base + EMAC_ECNTRL_REG);
6514 +       out_be32(&scfg->rgmiipcr, rgmii_pcr | SCFG_RGMIIPCR_SETFD);
6515 +
6516 +       /* remove loop back */
6517 +       rcr &= ~EMAC_RCNTRL_LOOP;
6518 +       /* enable flow control */
6519 +       rcr |= EMAC_RCNTRL_FCE;
6520 +
6521 +       /* Enable MII mode */
6522 +       rcr |= EMAC_RCNTRL_MII_MODE;
6523 +
6524 +       /* CRC field is stripped from the frame */
6525 +       //rcr |= EMAC_RCNTRL_CRC_FWD;
6526 +
6527 +       /* Enable promiscuous mode
6528 +          FIXME should be removed later*/
6529 +       //rcr |= EMAC_RCNTRL_PROM;
6530 +       writel(rcr, gemac_base + EMAC_RCNTRL_REG);
6531 +
6532 +       /*Enable Tx full duplex */
6533 +       writel(readl(gemac_base + EMAC_TCNTRL_REG ) | EMAC_TCNTRL_FDEN, gemac_base + EMAC_TCNTRL_REG);
6534 +
6535 +}
6536 +
6537 +static void ls1012a_gemac_set_ethaddr(void *gemac_base, uchar *mac)
6538 +{
6539 +        writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3], gemac_base + EMAC_PHY_ADDR_LOW);
6540 +        writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, gemac_base + EMAC_PHY_ADDR_HIGH);
6541 +}
6542 +
6543 +/** Stops or Disables GEMAC pointing to this eth iface.
6544 + *
6545 + * @param[in]   edev    Pointer to eth device structure.
6546 + *
6547 + * @return      none
6548 + */
6549 +static void ls1012a_eth_halt(struct eth_device *edev)
6550 +{
6551 +        struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)edev->priv;
6552 +
6553 +        ls1012a_gemac_enable(priv->gem->gemac_base);
6554 +
6555 +        gpi_disable(priv->gem->egpi_base);
6556 +
6557 +        return;
6558 +}
6559 +
6560 +static int ls1012a_eth_init(struct eth_device *dev, bd_t * bd)
6561 +{
6562 +        struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
6563 +        struct gemac_s *gem = priv->gem;
6564 +       int speed;
6565 +       int tmp;
6566 +
6567 +        /* set ethernet mac address */
6568 +        ls1012a_gemac_set_ethaddr(gem->gemac_base, dev->enetaddr);
6569 +
6570 +       //MAC will be always in GMII mode, it doesn't change with the link speed.
6571 +       //ls1012a_gemac_set_mode(gem->gemac_base, gem->gemac_mode);
6572 +
6573 +       writel(0x00000004, gem->gemac_base + EMAC_TFWR_STR_FWD);
6574 +       writel(0x00000005, gem->gemac_base + EMAC_RX_SECTIOM_FULL);
6575 +       writel(0x00003fff, gem->gemac_base + EMAC_TRUNC_FL);
6576 +       writel(0x00000030, gem->gemac_base + EMAC_TX_SECTION_EMPTY);
6577 +       writel(0x00000000, gem->gemac_base + EMAC_MIB_CTRL_STS_REG);
6578 +
6579 +#ifndef CONFIG_EMU
6580 +#ifdef CONFIG_PHYLIB
6581 +       /* Start up the PHY */
6582 +       //if(gem->phy_mode != PHY_INTERFACE_MODE_SGMII) {
6583 +       if (phy_startup(priv->phydev)) {
6584 +               printf("Could not initialize PHY %s\n",
6585 +                               priv->phydev->dev->name);
6586 +               return -1;
6587 +       }
6588 +       speed = priv->phydev->speed;
6589 +       printf("Speed detected %x\n", speed);
6590 +       if(priv->phydev->duplex == DUPLEX_HALF) {
6591 +               printf("Half duplex not supported \n");
6592 +               return -1;
6593 +       }
6594 +#endif
6595 +#else
6596 +       /*in emulator it is always 1000Mbps */
6597 +       speed = _1000BASET;
6598 +#endif
6599 +       ls1012a_gemac_set_speed(gem->gemac_base, speed);
6600 +
6601 +        /* Enable GPI */
6602 +        gpi_enable(gem->egpi_base);
6603 +
6604 +        /* Enable GEMAC */
6605 +        ls1012a_gemac_enable(gem->gemac_base);
6606 +
6607 +       return 0;
6608 +
6609 +}
6610 +
6611 +static int ls1012a_eth_send(struct eth_device *dev, void *data, int length)
6612 +{
6613 +        struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
6614 +
6615 +        int rc;
6616 +       int i=0;
6617 +
6618 +        rc = pfe_send(priv->gemac_port, data, length);
6619 +
6620 +        if (rc < 0) {
6621 +                printf("Tx Q full\n");
6622 +                return 0;
6623 +        }
6624 +
6625 +        while (1) {
6626 +                rc = pfe_tx_done();
6627 +                if (rc == 0)
6628 +                        break;
6629 +
6630 +               udelay(100);
6631 +               i++;
6632 +               if(i == 30000)
6633 +                       printf("Tx timeout, send failed\n");
6634 +                       break;
6635 +
6636 +       }
6637 +
6638 +       return 0;
6639 +}
6640 +
6641 +static int ls1012a_eth_recv(struct eth_device *dev)
6642 +{
6643 +        struct ls1012a_eth_dev *priv = (struct ls1012a_eth_dev *)dev->priv;
6644 +        u32 pkt_buf;
6645 +        int len;
6646 +        int phy_port;
6647 +
6648 +        len = pfe_recv(&pkt_buf, &phy_port);
6649 +
6650 +        if (len < 0)
6651 +                return 0; //no packet in rx
6652 +
6653 +        dprint("Rx pkt: pkt_buf(%08x), phy_port(%d), len(%d)\n", pkt_buf, phy_port, len);
6654 +        if (phy_port != priv->gemac_port)  {
6655 +                printf("Rx pkt not on expected port\n");
6656 +               pfe_recv_ack();
6657 +                return 0;
6658 +        }
6659 +
6660 +       // Pass the packet up to the protocol layers.
6661 +       net_process_received_packet((uchar *)pkt_buf, len);
6662 +
6663 +       pfe_recv_ack();
6664 +       return 0;
6665 +}
6666 +
6667 +#if defined(CONFIG_PHYLIB)
6668 +
6669 +#define MDIO_TIMEOUT    5000
6670 +static int ls1012a_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr, int reg_addr)
6671 +{
6672 +       void *reg_base = bus->priv;
6673 +       u32 reg;
6674 +       u32 phy;
6675 +       u32 reg_data;
6676 +       u16 val;
6677 +       int timeout = MDIO_TIMEOUT;
6678 +
6679 +       reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
6680 +       phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
6681 +
6682 +       reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_RD | EMAC_MII_DATA_TA | phy | reg );
6683 +
6684 +       //dprint("%s write data %x %x %x\n", __func__, reg_data, reg_addr, phy_addr);
6685 +       writel(reg_data, reg_base + EMAC_MII_DATA_REG);
6686 +
6687 +        /*
6688 +         * wait for the MII interrupt
6689 +         */
6690 +       while(!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII))
6691 +       {
6692 +               if (timeout-- <= 0) {
6693 +                       printf("Phy MDIO read/write timeout\n");
6694 +                       return -1;
6695 +               }
6696 +       }
6697 +
6698 +       /*
6699 +         * clear MII interrupt
6700 +         */
6701 +        writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
6702 +
6703 +        /*
6704 +         * it's now safe to read the PHY's register
6705 +         */
6706 +        val = (u16)readl(reg_base + EMAC_MII_DATA_REG);
6707 +        dprint("%s: %x phy: %02x reg:%02x val:%#x\n", __func__, reg_base, phy_addr, reg_addr, val);
6708 +
6709 +        return val;
6710 +}
6711 +
6712 +static int ls1012a_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr, int reg_addr, u16 data)
6713 +{
6714 +       void *reg_base = bus->priv;
6715 +       u32 reg;
6716 +       u32 phy;
6717 +       u32 reg_data;
6718 +       int timeout = MDIO_TIMEOUT;
6719 +       int val;
6720 +
6721 +       reg = ((reg_addr & EMAC_MII_DATA_RA_MASK) << EMAC_MII_DATA_RA_SHIFT);
6722 +       phy = ((phy_addr & EMAC_MII_DATA_PA_MASK) << EMAC_MII_DATA_PA_SHIFT);
6723 +
6724 +       reg_data = (EMAC_MII_DATA_ST | EMAC_MII_DATA_OP_WR | EMAC_MII_DATA_TA | phy | reg | data);
6725 +
6726 +       //dprint("%s write data %x\n", __func__, reg_data);
6727 +       writel(reg_data, reg_base + EMAC_MII_DATA_REG);
6728 +
6729 +        /*
6730 +         * wait for the MII interrupt
6731 +         */
6732 +       while(!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII))
6733 +       {
6734 +               if (timeout-- <= 0) {
6735 +                       printf("Phy MDIO read/write timeout\n");
6736 +                       return -1;
6737 +               }
6738 +       }
6739 +
6740 +       /*
6741 +         * clear MII interrupt
6742 +         */
6743 +        writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
6744 +
6745 +        dprint("%s: phy: %02x reg:%02x val:%#x\n", __func__, phy_addr, reg_addr, data);
6746 +
6747 +        return val;
6748 +}
6749 +
6750 +
6751 +struct mii_dev *ls1012a_mdio_init(struct mdio_info *mdio_info)
6752 +{
6753 +        struct mii_dev *bus;
6754 +        int ret;
6755 +       u32 mdio_speed;
6756 +       u32 pclk = 250000000;
6757 +
6758 +        bus = mdio_alloc();
6759 +        if (!bus) {
6760 +                printf("mdio_alloc failed\n");
6761 +                return NULL;
6762 +        }
6763 +        bus->read = ls1012a_phy_read;
6764 +        bus->write = ls1012a_phy_write;
6765 +       /* MAC1 MDIO used to communicate with external PHYS */
6766 +        bus->priv = mdio_info->reg_base;
6767 +       sprintf(bus->name, mdio_info->name);
6768 +
6769 +       /*configure mdio speed */
6770 +       mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
6771 +       mdio_speed |= EMAC_HOLDTIME(0x4);
6772 +       writel(mdio_speed, mdio_info->reg_base + EMAC_MII_CTRL_REG);
6773 +
6774 +        ret = mdio_register(bus);
6775 +        if (ret) {
6776 +                printf("mdio_register failed\n");
6777 +                free(bus);
6778 +                return NULL;
6779 +        }
6780 +       return bus;
6781 +}
6782 +
6783 +static void ls1012a_configure_serdes(struct ls1012a_eth_dev *priv)
6784 +{
6785 +       struct mii_dev bus;
6786 +       int value,sgmii_2500=0;
6787 +
6788 +       printf("%s %d\n", __func__, priv->gemac_port);
6789 +       /* PCS configuration done with corresponding GEMAC */
6790 +       bus.priv = priv->gem->gemac_base;
6791 +
6792 +       ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x0);
6793 +       ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x1);
6794 +       ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x2);
6795 +       ls1012a_phy_read(&bus, 0, MDIO_DEVAD_NONE, 0x3);
6796 +#if 0
6797 +       /*These settings taken from validtion team */
6798 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
6799 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, 0xb); //3 in case our code
6800 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, 0x1a1);
6801 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
6802 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
6803 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x1140);
6804 +       return;
6805 +#endif
6806 +
6807 +       /*Reset serdes */
6808 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x0, 0x8000);
6809 +
6810 +       /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
6811 +       value = PHY_SGMII_IF_MODE_SGMII;
6812 +       if (!sgmii_2500)
6813 +               value |= PHY_SGMII_IF_MODE_AN;
6814 +
6815 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
6816 +
6817 +       /* Dev ability according to SGMII specification */
6818 +       value = PHY_SGMII_DEV_ABILITY_SGMII;
6819 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x4, value);
6820 +
6821 +       /* Adjust link timer for SGMII  -
6822 +       1.6 ms in units of 8 ns = 2 * 10^5 = 0x30d40 */
6823 +       //ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x3);
6824 +       //ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
6825 +
6826 +       //These values taken from validation team
6827 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x13, 0x0);
6828 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0x400);
6829 +
6830 +       /* Restart AN */
6831 +       value = PHY_SGMII_CR_DEF_VAL;
6832 +       if (!sgmii_2500)
6833 +               value |= PHY_SGMII_CR_RESET_AN;
6834 +       ls1012a_phy_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
6835 +
6836 +
6837 +}
6838 +
6839 +void ls1012a_set_mdio(int dev_id, struct mii_dev *bus)
6840 +{
6841 +       gem_info[dev_id].bus = bus;
6842 +}
6843 +
6844 +void ls1012a_set_phy_address_mode(int dev_id, int phy_id, int phy_mode)
6845 +{
6846 +       gem_info[dev_id].phy_address = phy_id;
6847 +       gem_info[dev_id].phy_mode  = phy_mode;
6848 +}
6849 +
6850 +int ls1012a_phy_configure(struct ls1012a_eth_dev *priv, int dev_id, int phy_id)
6851 +{
6852 +       struct phy_device *phydev = NULL;
6853 +       struct eth_device *dev = priv->dev;
6854 +        struct gemac_s *gem = priv->gem;
6855 +       struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
6856 +
6857 +       //Configure SGMII  PCS
6858 +       if(gem->phy_mode == PHY_INTERFACE_MODE_SGMII ||
6859 +                       gem->phy_mode == PHY_INTERFACE_MODE_SGMII_2500)
6860 +       {
6861 +               //printf("Select MDIO from serdes\n");
6862 +               out_be32(&scfg->mdioselcr, 0x00000000);
6863 +               ls1012a_configure_serdes(priv);
6864 +       }
6865 +
6866 +       /*By this time on-chip SGMII initialization is done
6867 +       * we can swith mdio interface to external PHYs */
6868 +       //printf("Select MDIO from PAD\n");
6869 +       out_be32(&scfg->mdioselcr, 0x80000000);
6870 +
6871 +       if(! gem->bus) return -1;
6872 +        phydev = phy_connect(gem->bus, phy_id, dev, gem->phy_mode);
6873 +        if (!phydev) {
6874 +                printf("phy_connect failed\n");
6875 +                return -1;
6876 +        }
6877 +
6878 +        phy_config(phydev);
6879 +
6880 +       priv->phydev = phydev;
6881 +
6882 +        return 0;
6883 +}
6884 +#endif
6885 +
6886 +int ls1012a_gemac_initialize(bd_t * bis, int dev_id, char *devname)
6887 +{
6888 +        struct eth_device *dev;
6889 +        struct ls1012a_eth_dev *priv;
6890 +        struct pfe *pfe;
6891 +       int i;
6892 +
6893 +       if(dev_id > 1)
6894 +       {
6895 +               printf("Invalid port\n");
6896 +               return -1;
6897 +       }
6898 +
6899 +        dev = (struct eth_device *)malloc(sizeof(struct eth_device));
6900 +        if (!dev)
6901 +                return -1;
6902 +
6903 +        memset(dev, 0, sizeof(struct eth_device));
6904 +
6905 +        priv = (struct ls1012a_eth_dev *)malloc(sizeof(struct ls1012a_eth_dev));
6906 +        if (!priv)
6907 +                return -1;
6908 +
6909 +        gemac_list[dev_id] = priv;
6910 +       priv->gemac_port = dev_id;
6911 +        priv->gem = &gem_info[priv->gemac_port];
6912 +        priv->dev = dev;
6913 +
6914 +        pfe = &priv->pfe;
6915 +
6916 +        pfe->cbus_baseaddr = (void *)CONFIG_SYS_PPFE_ADDR;
6917 +        pfe->ddr_baseaddr = (void *)CONFIG_DDR_PPFE_BASEADDR;
6918 +        pfe->ddr_phys_baseaddr = (unsigned long)CONFIG_DDR_PPFE_PHYS_BASEADDR;
6919 +
6920 +       sprintf(dev->name, devname);
6921 +        dev->priv = priv;
6922 +        dev->init = ls1012a_eth_init;
6923 +        dev->halt = ls1012a_eth_halt;
6924 +        dev->send = ls1012a_eth_send;
6925 +        dev->recv = ls1012a_eth_recv;
6926 +
6927 +        /* Tell u-boot to get the addr from the env */
6928 +        for (i = 0; i < 6; i++)
6929 +                dev->enetaddr[i] = 0;
6930 +
6931 +        pfe_probe(pfe);
6932 +
6933 +        switch(priv->gemac_port)  {
6934 +                case EMAC_PORT_0:
6935 +                default:
6936 +                        priv->gem->gemac_base = EMAC1_BASE_ADDR;
6937 +                        priv->gem->egpi_base = EGPI1_BASE_ADDR;
6938 +                break;
6939 +                case EMAC_PORT_1:
6940 +                        priv->gem->gemac_base = EMAC2_BASE_ADDR;
6941 +                        priv->gem->egpi_base = EGPI2_BASE_ADDR;
6942 +                break;
6943 +        }
6944 +
6945 +
6946 +#ifndef CONFIG_EMU
6947 +#if defined(CONFIG_PHYLIB)
6948 +       if(ls1012a_phy_configure(priv, dev_id, gem_info[priv->gemac_port].phy_address))
6949 +               return -1;
6950 +#else
6951 +       #error ("Please enable CONFIG_PHYLIB")
6952 +#endif
6953 +#endif
6954 +
6955 +        eth_register(dev);
6956 +
6957 +       return 0;
6958 +}
6959 diff --git a/drivers/net/pfe_eth/pfe_eth.h b/drivers/net/pfe_eth/pfe_eth.h
6960 new file mode 100644
6961 index 0000000..dfcc00e
6962 --- /dev/null
6963 +++ b/drivers/net/pfe_eth/pfe_eth.h
6964 @@ -0,0 +1,161 @@
6965 +/*
6966 + *  (C) Copyright 2011
6967 + *  Author : Mindspeed Technologes
6968 + *
6969 + *  See file CREDITS for list of people who contributed to this
6970 + *  project.
6971 + *
6972 + *  This program is free software; you can redistribute it and/or
6973 + *  modify it under the terms of the GNU General Public License as
6974 + *  published by the Free Software Foundation; either version 2 of
6975 + *  the License, or (at your option) any later version.
6976 + *
6977 + *  This program is distributed in the hope that it will be useful,
6978 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
6979 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
6980 + *  GNU General Public License for more details.
6981 + *
6982 + *  You should have received a copy of the GNU General Public License
6983 + *  along with this program; if not, write to the Free Software
6984 + *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
6985 + *  MA 02111-1307 USA
6986 + * */
6987 +
6988 +#ifndef _LS1012a_ETH_H_
6989 +#define _LS1012a_ETH_H_
6990 +
6991 +
6992 +#include "pfe_driver.h"
6993 +
6994 +#ifndef SZ_1K
6995 +#define SZ_1K 1024
6996 +#endif
6997 +
6998 +#ifndef SZ_1M
6999 +#define SZ_1M (1024 * 1024)
7000 +#endif
7001 +
7002 +#define BMU2_DDR_BASEADDR      0
7003 +#define BMU2_BUF_COUNT         (3 * SZ_1K)
7004 +#define BMU2_DDR_SIZE          (DDR_BUF_SIZE * BMU2_BUF_COUNT)
7005 +
7006 +#define TMU_LLM_BASEADDR       (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
7007 +#define TMU_LLM_QUEUE_LEN      (16 * 256)                      /**< Must be power of two and at least 16 * 8 = 128 bytes */
7008 +#define TMU_LLM_SIZE           (4 * 16 * TMU_LLM_QUEUE_LEN)    /**< (4 TMU's x 16 queues x queue_len) */
7009 +
7010 +#define HIF_RX_PKT_DDR_BASEADDR (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
7011 +#define HIF_RX_PKT_DDR_SIZE     (HIF_RX_DESC_NT * DDR_BUF_SIZE)
7012 +#define HIF_TX_PKT_DDR_BASEADDR (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
7013 +#define HIF_TX_PKT_DDR_SIZE     (HIF_TX_DESC_NT * DDR_BUF_SIZE)
7014 +
7015 +#define HIF_DESC_BASEADDR       (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
7016 +#define HIF_RX_DESC_SIZE        (16*HIF_RX_DESC_NT)
7017 +#define HIF_TX_DESC_SIZE        (16*HIF_TX_DESC_NT)
7018 +#define HIF_DESC_SIZE           (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
7019 +
7020 +//#define FPPDIAG_CTL_BASE_ADDR        (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
7021 +#define FPPDIAG_CTL_BASE_ADDR  0x700000
7022 +#define FPPDIAG_CTL_SIZE               256     /**< Must be at least 11*8 bytes */
7023 +#define FPPDIAG_PAGE_BASE_ADDR (FPPDIAG_CTL_BASE_ADDR + FPPDIAG_CTL_SIZE)
7024 +#define FPPDIAG_PAGE_TOTAL_SIZE        (11 * 256) /**< 256 bytes per PE, 11 PEs */
7025 +
7026 +//#define UTIL_CODE_BASEADDR   (FPPDIAG_PAGE_BASE_ADDR + FPPDIAG_PAGE_TOTAL_SIZE)
7027 +#define UTIL_CODE_BASEADDR     0x780000
7028 +#define UTIL_CODE_SIZE         (128 * SZ_1K)
7029 +
7030 +#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
7031 +#define UTIL_DDR_DATA_SIZE     (64 * SZ_1K)
7032 +
7033 +#define CLASS_DDR_DATA_BASEADDR        (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
7034 +#define CLASS_DDR_DATA_SIZE    (32 * SZ_1K)
7035 +
7036 +#define TMU_DDR_DATA_BASEADDR  (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
7037 +#define TMU_DDR_DATA_SIZE      (32 * SZ_1K)
7038 +
7039 +//#define ROUTE_TABLE_BASEADDR (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
7040 +#define ROUTE_TABLE_BASEADDR   0x800000
7041 +#define ROUTE_TABLE_HASH_BITS_MAX      15      /**< 32K entries */
7042 +#define ROUTE_TABLE_HASH_BITS  8       /**< 256 entries */
7043 +#define ROUTE_TABLE_SIZE       ((1 << ROUTE_TABLE_HASH_BITS_MAX) * CLASS_ROUTE_SIZE)
7044 +
7045 +#define        PFE_TOTAL_DATA_SIZE     (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
7046 +
7047 +#if PFE_TOTAL_DATA_SIZE > (12 * SZ_1M)
7048 +#error DDR mapping above 12MiB
7049 +#endif
7050 +
7051 +/* LMEM Mapping */
7052 +#define BMU1_LMEM_BASEADDR     0
7053 +#define BMU1_BUF_COUNT         256
7054 +#define BMU1_LMEM_SIZE         (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
7055 +
7056 +
7057 +#define CONFIG_DDR_PPFE_PHYS_BASEADDR  0x03800000
7058 +#define CONFIG_DDR_PPFE_BASEADDR       0x83800000
7059 +
7060 +
7061 +#define GEMAC_NO_PHY           1
7062 +#define GEMAC_HAVE_SWITCH_PHY     2
7063 +#define GEMAC_HAVE_SWITCH              4
7064 +
7065 +
7066 +typedef struct gemac_s {
7067 +
7068 +       void *gemac_base;
7069 +       void *egpi_base;
7070 +
7071 +       /* GEMAC config */
7072 +       int gemac_mode;
7073 +       int gemac_speed;
7074 +       int gemac_duplex;
7075 +        int flags;
7076 +       /* phy iface */
7077 +       int phy_address;
7078 +       int phy_mode;
7079 +       struct mii_dev *bus;
7080 +
7081 +} gemac_t;
7082 +
7083 +struct mdio_info {
7084 +       void *reg_base;
7085 +       char *name;
7086 +};
7087 +
7088 +
7089 +struct pfe {
7090 +       unsigned long ddr_phys_baseaddr;
7091 +       void *ddr_baseaddr;
7092 +       void *cbus_baseaddr;
7093 +};
7094 +
7095 +
7096 +typedef struct ls1012a_eth_dev {
7097 +
7098 +       int gemac_port;
7099 +
7100 +       struct gemac_s *gem;
7101 +       struct pfe      pfe;
7102 +
7103 +        struct eth_device *dev;
7104 +#ifdef CONFIG_PHYLIB
7105 +       struct phy_device *phydev;
7106 +#endif
7107 +} ls1012a_eth_dev_t;
7108 +
7109 +
7110 +struct firmware {
7111 +       u8 *data;
7112 +};
7113 +
7114 +
7115 +int pfe_probe(struct pfe *pfe);
7116 +int pfe_remove(struct pfe *pfe);
7117 +
7118 +
7119 +//#define dprint(fmt, arg...)  printf(fmt, ##arg)
7120 +#define dprint(fmt, arg...)
7121 +//#define dprint       printf
7122 +
7123 +
7124 +#endif //_LS1012a_ETH_H_
7125 +
7126 diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
7127 new file mode 100644
7128 index 0000000..165eb3c
7129 --- /dev/null
7130 +++ b/drivers/net/pfe_eth/pfe_firmware.c
7131 @@ -0,0 +1,193 @@
7132 +
7133 +
7134 +/** @file
7135 + *  Contains all the functions to handle parsing and loading of PE firmware files.
7136 + */
7137 +
7138 +#include "hal.h"
7139 +#include "pfe_firmware.h"
7140 +#include "pfe/pfe.h"
7141 +
7142 +
7143 +/* CLASS-PE ELF file content */
7144 +unsigned char class_fw_data[] __attribute__((aligned(sizeof(int)))) = {
7145 +#include CLASS_FIRMWARE_FILENAME
7146 +};
7147 +
7148 +/* TMU-PE ELF file content */
7149 +unsigned char tmu_fw_data[] __attribute__((aligned(sizeof(int)))) = {
7150 +#include TMU_FIRMWARE_FILENAME
7151 +};
7152 +
7153 +#if !defined(CONFIG_UTIL_PE_DISABLED)
7154 +unsigned char util_fw_data[] = {
7155 +#include UTIL_FIRMWARE_FILENAME
7156 +};
7157 +#endif
7158 +
7159 +/** PFE elf firmware loader.
7160 +* Loads an elf firmware image into a list of PE's (specified using a bitmask)
7161 +*
7162 +* @param pe_mask       Mask of PE id's to load firmware to
7163 +* @param fw            Pointer to the firmware image
7164 +*
7165 +* @return              0 on sucess, a negative value on error
7166 +*
7167 +*/
7168 +int pfe_load_elf(int pe_mask, const struct firmware *fw)
7169 +{
7170 +       Elf32_Ehdr *elf_hdr = (Elf32_Ehdr *)fw->data;
7171 +       Elf32_Half sections = be16_to_cpu(elf_hdr->e_shnum);
7172 +       Elf32_Shdr *shdr = (Elf32_Shdr *) (fw->data + be32_to_cpu(elf_hdr->e_shoff));
7173 +       int id, section;
7174 +       int rc;
7175 +
7176 +       printf("%s: no of sections: %d\n", __func__, sections);
7177 +
7178 +       /* Some sanity checks */
7179 +       if (strncmp(&elf_hdr->e_ident[EI_MAG0], ELFMAG, SELFMAG))
7180 +       {
7181 +               printf("%s: incorrect elf magic number\n", __func__);
7182 +               return -1;
7183 +       }
7184 +
7185 +       if (elf_hdr->e_ident[EI_CLASS] != ELFCLASS32)
7186 +       {
7187 +               printf("%s: incorrect elf class(%x)\n", __func__, elf_hdr->e_ident[EI_CLASS]);
7188 +               return -1;
7189 +       }
7190 +
7191 +       if (elf_hdr->e_ident[EI_DATA] != ELFDATA2MSB)
7192 +       {
7193 +               printf("%s: incorrect elf data(%x)\n", __func__, elf_hdr->e_ident[EI_DATA]);
7194 +               return -1;
7195 +       }
7196 +
7197 +       if (be16_to_cpu(elf_hdr->e_type) != ET_EXEC)
7198 +       {
7199 +               printf("%s: incorrect elf file type(%x)\n", __func__, be16_to_cpu(elf_hdr->e_type));
7200 +               return -1;
7201 +       }
7202 +
7203 +       for (section = 0; section < sections; section++, shdr++)
7204 +       {
7205 +               if (!(be32_to_cpu(shdr->sh_flags) & (SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR)))
7206 +                        continue;
7207 +               for (id = 0; id < MAX_PE; id++)
7208 +                       if (pe_mask & (1 << id))
7209 +                       {
7210 +                               rc = pe_load_elf_section(id, fw->data, shdr);
7211 +                               if (rc < 0)
7212 +                                       goto err;
7213 +                       }
7214 +               //printf("\n");
7215 +       }
7216 +
7217 +       return 0;
7218 +
7219 +err:
7220 +       return rc;
7221 +}
7222 +
7223 +/** PFE firmware initialization.
7224 +* Loads different firmware files from filesystem.
7225 +* Initializes PE IMEM/DMEM and UTIL-PE DDR
7226 +* Initializes control path symbol addresses (by looking them up in the elf firmware files
7227 +* Takes PE's out of reset
7228 +*
7229 +* @return      0 on sucess, a negative value on error
7230 +*
7231 +*/
7232 +int pfe_firmware_init(u8 *class_fw_loc, u8 *tmu_fw_loc, u8 *util_fw_loc)
7233 +{
7234 +       struct firmware class_fw, tmu_fw;
7235 +#if !defined(CONFIG_UTIL_PE_DISABLED)
7236 +       struct firmware util_fw;
7237 +#endif
7238 +       int rc = 0;
7239 +
7240 +       printf("%s\n", __func__);
7241 +#if 0
7242 +       /*This testing purpose only */
7243 +       printf("Copying default fw \n");
7244 +       memcpy(class_fw_loc, class_fw_data, sizeof(class_fw_data));
7245 +       memcpy(tmu_fw_loc, tmu_fw_data, sizeof(tmu_fw_data));
7246 +       memcpy(util_fw_loc, util_fw_data, sizeof(util_fw_data));
7247 +#endif
7248 +
7249 +       if (class_fw_loc)
7250 +               class_fw.data = class_fw_loc;
7251 +       else
7252 +               class_fw.data = class_fw_data;
7253 +
7254 +       if (tmu_fw_loc)
7255 +               tmu_fw.data = tmu_fw_loc;
7256 +       else
7257 +               tmu_fw.data = tmu_fw_data;
7258 +
7259 +#if !defined(CONFIG_UTIL_PE_DISABLED)
7260 +       if (util_fw_loc)
7261 +               util_fw.data = util_fw_loc;
7262 +       else
7263 +               util_fw.data = util_fw_data;
7264 +#endif
7265 +
7266 +       rc = pfe_load_elf(CLASS_MASK, &class_fw);
7267 +       if (rc < 0) {
7268 +               printf("%s: class firmware load failed\n", __func__);
7269 +               goto err3;
7270 +       }
7271 +
7272 +       printf("%s: class firmware loaded\n", __func__);
7273 +
7274 +       rc = pfe_load_elf(TMU_MASK, &tmu_fw);
7275 +       if (rc < 0) {
7276 +               printf("%s: tmu firmware load failed\n", __func__);
7277 +               goto err3;
7278 +       }
7279 +
7280 +       printf("%s: tmu firmware loaded\n", __func__);
7281 +
7282 +#if !defined(CONFIG_UTIL_PE_DISABLED)
7283 +       rc = pfe_load_elf(UTIL_MASK, &util_fw);
7284 +       if (rc < 0) {
7285 +               printf("%s: util firmware load failed\n", __func__);
7286 +               goto err3;
7287 +       }
7288 +
7289 +       printf("%s: util firmware loaded\n", __func__);
7290 +
7291 +       util_enable();
7292 +#endif
7293 +
7294 +#if defined(CONFIG_LS1012A)
7295 +       tmu_enable(0xb);
7296 +#else
7297 +       tmu_enable(0xf);
7298 +#endif
7299 +       class_enable();
7300 +
7301 +       gpi_enable(HGPI_BASE_ADDR);
7302 +
7303 +
7304 +err3:
7305 +       return rc;
7306 +}
7307 +
7308 +/** PFE firmware cleanup
7309 +* Puts PE's in reset
7310 +*
7311 +*
7312 +*/
7313 +void pfe_firmware_exit(void)
7314 +{
7315 +       printf("%s\n", __func__);
7316 +
7317 +       class_disable();
7318 +       tmu_disable(0xf);
7319 +#if !defined(CONFIG_UTIL_PE_DISABLED)
7320 +       util_disable();
7321 +#endif
7322 +       hif_tx_disable();
7323 +       hif_rx_disable();
7324 +}
7325 diff --git a/drivers/net/pfe_eth/pfe_firmware.h b/drivers/net/pfe_eth/pfe_firmware.h
7326 new file mode 100644
7327 index 0000000..2823162
7328 --- /dev/null
7329 +++ b/drivers/net/pfe_eth/pfe_firmware.h
7330 @@ -0,0 +1,20 @@
7331 +
7332 +
7333 +/** @file
7334 + *  Contains all the defines to handle parsing and loading of PE firmware files.
7335 + */
7336 +
7337 +#ifndef __PFE_FIRMWARE_H__
7338 +#define __PFE_FIRMWARE_H__
7339 +
7340 +
7341 +#define CLASS_FIRMWARE_FILENAME                "class_sbl_elf.fw"
7342 +#define TMU_FIRMWARE_FILENAME             "tmu_sbl_elf.fw"
7343 +#define UTIL_FIRMWARE_FILENAME         "util_sbl_elf.fw"
7344 +
7345 +
7346 +int pfe_firmware_init(u8 * clasS_fw_loc, u8 *tmu_fw_loc, u8 *util_fw_loc);
7347 +void pfe_firmware_exit(void);
7348 +
7349 +
7350 +#endif
7351 diff --git a/drivers/net/pfe_eth/pfe_mod.h b/drivers/net/pfe_eth/pfe_mod.h
7352 new file mode 100644
7353 index 0000000..9436b72
7354 --- /dev/null
7355 +++ b/drivers/net/pfe_eth/pfe_mod.h
7356 @@ -0,0 +1,140 @@
7357 +/*
7358 + *  (C) Copyright 2011
7359 + *  Author : Mindspeed Technologes
7360 + *
7361 + *  See file CREDITS for list of people who contributed to this
7362 + *  project.
7363 + *
7364 + *  This program is free software; you can redistribute it and/or
7365 + *  modify it under the terms of the GNU General Public License as
7366 + *  published by the Free Software Foundation; either version 2 of
7367 + *  the License, or (at your option) any later version.
7368 + *
7369 + *  This program is distributed in the hope that it will be useful,
7370 + *  but WITHOUT ANY WARRANTY; without even the implied warranty of
7371 + *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
7372 + *  GNU General Public License for more details.
7373 + *
7374 + *  You should have received a copy of the GNU General Public License
7375 + *  along with this program; if not, write to the Free Software
7376 + *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
7377 + *  MA 02111-1307 USA
7378 + * */
7379 +
7380 +
7381 +#ifndef _PFE_MOD_H_
7382 +#define _PFE_MOD_H_
7383 +
7384 +#include <linux/device.h>
7385 +
7386 +#include "pfe/pfe.h"
7387 +#include "pfe/cbus.h"
7388 +#include "pfe/cbus/bmu.h"
7389 +
7390 +#include "pfe_driver.h"
7391 +
7392 +struct pfe;
7393 +
7394 +
7395 +struct pfe {
7396 +       unsigned long ddr_phys_baseaddr;
7397 +       void *ddr_baseaddr;
7398 +       void *cbus_baseaddr;
7399 +       void *apb_baseaddr;
7400 +       void *iram_baseaddr;
7401 +       int hif_irq;
7402 +       struct device *dev;
7403 +       struct pci_dev *pdev;
7404 +
7405 +#if 0
7406 +       struct pfe_ctrl ctrl;
7407 +       struct pfe_hif hif;
7408 +       struct pfe_eth eth;
7409 +#endif
7410 +};
7411 +
7412 +extern struct pfe *pfe;
7413 +
7414 +int pfe_probe(struct pfe *pfe);
7415 +int pfe_remove(struct pfe *pfe);
7416 +
7417 +#ifndef SZ_1K
7418 +#define SZ_1K 1024
7419 +#endif
7420 +
7421 +#ifndef SZ_1M
7422 +#define SZ_1M (1024 * 1024)
7423 +#endif
7424 +
7425 +/* DDR Mapping */
7426 +#if !defined(CONFIG_PLATFORM_PCI)
7427 +#define UTIL_CODE_BASEADDR     0
7428 +#define UTIL_CODE_SIZE         (128 * SZ_1K)
7429 +#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
7430 +#define UTIL_DDR_DATA_SIZE     (64 * SZ_1K)
7431 +#define CLASS_DDR_DATA_BASEADDR        (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
7432 +#define CLASS_DDR_DATA_SIZE    (32 * SZ_1K)
7433 +#define TMU_DDR_DATA_BASEADDR  (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
7434 +#define TMU_DDR_DATA_SIZE      (32 * SZ_1K)
7435 +#define ROUTE_TABLE_BASEADDR   (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
7436 +#define ROUTE_TABLE_HASH_BITS  15      /**< 32K entries */
7437 +#define ROUTE_TABLE_SIZE       ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
7438 +#define BMU2_DDR_BASEADDR      (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
7439 +#define BMU2_BUF_COUNT         (4096 - 256)                    /**< This is to get a total DDR size of 12MiB */
7440 +#define BMU2_DDR_SIZE          (DDR_BUF_SIZE * BMU2_BUF_COUNT)
7441 +#define TMU_LLM_BASEADDR       (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
7442 +#define TMU_LLM_QUEUE_LEN      (16 * 256)                      /**< Must be power of two and at least 16 * 8 = 128 bytes */
7443 +#define TMU_LLM_SIZE           (4 * 16 * TMU_LLM_QUEUE_LEN)    /**< (4 TMU's x 16 queues x queue_len) */
7444 +
7445 +#if (TMU_LLM_BASEADDR + TMU_LLM_SIZE) > 0xC00000
7446 +#error DDR mapping above 12MiB
7447 +#endif
7448 +
7449 +#else
7450 +
7451 +#define UTIL_CODE_BASEADDR     0
7452 +#if defined(CONFIG_UTIL_PE_DISABLED)
7453 +#define UTIL_CODE_SIZE         (0 * SZ_1K)
7454 +#else
7455 +#define UTIL_CODE_SIZE         (8 * SZ_1K)
7456 +#endif
7457 +#define UTIL_DDR_DATA_BASEADDR (UTIL_CODE_BASEADDR + UTIL_CODE_SIZE)
7458 +#define UTIL_DDR_DATA_SIZE     (0 * SZ_1K)
7459 +#define CLASS_DDR_DATA_BASEADDR        (UTIL_DDR_DATA_BASEADDR + UTIL_DDR_DATA_SIZE)
7460 +#define CLASS_DDR_DATA_SIZE    (0 * SZ_1K)
7461 +#define TMU_DDR_DATA_BASEADDR  (CLASS_DDR_DATA_BASEADDR + CLASS_DDR_DATA_SIZE)
7462 +#define TMU_DDR_DATA_SIZE      (0 * SZ_1K)
7463 +#define ROUTE_TABLE_BASEADDR   (TMU_DDR_DATA_BASEADDR + TMU_DDR_DATA_SIZE)
7464 +#define ROUTE_TABLE_HASH_BITS  5       /**< 32 entries */
7465 +#define ROUTE_TABLE_SIZE       ((1 << ROUTE_TABLE_HASH_BITS) * CLASS_ROUTE_SIZE)
7466 +#define BMU2_DDR_BASEADDR      (ROUTE_TABLE_BASEADDR + ROUTE_TABLE_SIZE)
7467 +#define BMU2_BUF_COUNT         8
7468 +#define BMU2_DDR_SIZE          (DDR_BUF_SIZE * BMU2_BUF_COUNT)
7469 +#define TMU_LLM_BASEADDR       (BMU2_DDR_BASEADDR + BMU2_DDR_SIZE)
7470 +#define TMU_LLM_QUEUE_LEN      (16 * 8)                        /**< Must be power of two and at least 16 * 8 = 128 bytes */
7471 +#define TMU_LLM_SIZE           (4 * 16 * TMU_LLM_QUEUE_LEN)    /**< (4 TMU's x 16 queues x queue_len) */
7472 +#define HIF_DESC_BASEADDR      (TMU_LLM_BASEADDR + TMU_LLM_SIZE)
7473 +#define HIF_RX_DESC_SIZE       (16*HIF_RX_DESC_NT)
7474 +#define HIF_TX_DESC_SIZE       (16*HIF_TX_DESC_NT)
7475 +#define HIF_DESC_SIZE          (HIF_RX_DESC_SIZE + HIF_TX_DESC_SIZE)
7476 +#define HIF_RX_PKT_DDR_BASEADDR        (HIF_DESC_BASEADDR + HIF_DESC_SIZE)
7477 +#define HIF_RX_PKT_DDR_SIZE    (HIF_RX_DESC_NT * DDR_BUF_SIZE)
7478 +#define HIF_TX_PKT_DDR_BASEADDR        (HIF_RX_PKT_DDR_BASEADDR + HIF_RX_PKT_DDR_SIZE)
7479 +#define HIF_TX_PKT_DDR_SIZE    (HIF_TX_DESC_NT * DDR_BUF_SIZE)
7480 +#define ROUTE_BASEADDR         (HIF_TX_PKT_DDR_BASEADDR + HIF_TX_PKT_DDR_SIZE)
7481 +#define ROUTE_SIZE             (2 * CLASS_ROUTE_SIZE)
7482 +
7483 +#if (ROUTE_BASEADDR + ROUTE_SIZE) > 0x10000
7484 +#error DDR mapping above 64KiB
7485 +#endif
7486 +
7487 +#define PFE_HOST_TO_PCI(addr)  (((u32)addr)- ((u32)DDR_BASE_ADDR))
7488 +#define PFE_PCI_TO_HOST(addr)  (((u32)addr)+ ((u32)DDR_BASE_ADDR))
7489 +#endif
7490 +
7491 +/* LMEM Mapping */
7492 +#define BMU1_LMEM_BASEADDR     0
7493 +#define BMU1_BUF_COUNT         256
7494 +#define BMU1_LMEM_SIZE         (LMEM_BUF_SIZE * BMU1_BUF_COUNT)
7495 +
7496 +#endif /* _PFE_MOD_H */
7497 diff --git a/drivers/net/pfe_eth/tmu_sbl_elf.fw b/drivers/net/pfe_eth/tmu_sbl_elf.fw
7498 new file mode 100644
7499 index 0000000..d9e8409
7500 --- /dev/null
7501 +++ b/drivers/net/pfe_eth/tmu_sbl_elf.fw
7502 @@ -0,0 +1 @@
7503 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7504 \ No newline at end of file
7505 diff --git a/drivers/net/pfe_eth/util_sbl_elf.fw b/drivers/net/pfe_eth/util_sbl_elf.fw
7506 new file mode 100644
7507 index 0000000..7a34b86
7508 --- /dev/null
7509 +++ b/drivers/net/pfe_eth/util_sbl_elf.fw
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7512 \ No newline at end of file
7513 diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
7514 index 07ef7c6..3c4ab6c 100644
7515 --- a/include/configs/ls1012a_common.h
7516 +++ b/include/configs/ls1012a_common.h
7517 @@ -109,6 +109,16 @@
7518  #define CONFIG_CMD_PING
7519  #undef CONFIG_CMD_IMLS
7520
7521 +/*  PPFE */
7522 +#define CONFIG_FSL_PPFE
7523 +
7524 +#ifdef CONFIG_FSL_PPFE
7525 +#define CONFIG_CMD_PFE_START
7526 +#define CONFIG_CMD_PFE_COMMANDS
7527 +#define CONFIG_UTIL_PE_DISABLED
7528 +
7529 +#endif
7530 +
7531
7532  #define CONFIG_ARCH_EARLY_INIT_R
7533
7534 diff --git a/include/configs/ls1012aqds.h b/include/configs/ls1012aqds.h
7535 index 488811b..1fa7b6f 100644
7536 --- a/include/configs/ls1012aqds.h
7537 +++ b/include/configs/ls1012aqds.h
7538 @@ -14,16 +14,14 @@
7539  #define CONFIG_CHIP_SELECTS_PER_CTRL   1
7540  #define CONFIG_NR_DRAM_BANKS           2
7541
7542 -#ifdef CONFIG_SYS_DPAA_FMAN
7543 -#define CONFIG_FMAN_ENET
7544 +#ifdef CONFIG_FSL_PPFE
7545 +/*#define CONFIG_CMD_PFE_START */
7546 +#define EMAC1_PHY_ADDR          0x1e
7547 +#define EMAC2_PHY_ADDR          0x1
7548  #define CONFIG_PHYLIB
7549  #define CONFIG_PHY_VITESSE
7550  #define CONFIG_PHY_REALTEK
7551 -#define RGMII_PHY1_ADDR                0x1
7552 -#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
7553 -#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
7554 -#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
7555 -#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
7556 +#define RGMII_RESET_WA
7557  #endif
7558
7559  /*  MMC  */
7560 @@ -142,6 +140,7 @@
7561  #define I2C_VOL_MONITOR_BUS_V_OVF      0x1
7562  #define I2C_VOL_MONITOR_BUS_V_SHIFT    3
7563
7564 +
7565  /* DSPI */
7566  #define CONFIG_FSL_DSPI
7567  #define CONFIG_FSL_DSPI1
7568 diff --git a/include/configs/ls1012ardb.h b/include/configs/ls1012ardb.h
7569 index 1629e19..1b72bf1 100644
7570 --- a/include/configs/ls1012ardb.h
7571 +++ b/include/configs/ls1012ardb.h
7572 @@ -19,10 +19,12 @@
7573  #define CONFIG_SYS_MEMTEST_START       0x80000000
7574  #define CONFIG_SYS_MEMTEST_END         0x9fffffff
7575
7576 +#ifdef CONFIG_FSL_PPFE
7577 +#define EMAC1_PHY_ADDR          0x2
7578 +#define EMAC2_PHY_ADDR          0x1
7579  #define CONFIG_PHYLIB
7580  #define CONFIG_PHY_REALTEK
7581 -#define SGMII_PHY1_ADDR                0x0
7582 -#define RGMII_PHY2_ADDR                0x1
7583 +#endif
7584
7585  /*
7586  * USB
7587 --
7588 1.7.9.5
7589