target/linux/amazon-2.6/files/include/asm-mips/amazon/ifx_ssc.h

   1 /*
   2  * ifx_ssc.h defines some data sructures used in ifx_ssc.c
   3  *
   4  * Copyright (C) 2004 Michael Schoenenborn (IFX COM TI BT)
   5  *
   6  *
   7  */
   8
   9 #ifndef __IFX_SSC_H
  10 #define __IFX_SSC_H
  11 #ifdef __KERNEL__
  12 #include <asm/amazon/ifx_ssc_defines.h>
  13 #endif  //__KERNEL__
  14
  15 #define PORT_CNT                1       // assume default value
  16
  17 /* symbolic constants to be used in SSC routines */
  18
  19 // ### TO DO: bad performance
  20 #define IFX_SSC_TXFIFO_ITL      1
  21 #define IFX_SSC_RXFIFO_ITL      1
  22
  23
  24
  25 struct ifx_ssc_statistics{
  26         unsigned int  abortErr;   /* abort error */
  27         unsigned int  modeErr;    /* master/slave mode error */
  28         unsigned int  txOvErr;    /* TX Overflow error */
  29         unsigned int  txUnErr;    /* TX Underrun error */
  30         unsigned int  rxOvErr;    /* RX Overflow error */
  31         unsigned int  rxUnErr;    /* RX Underrun error */
  32         unsigned int  rxBytes;
  33         unsigned int  txBytes;
  34 };
  35
  36
  37 struct ifx_ssc_hwopts {
  38         unsigned int  AbortErrDetect :1;   /* Abort Error detection (in slave mode) */
  39         unsigned int  rxOvErrDetect  :1;   /* Receive Overflow Error detection */
  40         unsigned int  rxUndErrDetect :1;   /* Receive Underflow Error detection */
  41         unsigned int  txOvErrDetect  :1;   /* Transmit Overflow Error detection */
  42         unsigned int  txUndErrDetect :1;   /* Transmit Underflow Error detection */
  43         unsigned int  echoMode       :1;   /* Echo mode */
  44         unsigned int  loopBack       :1;   /* Loopback mode */
  45         unsigned int  idleValue      :1;   /* Idle value */
  46         unsigned int  clockPolarity  :1;   /* Idle clock is high or low */
  47         unsigned int  clockPhase     :1;   /* Tx on trailing or leading edge*/
  48         unsigned int  headingControl :1;   /* LSB first or MSB first */
  49         unsigned int  dataWidth      :6;   /* from 2 up to 32 bits */
  50         unsigned int  masterSelect   :1;   /* Master or Slave mode */
  51         unsigned int  modeRxTx       :2;   /* rx/tx mode */
  52         unsigned int  gpoCs          :8;   /* choose outputs to use for chip select */
  53         unsigned int  gpoInv         :8;   /* invert GPO outputs */
  54 };
  55
  56
  57 struct ifx_ssc_frm_opts {
  58         bool            FrameEnable;    // SFCON.SFEN
  59         unsigned int    DataLength;     // SFCON.DLEN
  60         unsigned int    PauseLength;    // SFCON.PLEN
  61         unsigned int    IdleData;       // SFCON.IDAT
  62         unsigned int    IdleClock;      // SFCON.ICLK
  63         bool            StopAfterPause; // SFCON.STOP
  64 };
  65
  66 struct ifx_ssc_frm_status {
  67         bool            DataBusy;       // SFSTAT.DBSY
  68         bool            PauseBusy;      // SFSTAT.PBSY
  69         unsigned int    DataCount;      // SFSTAT.DCNT
  70         unsigned int    PauseCount;     // SFSTAT.PCNT
  71         bool            EnIntAfterData; // SFCON.IBEN
  72         bool            EnIntAfterPause;// SFCON.IAEN
  73 };
  74
  75 typedef struct {
  76         char    *buf;
  77         size_t  len;
  78 } ifx_ssc_buf_item_t;
  79
  80
  81 // data structures for batch execution
  82 typedef union {
  83         struct {
  84                 bool            save_options;
  85         } init;
  86         ifx_ssc_buf_item_t      read;
  87         ifx_ssc_buf_item_t      write;
  88         ifx_ssc_buf_item_t      rd_wr;
  89         unsigned int    set_baudrate;
  90         struct ifx_ssc_frm_opts set_frm;
  91         unsigned int    set_gpo;
  92         struct ifx_ssc_hwopts set_hwopts;
  93 }ifx_ssc_batch_cmd_param;
  94
  95 struct ifx_ssc_batch_list {
  96         unsigned int                    cmd;
  97         ifx_ssc_batch_cmd_param         cmd_param;
  98         struct ifx_ssc_batch_list       *next;
  99 };
 100
 101 #ifdef __KERNEL__
 102 #define IFX_SSC_IS_MASTER(p) ((p)->opts.masterSelect == SSC_MASTER_MODE)
 103
 104
 105 struct ifx_ssc_port{
 106         unsigned long           mapbase;
 107         struct ifx_ssc_hwopts   opts;
 108         struct ifx_ssc_statistics stats;
 109         struct ifx_ssc_frm_status frm_status;
 110         struct ifx_ssc_frm_opts frm_opts;
 111         /* wait queue for ifx_ssc_read() */
 112         wait_queue_head_t       rwait, pwait;
 113         int                     port_nr;
 114         char                    port_is_open; /* exclusive open  - boolean */
 115 //      int no_of_bits; /* number of _valid_ bits */
 116 //      int elem_size; /* shift for element (no of bytes)*/
 117         /* buffer and pointers to the read/write position */
 118         char                    *rxbuf; /* buffer for RX */
 119         char                    *rxbuf_end; /* buffer end pointer for RX */
 120         volatile char           *rxbuf_ptr; /* buffer write pointer for RX */
 121         char                    *txbuf; /* buffer for TX */
 122         char                    *txbuf_end; /* buffer end pointer for TX */
 123         volatile char           *txbuf_ptr; /* buffer read pointer for TX */
 124         unsigned int            baud;
 125         /* each channel has its own interrupts */
 126         /* (transmit/receive/error/frame) */
 127         unsigned int txirq, rxirq, errirq, frmirq;
 128 };
 129 /* default values for SSC configuration */
 130 // values of CON
 131 #define IFX_SSC_DEF_IDLE_DATA       1  /* enable */
 132 #define IFX_SSC_DEF_BYTE_VALID_CTL  1  /* enable */
 133 #define IFX_SSC_DEF_DATA_WIDTH      32 /* bits */
 134 #define IFX_SSC_DEF_ABRT_ERR_DETECT 0  /* disable */
 135 #define IFX_SSC_DEF_RO_ERR_DETECT   1  /* enable */
 136 #define IFX_SSC_DEF_RU_ERR_DETECT   0  /* disable */
 137 #define IFX_SSC_DEF_TO_ERR_DETECT   0  /* disable */
 138 #define IFX_SSC_DEF_TU_ERR_DETECT   0  /* disable */
 139 #define IFX_SSC_DEF_LOOP_BACK       0  /* disable */
 140 #define IFX_SSC_DEF_ECHO_MODE       0  /* disable */
 141 #define IFX_SSC_DEF_CLOCK_POLARITY  0  /* low */
 142 #define IFX_SSC_DEF_CLOCK_PHASE     1  /* 0: shift on leading edge, latch on trailling edge, 1, otherwise */
 143 #define IFX_SSC_DEF_HEADING_CONTROL IFX_SSC_MSB_FIRST
 144 #define IFX_SSC_DEF_MODE_RXTX       IFX_SSC_MODE_RXTX
 145 // other values
 146 #define IFX_SSC_DEF_MASTERSLAVE     IFX_SSC_MASTER_MODE /* master */
 147 #define IFX_SSC_DEF_BAUDRATE        1000000
 148 #define IFX_SSC_DEF_RMC             0x10
 149
 150 #define IFX_SSC_DEF_TXFIFO_FL       8
 151 #define IFX_SSC_DEF_RXFIFO_FL       1
 152
 153 #if 1 //TODO
 154 #define IFX_SSC_DEF_GPO_CS          2   /* no chip select */
 155 #define IFX_SSC_DEF_GPO_INV         0   /* no chip select */
 156 #else
 157 #error "what is ur Chip Select???"
 158 #endif
 159 #define IFX_SSC_DEF_SFCON           0   /* no serial framing */
 160 #if 0
 161 #define IFX_SSC_DEF_IRNEN           IFX_SSC_T_BIT | /* enable all int's */\
 162                                     IFX_SSC_R_BIT | IFX_SSC_E_BIT | IFX_SSC_F_BIT
 163 #endif
 164 #define IFX_SSC_DEF_IRNEN           IFX_SSC_T_BIT | /* enable all int's */\
 165                                     IFX_SSC_R_BIT | IFX_SSC_E_BIT
 166 #endif /* __KERNEL__ */
 167
 168 // batch execution commands
 169 #define IFX_SSC_BATCH_CMD_INIT          1
 170 #define IFX_SSC_BATCH_CMD_READ          2
 171 #define IFX_SSC_BATCH_CMD_WRITE         3
 172 #define IFX_SSC_BATCH_CMD_RD_WR         4
 173 #define IFX_SSC_BATCH_CMD_SET_BAUDRATE  5
 174 #define IFX_SSC_BATCH_CMD_SET_HWOPTS    6
 175 #define IFX_SSC_BATCH_CMD_SET_FRM       7
 176 #define IFX_SSC_BATCH_CMD_SET_GPO       8
 177 #define IFX_SSC_BATCH_CMD_FIFO_FLUSH    9
 178 //#define IFX_SSC_BATCH_CMD_
 179 //#define IFX_SSC_BATCH_CMD_
 180 #define IFX_SSC_BATCH_CMD_END_EXEC      0
 181
 182 /* Macros to configure SSC hardware */
 183 /* headingControl: */
 184 #define IFX_SSC_LSB_FIRST            0
 185 #define IFX_SSC_MSB_FIRST            1
 186 /* dataWidth: */
 187 #define IFX_SSC_MIN_DATA_WIDTH       2
 188 #define IFX_SSC_MAX_DATA_WIDTH       32
 189 /* master/slave mode select */
 190 #define IFX_SSC_MASTER_MODE          1
 191 #define IFX_SSC_SLAVE_MODE           0
 192 /* rx/tx mode */
 193 // ### TO DO: !!! ATTENTION! Hardware dependency => move to ifx_ssc_defines.h
 194 #define IFX_SSC_MODE_RXTX            0
 195 #define IFX_SSC_MODE_RX              1
 196 #define IFX_SSC_MODE_TX              2
 197 #define IFX_SSC_MODE_OFF             3
 198 #define IFX_SSC_MODE_MASK            IFX_SSC_MODE_RX | IFX_SSC_MODE_TX
 199
 200 /* GPO values */
 201 #define IFX_SSC_MAX_GPO_OUT          7
 202
 203 #define IFX_SSC_RXREQ_BLOCK_SIZE     32768
 204
 205 /***********************/
 206 /* defines for ioctl's */
 207 /***********************/
 208 #define IFX_SSC_IOCTL_MAGIC     'S'
 209 /* read out the statistics */
 210 #define IFX_SSC_STATS_READ _IOR(IFX_SSC_IOCTL_MAGIC, 1, struct ifx_ssc_statistics)
 211 /* clear the statistics */
 212 #define IFX_SSC_STATS_RESET _IO(IFX_SSC_IOCTL_MAGIC, 2)
 213 /* set the baudrate */
 214 #define IFX_SSC_BAUD_SET _IOW(IFX_SSC_IOCTL_MAGIC, 3, unsigned int)
 215 /* get the current baudrate */
 216 #define IFX_SSC_BAUD_GET _IOR(IFX_SSC_IOCTL_MAGIC, 4, unsigned int)
 217 /* set hardware options */
 218 #define IFX_SSC_HWOPTS_SET _IOW(IFX_SSC_IOCTL_MAGIC, 5, struct ifx_ssc_hwopts)
 219 /* get the current hardware options */
 220 #define IFX_SSC_HWOPTS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 6, struct ifx_ssc_hwopts)
 221 /* set transmission mode */
 222 #define IFX_SSC_RXTX_MODE_SET _IOW(IFX_SSC_IOCTL_MAGIC, 7, unsigned int)
 223 /* get the current transmission mode */
 224 #define IFX_SSC_RXTX_MODE_GET _IOR(IFX_SSC_IOCTL_MAGIC, 8, unsigned int)
 225 /* abort transmission */
 226 #define IFX_SSC_ABORT _IO(IFX_SSC_IOCTL_MAGIC, 9)
 227 #define IFX_SSC_FIFO_FLUSH _IO(IFX_SSC_IOCTL_MAGIC, 9)
 228
 229 /* set general purpose outputs */
 230 #define IFX_SSC_GPO_OUT_SET _IOW(IFX_SSC_IOCTL_MAGIC, 32, unsigned int)
 231 /* clear general purpose outputs */
 232 #define IFX_SSC_GPO_OUT_CLR _IOW(IFX_SSC_IOCTL_MAGIC, 33, unsigned int)
 233 /* get general purpose outputs */
 234 #define IFX_SSC_GPO_OUT_GET _IOR(IFX_SSC_IOCTL_MAGIC, 34, unsigned int)
 235
 236 /*** serial framing ***/
 237 /* get status of serial framing */
 238 #define IFX_SSC_FRM_STATUS_GET _IOR(IFX_SSC_IOCTL_MAGIC, 48, struct ifx_ssc_frm_status)
 239 /* get counter reload values and control bits */
 240 #define IFX_SSC_FRM_CONTROL_GET _IOR(IFX_SSC_IOCTL_MAGIC, 49, struct ifx_ssc_frm_opts)
 241 /* set counter reload values and control bits */
 242 #define IFX_SSC_FRM_CONTROL_SET _IOW(IFX_SSC_IOCTL_MAGIC, 50, struct ifx_ssc_frm_opts)
 243
 244
 245 /*** batch execution ***/
 246 /* do batch execution */
 247 #define IFX_SSC_BATCH_EXEC _IOW(IFX_SSC_IOCTL_MAGIC, 64, struct ifx_ssc_batch_list)
 248
 249
 250 #ifdef __KERNEL__
 251 // routines from ifx_ssc.c
 252 // ### TO DO
 253 /* kernel interface for read and write */
 254 ssize_t ifx_ssc_kread(int, char *, size_t);
 255 ssize_t ifx_ssc_kwrite(int, const char *, size_t);
 256
 257 #ifdef CONFIG_IFX_VP_KERNEL_TEST
 258 void ifx_ssc_tc(void);
 259 #endif // CONFIG_IFX_VP_KERNEL_TEST
 260
 261 #endif //__KERNEL__
 262 #endif // __IFX_SSC_H
 263