target/linux/ar71xx/files/arch/mips/ath79/mach-wpj342.c

   1 /*
   2  * Compex WPJ342 board support
   3  *
   4  * Copyright (c) 2011 Qualcomm Atheros
   5  * Copyright (c) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  */
  20
  21 #include <linux/irq.h>
  22 #include <linux/pci.h>
  23 #include <linux/phy.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/ath9k_platform.h>
  26 #include <linux/ar8216_platform.h>
  27 #include <linux/export.h>
  28
  29 #include <asm/mach-ath79/ar71xx_regs.h>
  30
  31 #include "pci.h"
  32 #include "common.h"
  33 #include "dev-ap9x-pci.h"
  34 #include "dev-eth.h"
  35 #include "dev-gpio-buttons.h"
  36 #include "dev-leds-gpio.h"
  37 #include "dev-m25p80.h"
  38 #include "dev-nfc.h"
  39 #include "dev-spi.h"
  40 #include "dev-usb.h"
  41 #include "dev-wmac.h"
  42 #include "machtypes.h"
  43
  44 #define WPJ342_GPIO_LED_STATUS          11
  45 #define WPJ342_GPIO_LED_SIG1            14
  46 #define WPJ342_GPIO_LED_SIG2            13
  47 #define WPJ342_GPIO_LED_SIG3            12
  48 #define WPJ342_GPIO_LED_SIG4            11
  49 #define WPJ342_GPIO_BUZZER                      15
  50
  51 #define WPJ342_GPIO_BTN_RESET           17
  52
  53 #define WPJ342_KEYS_POLL_INTERVAL       20 /* msecs */
  54 #define WPJ342_KEYS_DEBOUNCE_INTERVAL   (3 * WPJ342_KEYS_POLL_INTERVAL)
  55
  56 #define WPJ342_MAC0_OFFSET              0x10
  57 #define WPJ342_MAC1_OFFSET              0x18
  58 #define WPJ342_WMAC_CALDATA_OFFSET      0x1000
  59 #define WPJ342_PCIE_CALDATA_OFFSET      0x5000
  60
  61 #define WPJ342_ART_SIZE         0x8000
  62
  63 static struct gpio_led wpj342_leds_gpio[] __initdata = {
  64         {
  65                 .name           = "wpj342:red:sig1",
  66                 .gpio           = WPJ342_GPIO_LED_SIG1,
  67                 .active_low     = 1,
  68         },
  69         {
  70                 .name           = "wpj342:yellow:sig2",
  71                 .gpio           = WPJ342_GPIO_LED_SIG2,
  72                 .active_low     = 1,
  73         },
  74         {
  75                 .name           = "wpj342:green:sig3",
  76                 .gpio           = WPJ342_GPIO_LED_SIG3,
  77                 .active_low     = 1,
  78         },
  79         {
  80                 .name           = "wpj342:green:sig4",
  81                 .gpio           = WPJ342_GPIO_LED_SIG4,
  82                 .active_low     = 1,
  83         },
  84         {
  85                 .name           = "wpj342:buzzer",
  86                 .gpio           = WPJ342_GPIO_BUZZER,
  87                 .active_low     = 0,
  88         }
  89 };
  90
  91 static struct gpio_keys_button wpj342_gpio_keys[] __initdata = {
  92         {
  93                 .desc           = "reset",
  94                 .type           = EV_KEY,
  95                 .code           = KEY_RESTART,
  96                 .debounce_interval = WPJ342_KEYS_DEBOUNCE_INTERVAL,
  97                 .gpio           = WPJ342_GPIO_BTN_RESET,
  98                 .active_low     = 1,
  99         },
 100 };
 101
 102 static struct ar8327_pad_cfg wpj342_ar8327_pad0_cfg = {
 103         .mode = AR8327_PAD_MAC_RGMII,
 104         .txclk_delay_en = true,
 105         .rxclk_delay_en = true,
 106         .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
 107         .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
 108 };
 109
 110 static struct ar8327_led_cfg wpj342_ar8327_led_cfg = {
 111         .led_ctrl0 = 0x00000000,
 112         .led_ctrl1 = 0xc737c737,
 113         .led_ctrl2 = 0x00000000,
 114         .led_ctrl3 = 0x00c30c00,
 115         .open_drain = true,
 116 };
 117
 118 static struct ar8327_platform_data wpj342_ar8327_data = {
 119         .pad0_cfg = &wpj342_ar8327_pad0_cfg,
 120         .port0_cfg = {
 121                 .force_link = 1,
 122                 .speed = AR8327_PORT_SPEED_1000,
 123                 .duplex = 1,
 124                 .txpause = 1,
 125                 .rxpause = 1,
 126         },
 127         .led_cfg = &wpj342_ar8327_led_cfg,
 128 };
 129
 130 static struct mdio_board_info wpj342_mdio0_info[] = {
 131         {
 132                 .bus_id = "ag71xx-mdio.0",
 133                 .phy_addr = 0,
 134                 .platform_data = &wpj342_ar8327_data,
 135         },
 136 };
 137
 138
 139 static void __init wpj342_setup(void)
 140 {
 141         u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
 142         u8 *mac = (u8 *) KSEG1ADDR(0x1f02e000);
 143
 144         ath79_register_m25p80(NULL);
 145         ath79_register_leds_gpio(-1, ARRAY_SIZE(wpj342_leds_gpio),
 146                                 wpj342_leds_gpio);
 147
 148         ath79_register_gpio_keys_polled(-1, WPJ342_KEYS_POLL_INTERVAL,
 149                                         ARRAY_SIZE(wpj342_gpio_keys),
 150                                         wpj342_gpio_keys);
 151
 152         ath79_register_usb();
 153
 154         ath79_register_wmac(art + WPJ342_WMAC_CALDATA_OFFSET, NULL);
 155
 156         ath79_register_pci();
 157
 158         mdiobus_register_board_info(wpj342_mdio0_info,
 159                                 ARRAY_SIZE(wpj342_mdio0_info));
 160
 161         ath79_register_mdio(1, 0x0);
 162         ath79_register_mdio(0, 0x0);
 163
 164         ath79_init_mac(ath79_eth0_data.mac_addr, mac + WPJ342_MAC0_OFFSET, 0);
 165         ath79_init_mac(ath79_eth1_data.mac_addr, mac + WPJ342_MAC1_OFFSET, 0);
 166
 167         ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_MII_GMAC0);
 168
 169         /* GMAC0 is connected to an AR8236 switch */
 170         ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
 171         ath79_eth0_data.phy_mask = BIT(0);
 172         ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
 173         ath79_eth0_pll_data.pll_1000 = 0x06000000;
 174
 175         ath79_register_eth(0);
 176 }
 177
 178 MIPS_MACHINE(ATH79_MACH_WPJ342, "WPJ342", "Compex WPJ342", wpj342_setup);