1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
10 compatible = "dlink,dir-825-b1", "qca,ar7161";
11 model = "D-Link DIR825B1";
14 led-status = &orange_power;
18 bootargs = "console=ttyS0,115200";
22 compatible = "fixed-clock";
24 clock-output-names = "ref";
25 clock-frequency = <40000000>;
29 compatible = "gpio-leds";
31 label = "d-link:blue:usb";
32 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
33 default-state = "off";
34 trigger-sources = <&usb_ochi_port>, <&usb_echi_port>;
35 linux,default-trigger = "usbport";
38 orange_power: orange_power {
39 label = "d-link:orange:power";
40 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
44 label = "d-link:blue:power";
45 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
46 default-state = "off";
50 label = "d-link:blue:wps";
51 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
52 default-state = "off";
56 label = "d-link:orange:planet";
57 gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
58 default-state = "off";
62 label = "d-link:blue:planet";
63 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
64 default-state = "off";
69 compatible = "gpio-leds";
72 label = "d-link:blue:wlan2g";
73 gpios = <&ath9k0 5 GPIO_ACTIVE_LOW>;
74 default-state = "off";
75 linux,default-trigger = "phy0tpt";
79 label = "d-link:blue:wlan5g";
80 gpios = <&ath9k1 5 GPIO_ACTIVE_LOW>;
81 default-state = "off";
82 linux,default-trigger = "phy1tpt";
88 compatible = "gpio-keys-polled";
93 linux,code = <KEY_RESTART>;
94 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
95 debounce-interval = <60>;
100 linux,code = <KEY_WPS_BUTTON>;
101 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
102 debounce-interval = <60>;
107 compatible = "realtek,rtl8366s";
108 gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
109 gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
110 realtek,initvals = <0x06 0x0108>;
113 #address-cells = <1>;
119 phy4: ethernet-phy@4 {
130 #address-cells = <1>;
134 usb_ochi_port: port@1 {
136 #trigger-source-cells = <0>;
141 #address-cells = <1>;
145 usb_echi_port: port@1 {
147 #trigger-source-cells = <0>;
159 compatible = "pci168c,0029";
160 reg = <0x8800 0 0 0 0>;
167 compatible = "pci168c,0029";
168 reg = <0x9000 0 0 0 0>;
188 compatible = "jedec,spi-nor";
190 spi-max-frequency = <25000000>;
193 compatible = "fixed-partitions";
194 #address-cells = <1>;
199 reg = <0x000000 0x040000>;
205 reg = <0x040000 0x010000>;
211 reg = <0x050000 0x610000>;
214 caldata: partition@60000 {
216 reg = <0x660000 0x010000>;
222 reg = <0x670000 0x190000>;
232 pll-data = <0x11110000 0x00001099 0x00991099>;
243 pll-data = <0x11110000 0x00001099 0x00991099>;
245 phy-handle = <&phy4>;