ath79: ag71xx: add support for optional mdio reset
[openwrt/staging/wigyori.git] / target / linux / ath79 / files / drivers / net / ethernet / atheros / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/if_vlan.h>
29 #include <linux/phy.h>
30 #include <linux/skbuff.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
33 #include <linux/reset.h>
34 #include <linux/of.h>
35 #include <linux/mfd/syscon.h>
36 #include <linux/regmap.h>
37
38 #include <linux/bitops.h>
39
40 #include <asm/mach-ath79/ar71xx_regs.h>
41 #include <asm/mach-ath79/ath79.h>
42
43 #define AG71XX_DRV_NAME "ag71xx"
44
45 /*
46 * For our NAPI weight bigger does *NOT* mean better - it means more
47 * D-cache misses and lots more wasted cycles than we'll ever
48 * possibly gain from saving instructions.
49 */
50 #define AG71XX_NAPI_WEIGHT 32
51 #define AG71XX_OOM_REFILL (1 + HZ/10)
52
53 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
54 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
55 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
56
57 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
58 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
59
60 #define AG71XX_TX_MTU_LEN 1540
61
62 #define AG71XX_TX_RING_SPLIT 512
63 #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
64 AG71XX_TX_RING_SPLIT)
65 #define AG71XX_TX_RING_SIZE_DEFAULT 128
66 #define AG71XX_RX_RING_SIZE_DEFAULT 256
67
68 #define AG71XX_TX_RING_SIZE_MAX 128
69 #define AG71XX_RX_RING_SIZE_MAX 256
70
71 #ifdef CONFIG_AG71XX_DEBUG
72 #define DBG(fmt, args...) pr_debug(fmt, ## args)
73 #else
74 #define DBG(fmt, args...) do {} while (0)
75 #endif
76
77 #define ag71xx_assert(_cond) \
78 do { \
79 if (_cond) \
80 break; \
81 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
82 BUG(); \
83 } while (0)
84
85 struct ag71xx_desc {
86 u32 data;
87 u32 ctrl;
88 #define DESC_EMPTY BIT(31)
89 #define DESC_MORE BIT(24)
90 #define DESC_PKTLEN_M 0xfff
91 u32 next;
92 u32 pad;
93 } __attribute__((aligned(4)));
94
95 #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \
96 L1_CACHE_BYTES)
97
98 struct ag71xx_buf {
99 union {
100 struct sk_buff *skb;
101 void *rx_buf;
102 };
103 union {
104 dma_addr_t dma_addr;
105 unsigned int len;
106 };
107 };
108
109 struct ag71xx_ring {
110 struct ag71xx_buf *buf;
111 u8 *descs_cpu;
112 dma_addr_t descs_dma;
113 u16 desc_split;
114 u16 order;
115 unsigned int curr;
116 unsigned int dirty;
117 };
118
119 struct ag71xx_int_stats {
120 unsigned long rx_pr;
121 unsigned long rx_be;
122 unsigned long rx_of;
123 unsigned long tx_ps;
124 unsigned long tx_be;
125 unsigned long tx_ur;
126 unsigned long total;
127 };
128
129 struct ag71xx_napi_stats {
130 unsigned long napi_calls;
131 unsigned long rx_count;
132 unsigned long rx_packets;
133 unsigned long rx_packets_max;
134 unsigned long tx_count;
135 unsigned long tx_packets;
136 unsigned long tx_packets_max;
137
138 unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
139 unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
140 };
141
142 struct ag71xx_debug {
143 struct dentry *debugfs_dir;
144
145 struct ag71xx_int_stats int_stats;
146 struct ag71xx_napi_stats napi_stats;
147 };
148
149 struct ag71xx {
150 /*
151 * Critical data related to the per-packet data path are clustered
152 * early in this structure to help improve the D-cache footprint.
153 */
154 struct ag71xx_ring rx_ring ____cacheline_aligned;
155 struct ag71xx_ring tx_ring ____cacheline_aligned;
156
157 int mac_idx;
158
159 u16 desc_pktlen_mask;
160 u16 rx_buf_size;
161 u8 rx_buf_offset;
162 u8 tx_hang_workaround:1;
163
164 struct net_device *dev;
165 struct platform_device *pdev;
166 spinlock_t lock;
167 struct napi_struct napi;
168 u32 msg_enable;
169
170 /*
171 * From this point onwards we're not looking at per-packet fields.
172 */
173 void __iomem *mac_base;
174 void __iomem *mii_base;
175
176 struct ag71xx_desc *stop_desc;
177 dma_addr_t stop_desc_dma;
178
179 struct phy_device *phy_dev;
180 void *phy_priv;
181 int phy_if_mode;
182
183 unsigned int link;
184 unsigned int speed;
185 int duplex;
186
187 struct delayed_work restart_work;
188 struct timer_list oom_timer;
189
190 struct reset_control *mac_reset;
191 struct reset_control *mdio_reset;
192
193 u32 fifodata[3];
194 u32 plldata[3];
195 u32 pllreg[3];
196 struct regmap *pllregmap;
197
198 #ifdef CONFIG_AG71XX_DEBUG_FS
199 struct ag71xx_debug debug;
200 #endif
201 };
202
203 struct ag71xx_mdio {
204 struct reset_control *mdio_reset;
205 struct mii_bus *mii_bus;
206 struct regmap *mii_regmap;
207 };
208
209 extern struct ethtool_ops ag71xx_ethtool_ops;
210 void ag71xx_link_adjust(struct ag71xx *ag);
211
212 int ag71xx_phy_connect(struct ag71xx *ag);
213 void ag71xx_phy_disconnect(struct ag71xx *ag);
214
215 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
216 {
217 return (desc->ctrl & DESC_EMPTY) != 0;
218 }
219
220 static inline struct ag71xx_desc *
221 ag71xx_ring_desc(struct ag71xx_ring *ring, int idx)
222 {
223 return (struct ag71xx_desc *) &ring->descs_cpu[idx * AG71XX_DESC_SIZE];
224 }
225
226 static inline int
227 ag71xx_ring_size_order(int size)
228 {
229 return fls(size - 1);
230 }
231
232 /* Register offsets */
233 #define AG71XX_REG_MAC_CFG1 0x0000
234 #define AG71XX_REG_MAC_CFG2 0x0004
235 #define AG71XX_REG_MAC_IPG 0x0008
236 #define AG71XX_REG_MAC_HDX 0x000c
237 #define AG71XX_REG_MAC_MFL 0x0010
238 #define AG71XX_REG_MII_CFG 0x0020
239 #define AG71XX_REG_MII_CMD 0x0024
240 #define AG71XX_REG_MII_ADDR 0x0028
241 #define AG71XX_REG_MII_CTRL 0x002c
242 #define AG71XX_REG_MII_STATUS 0x0030
243 #define AG71XX_REG_MII_IND 0x0034
244 #define AG71XX_REG_MAC_IFCTL 0x0038
245 #define AG71XX_REG_MAC_ADDR1 0x0040
246 #define AG71XX_REG_MAC_ADDR2 0x0044
247 #define AG71XX_REG_FIFO_CFG0 0x0048
248 #define AG71XX_REG_FIFO_CFG1 0x004c
249 #define AG71XX_REG_FIFO_CFG2 0x0050
250 #define AG71XX_REG_FIFO_CFG3 0x0054
251 #define AG71XX_REG_FIFO_CFG4 0x0058
252 #define AG71XX_REG_FIFO_CFG5 0x005c
253 #define AG71XX_REG_FIFO_RAM0 0x0060
254 #define AG71XX_REG_FIFO_RAM1 0x0064
255 #define AG71XX_REG_FIFO_RAM2 0x0068
256 #define AG71XX_REG_FIFO_RAM3 0x006c
257 #define AG71XX_REG_FIFO_RAM4 0x0070
258 #define AG71XX_REG_FIFO_RAM5 0x0074
259 #define AG71XX_REG_FIFO_RAM6 0x0078
260 #define AG71XX_REG_FIFO_RAM7 0x007c
261
262 #define AG71XX_REG_TX_CTRL 0x0180
263 #define AG71XX_REG_TX_DESC 0x0184
264 #define AG71XX_REG_TX_STATUS 0x0188
265 #define AG71XX_REG_RX_CTRL 0x018c
266 #define AG71XX_REG_RX_DESC 0x0190
267 #define AG71XX_REG_RX_STATUS 0x0194
268 #define AG71XX_REG_INT_ENABLE 0x0198
269 #define AG71XX_REG_INT_STATUS 0x019c
270
271 #define AG71XX_REG_FIFO_DEPTH 0x01a8
272 #define AG71XX_REG_RX_SM 0x01b0
273 #define AG71XX_REG_TX_SM 0x01b4
274
275 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
276 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
277 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
278 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
279 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
280 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
281 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
282 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
283
284 #define MAC_CFG2_FDX BIT(0)
285 #define MAC_CFG2_CRC_EN BIT(1)
286 #define MAC_CFG2_PAD_CRC_EN BIT(2)
287 #define MAC_CFG2_LEN_CHECK BIT(4)
288 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
289 #define MAC_CFG2_IF_1000 BIT(9)
290 #define MAC_CFG2_IF_10_100 BIT(8)
291
292 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
293 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
294 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
295 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
296 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
297 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
298 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
299
300 #define FIFO_CFG0_ENABLE_SHIFT 8
301
302 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
303 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
304 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
305 #define FIFO_CFG4_CE BIT(3) /* Code Error */
306 #define FIFO_CFG4_CR BIT(4) /* CRC error */
307 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
308 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
309 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
310 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
311 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
312 #define FIFO_CFG4_DR BIT(10) /* Dribble */
313 #define FIFO_CFG4_LE BIT(11) /* Long Event */
314 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
315 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
316 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
317 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
318 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
319 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
320
321 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
322 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
323 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
324 #define FIFO_CFG5_CE BIT(3) /* Code Error */
325 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
326 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
327 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
328 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
329 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
330 #define FIFO_CFG5_DR BIT(9) /* Dribble */
331 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
332 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
333 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
334 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
335 #define FIFO_CFG5_LE BIT(14) /* Long Event */
336 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
337 #define FIFO_CFG5_16 BIT(16) /* unknown */
338 #define FIFO_CFG5_17 BIT(17) /* unknown */
339 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
340 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
341
342 #define AG71XX_INT_TX_PS BIT(0)
343 #define AG71XX_INT_TX_UR BIT(1)
344 #define AG71XX_INT_TX_BE BIT(3)
345 #define AG71XX_INT_RX_PR BIT(4)
346 #define AG71XX_INT_RX_OF BIT(6)
347 #define AG71XX_INT_RX_BE BIT(7)
348
349 #define MAC_IFCTL_SPEED BIT(16)
350
351 #define MII_CFG_CLK_DIV_4 0
352 #define MII_CFG_CLK_DIV_6 2
353 #define MII_CFG_CLK_DIV_8 3
354 #define MII_CFG_CLK_DIV_10 4
355 #define MII_CFG_CLK_DIV_14 5
356 #define MII_CFG_CLK_DIV_20 6
357 #define MII_CFG_CLK_DIV_28 7
358 #define MII_CFG_CLK_DIV_34 8
359 #define MII_CFG_CLK_DIV_42 9
360 #define MII_CFG_CLK_DIV_50 10
361 #define MII_CFG_CLK_DIV_58 11
362 #define MII_CFG_CLK_DIV_66 12
363 #define MII_CFG_CLK_DIV_74 13
364 #define MII_CFG_CLK_DIV_82 14
365 #define MII_CFG_CLK_DIV_98 15
366 #define MII_CFG_RESET BIT(31)
367
368 #define MII_CMD_WRITE 0x0
369 #define MII_CMD_READ 0x1
370 #define MII_ADDR_SHIFT 8
371 #define MII_IND_BUSY BIT(0)
372 #define MII_IND_INVALID BIT(2)
373
374 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
375
376 #define TX_STATUS_PS BIT(0) /* Packet Sent */
377 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
378 #define TX_STATUS_BE BIT(3) /* Bus Error */
379
380 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
381
382 #define RX_STATUS_PR BIT(0) /* Packet Received */
383 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
384 #define RX_STATUS_BE BIT(3) /* Bus Error */
385
386 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
387 {
388 __raw_writel(value, ag->mac_base + reg);
389 /* flush write */
390 (void) __raw_readl(ag->mac_base + reg);
391 }
392
393 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
394 {
395 return __raw_readl(ag->mac_base + reg);
396 }
397
398 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
399 {
400 void __iomem *r;
401
402 r = ag->mac_base + reg;
403 __raw_writel(__raw_readl(r) | mask, r);
404 /* flush write */
405 (void) __raw_readl(r);
406 }
407
408 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
409 {
410 void __iomem *r;
411
412 r = ag->mac_base + reg;
413 __raw_writel(__raw_readl(r) & ~mask, r);
414 /* flush write */
415 (void) __raw_readl(r);
416 }
417
418 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
419 {
420 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
421 }
422
423 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
424 {
425 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
426 }
427
428 #ifdef CONFIG_AG71XX_DEBUG_FS
429 int ag71xx_debugfs_root_init(void);
430 void ag71xx_debugfs_root_exit(void);
431 int ag71xx_debugfs_init(struct ag71xx *ag);
432 void ag71xx_debugfs_exit(struct ag71xx *ag);
433 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
434 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
435 #else
436 static inline int ag71xx_debugfs_root_init(void) { return 0; }
437 static inline void ag71xx_debugfs_root_exit(void) {}
438 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
439 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
440 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
441 u32 status) {}
442 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
443 int rx, int tx) {}
444 #endif /* CONFIG_AG71XX_DEBUG_FS */
445
446 int ag71xx_ar7240_init(struct ag71xx *ag, struct device_node *np);
447 void ag71xx_ar7240_cleanup(struct ag71xx *ag);
448
449 int ag71xx_setup_gmac(struct device_node *np);
450
451 int ar7240sw_phy_read(struct mii_bus *mii, int addr, int reg);
452 int ar7240sw_phy_write(struct mii_bus *mii, int addr, int reg, u16 val);
453
454 #endif /* _AG71XX_H */